arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         memory {
  67                 device_type = "memory";
  68                 reg = <0x60000000 0x40000000>;
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 enable-method = "rockchip,rk3036-smp";
  75
  76                 cpu0: cpu@f00 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf00>;
  80                         resets = <&cru SRST_CORE0>;
  81                         operating-points = <
  82                                 /* KHz    uV */
  83                                  816000 1000000
  84                         >;
  85                         clock-latency = <40000>;
  86                         clocks = <&cru ARMCLK>;
  87                 };
  88
  89                 cpu1: cpu@f01 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a7";
  92                         reg = <0xf01>;
  93                         resets = <&cru SRST_CORE1>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 pdma: pdma@20078000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0x20078000 0x4000>;
 106                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112         };
 113
 114         arm-pmu {
 115                 compatible = "arm,cortex-a7-pmu";
 116                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 117                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 118                 interrupt-affinity = <&cpu0>, <&cpu1>;
 119         };
 120
 121         timer {
 122                 compatible = "arm,armv7-timer";
 123                 arm,cpu-registers-not-fw-configured;
 124                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 125                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 126                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 128                 clock-frequency = <24000000>;
 129         };
 130
 131         xin24m: oscillator {
 132                 compatible = "fixed-clock";
 133                 clock-frequency = <24000000>;
 134                 clock-output-names = "xin24m";
 135                 #clock-cells = <0>;
 136         };
 137
 138         bus_intmem@10080000 {
 139                 compatible = "mmio-sram";
 140                 reg = <0x10080000 0x2000>;
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 ranges = <0 0x10080000 0x2000>;
 144
 145                 smp-sram@0 {
 146                         compatible = "rockchip,rk3066-smp-sram";
 147                         reg = <0x00 0x10>;
 148                 };
 149         };
 150
 151         gic: interrupt-controller@10139000 {
 152                 compatible = "arm,gic-400";
 153                 interrupt-controller;
 154                 #interrupt-cells = <3>;
 155                 #address-cells = <0>;
 156
 157                 reg = <0x10139000 0x1000>,
 158                       <0x1013a000 0x1000>,
 159                       <0x1013c000 0x2000>,
 160                       <0x1013e000 0x2000>;
 161                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 162         };
 163
 164         usb_otg: usb@10180000 {
 165                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 166                                 "snps,dwc2";
 167                 reg = <0x10180000 0x40000>;
 168                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru HCLK_OTG0>;
 170                 clock-names = "otg";
 171                 dr_mode = "otg";
 172                 g-np-tx-fifo-size = <16>;
 173                 g-rx-fifo-size = <275>;
 174                 g-tx-fifo-size = <256 128 128 64 64 32>;
 175                 g-use-dma;
 176                 status = "disabled";
 177         };
 178
 179         usb_host: usb@101c0000 {
 180                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 181                                 "snps,dwc2";
 182                 reg = <0x101c0000 0x40000>;
 183                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&cru HCLK_OTG1>;
 185                 clock-names = "otg";
 186                 dr_mode = "host";
 187                 status = "disabled";
 188         };
 189
 190         emac: ethernet@10200000 {
 191                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 192                 reg = <0x10200000 0x4000>;
 193                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 rockchip,grf = <&grf>;
 197                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 198                 clock-names = "hclk", "macref", "macclk";
 199                 /*
 200                  * Fix the emac parent clock is DPLL instead of APLL.
 201                  * since that will cause some unstable things if the cpufreq
 202                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 203                  */
 204                 assigned-clocks = <&cru SCLK_MACPLL>;
 205                 assigned-clock-parents = <&cru PLL_DPLL>;
 206                 max-speed = <100>;
 207                 phy-mode = "rmii";
 208                 status = "disabled";
 209         };
 210
 211         sdmmc: dwmmc@10214000 {
 212                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 213                 reg = <0x10214000 0x4000>;
 214                 clock-frequency = <37500000>;
 215                 clock-freq-min-max = <400000 37500000>;
 216                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 217                 clock-names = "biu", "ciu";
 218                 fifo-depth = <0x100>;
 219                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 220                 status = "disabled";
 221         };
 222
 223         sdio: dwmmc@10218000 {
 224                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 225                 reg = <0x10218000 0x4000>;
 226                 clock-freq-min-max = <400000 37500000>;
 227                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 228                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 229                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 230                 fifo-depth = <0x100>;
 231                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 232                 status = "disabled";
 233         };
 234
 235         emmc: dwmmc@1021c000 {
 236                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 237                 reg = <0x1021c000 0x4000>;
 238                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 239                 broken-cd;
 240                 bus-width = <8>;
 241                 cap-mmc-highspeed;
 242                 clock-frequency = <37500000>;
 243                 clock-freq-min-max = <400000 37500000>;
 244                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 245                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 246                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 247                 default-sample-phase = <158>;
 248                 disable-wp;
 249                 dmas = <&pdma 12>;
 250                 dma-names = "rx-tx";
 251                 fifo-depth = <0x100>;
 252                 mmc-ddr-1_8v;
 253                 non-removable;
 254                 num-slots = <1>;
 255                 pinctrl-names = "default";
 256                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 257                 status = "disabled";
 258         };
 259
 260         i2s: i2s@10220000 {
 261                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 262                 reg = <0x10220000 0x4000>;
 263                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 clock-names = "i2s_clk", "i2s_hclk";
 267                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 268                 dmas = <&pdma 0>, <&pdma 1>;
 269                 dma-names = "tx", "rx";
 270                 pinctrl-names = "default";
 271                 pinctrl-0 = <&i2s_bus>;
 272                 status = "disabled";
 273         };
 274
 275         cru: clock-controller@20000000 {
 276                 compatible = "rockchip,rk3036-cru";
 277                 reg = <0x20000000 0x1000>;
 278                 rockchip,grf = <&grf>;
 279                 #clock-cells = <1>;
 280                 #reset-cells = <1>;
 281                 assigned-clocks = <&cru PLL_GPLL>;
 282                 assigned-clock-rates = <594000000>;
 283         };
 284
 285         grf: syscon@20008000 {
 286                 compatible = "rockchip,rk3036-grf", "syscon";
 287                 reg = <0x20008000 0x1000>;
 288         };
 289
 290         acodec: acodec-ana@20030000 {
 291                 compatible = "rk3036-codec";
 292                 reg = <0x20030000 0x4000>;
 293                 rockchip,grf = <&grf>;
 294                 clock-names = "acodec_pclk";
 295                 clocks = <&cru PCLK_ACODEC>;
 296                 status = "disabled";
 297         };
 298
 299         timer: timer@20044000 {
 300                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 301                 reg = <0x20044000 0x20>;
 302                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 304                 clock-names = "timer", "pclk";
 305         };
 306
 307         pwm0: pwm@20050000 {
 308                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 309                 reg = <0x20050000 0x10>;
 310                 #pwm-cells = <3>;
 311                 clocks = <&cru PCLK_PWM>;
 312                 clock-names = "pwm";
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&pwm0_pin>;
 315                 status = "disabled";
 316         };
 317
 318         pwm1: pwm@20050010 {
 319                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 320                 reg = <0x20050010 0x10>;
 321                 #pwm-cells = <3>;
 322                 clocks = <&cru PCLK_PWM>;
 323                 clock-names = "pwm";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&pwm1_pin>;
 326                 status = "disabled";
 327         };
 328
 329         pwm2: pwm@20050020 {
 330                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 331                 reg = <0x20050020 0x10>;
 332                 #pwm-cells = <3>;
 333                 clocks = <&cru PCLK_PWM>;
 334                 clock-names = "pwm";
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&pwm2_pin>;
 337                 status = "disabled";
 338         };
 339
 340         pwm3: pwm@20050030 {
 341                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 342                 reg = <0x20050030 0x10>;
 343                 #pwm-cells = <2>;
 344                 clocks = <&cru PCLK_PWM>;
 345                 clock-names = "pwm";
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&pwm3_pin>;
 348                 status = "disabled";
 349         };
 350
 351         i2c1: i2c@20056000 {
 352                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 353                 reg = <0x20056000 0x1000>;
 354                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clock-names = "i2c";
 358                 clocks = <&cru PCLK_I2C1>;
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2c1_xfer>;
 361                 status = "disabled";
 362         };
 363
 364         i2c2: i2c@2005a000 {
 365                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 366                 reg = <0x2005a000 0x1000>;
 367                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clock-names = "i2c";
 371                 clocks = <&cru PCLK_I2C2>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&i2c2_xfer>;
 374                 status = "disabled";
 375         };
 376
 377         uart0: serial@20060000 {
 378                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 379                 reg = <0x20060000 0x100>;
 380                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 381                 reg-shift = <2>;
 382                 reg-io-width = <4>;
 383                 clock-frequency = <24000000>;
 384                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 385                 clock-names = "baudclk", "apb_pclk";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 388                 status = "disabled";
 389         };
 390
 391         uart1: serial@20064000 {
 392                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 393                 reg = <0x20064000 0x100>;
 394                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 395                 reg-shift = <2>;
 396                 reg-io-width = <4>;
 397                 clock-frequency = <24000000>;
 398                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 399                 clock-names = "baudclk", "apb_pclk";
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&uart1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         uart2: serial@20068000 {
 406                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 407                 reg = <0x20068000 0x100>;
 408                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 409                 reg-shift = <2>;
 410                 reg-io-width = <4>;
 411                 clock-frequency = <24000000>;
 412                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 413                 clock-names = "baudclk", "apb_pclk";
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&uart2_xfer>;
 416                 status = "disabled";
 417         };
 418
 419         i2c0: i2c@20072000 {
 420                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 421                 reg = <0x20072000 0x1000>;
 422                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 clock-names = "i2c";
 426                 clocks = <&cru PCLK_I2C0>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&i2c0_xfer>;
 429                 status = "disabled";
 430         };
 431
 432         spi: spi@20074000 {
 433                 compatible = "rockchip,rockchip-spi";
 434                 reg = <0x20074000 0x1000>;
 435                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 436                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 437                 clock-names = "apb-pclk","spi_pclk";
 438                 dmas = <&pdma 8>, <&pdma 9>;
 439                 dma-names = "tx", "rx";
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 status = "disabled";
 445         };
 446
 447         pinctrl: pinctrl {
 448                 compatible = "rockchip,rk3036-pinctrl";
 449                 rockchip,grf = <&grf>;
 450                 #address-cells = <1>;
 451                 #size-cells = <1>;
 452                 ranges;
 453
 454                 gpio0: gpio0@2007c000 {
 455                         compatible = "rockchip,gpio-bank";
 456                         reg = <0x2007c000 0x100>;
 457                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 458                         clocks = <&cru PCLK_GPIO0>;
 459
 460                         gpio-controller;
 461                         #gpio-cells = <2>;
 462
 463                         interrupt-controller;
 464                         #interrupt-cells = <2>;
 465                 };
 466
 467                 gpio1: gpio1@20080000 {
 468                         compatible = "rockchip,gpio-bank";
 469                         reg = <0x20080000 0x100>;
 470                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&cru PCLK_GPIO1>;
 472
 473                         gpio-controller;
 474                         #gpio-cells = <2>;
 475
 476                         interrupt-controller;
 477                         #interrupt-cells = <2>;
 478                 };
 479
 480                 gpio2: gpio2@20084000 {
 481                         compatible = "rockchip,gpio-bank";
 482                         reg = <0x20084000 0x100>;
 483                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&cru PCLK_GPIO2>;
 485
 486                         gpio-controller;
 487                         #gpio-cells = <2>;
 488
 489                         interrupt-controller;
 490                         #interrupt-cells = <2>;
 491                 };
 492
 493                 pcfg_pull_default: pcfg_pull_default {
 494                         bias-pull-pin-default;
 495                 };
 496
 497                 pcfg_pull_none: pcfg-pull-none {
 498                         bias-disable;
 499                 };
 500
 501                 pwm0 {
 502                         pwm0_pin: pwm0-pin {
 503                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 504                         };
 505                 };
 506
 507                 pwm1 {
 508                         pwm1_pin: pwm1-pin {
 509                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 510                         };
 511                 };
 512
 513                 pwm2 {
 514                         pwm2_pin: pwm2-pin {
 515                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 516                         };
 517                 };
 518
 519                 pwm3 {
 520                         pwm3_pin: pwm3-pin {
 521                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 522                         };
 523                 };
 524
 525                 sdmmc {
 526                         sdmmc_clk: sdmmc-clk {
 527                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 528                         };
 529
 530                         sdmmc_cmd: sdmmc-cmd {
 531                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 532                         };
 533
 534                         sdmmc_cd: sdmcc-cd {
 535                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 536                         };
 537
 538                         sdmmc_bus1: sdmmc-bus1 {
 539                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 540                         };
 541
 542                         sdmmc_bus4: sdmmc-bus4 {
 543                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 544                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 545                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 546                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 547                         };
 548                 };
 549
 550                 sdio {
 551                         sdio_bus1: sdio-bus1 {
 552                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 553                         };
 554
 555                         sdio_bus4: sdio-bus4 {
 556                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 557                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 558                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 559                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 560                         };
 561
 562                         sdio_cmd: sdio-cmd {
 563                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 564                         };
 565
 566                         sdio_clk: sdio-clk {
 567                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 568                         };
 569                 };
 570
 571                 emmc {
 572                         /*
 573                          * We run eMMC at max speed; bump up drive strength.
 574                          * We also have external pulls, so disable the internal ones.
 575                          */
 576                         emmc_clk: emmc-clk {
 577                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 578                         };
 579
 580                         emmc_cmd: emmc-cmd {
 581                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 582                         };
 583
 584                         emmc_bus8: emmc-bus8 {
 585                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 586                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 587                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 588                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 589                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 590                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 591                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 592                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 593                         };
 594                 };
 595
 596                 emac {
 597                         emac_xfer: emac-xfer {
 598                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 599                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 600                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 601                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 602                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 603                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 604                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 605                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 606                         };
 607
 608                         emac_mdio: emac-mdio {
 609                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 610                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 611                         };
 612                 };
 613
 614                 i2c0 {
 615                         i2c0_xfer: i2c0-xfer {
 616                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 617                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 618                         };
 619                 };
 620
 621                 i2c1 {
 622                         i2c1_xfer: i2c1-xfer {
 623                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 624                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 625                         };
 626                 };
 627
 628                 i2c2 {
 629                         i2c2_xfer: i2c2-xfer {
 630                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 631                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 632                         };
 633                 };
 634
 635                 i2s {
 636                         i2s_bus: i2s-bus {
 637                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 638                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 639                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 640                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 641                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 642                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 643                         };
 644                 };
 645
 646                 uart0 {
 647                         uart0_xfer: uart0-xfer {
 648                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 649                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 650                         };
 651
 652                         uart0_cts: uart0-cts {
 653                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 654                         };
 655
 656                         uart0_rts: uart0-rts {
 657                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 658                         };
 659                 };
 660
 661                 uart1 {
 662                         uart1_xfer: uart1-xfer {
 663                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 664                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 665                         };
 666                         /* no rts / cts for uart1 */
 667                 };
 668
 669                 uart2 {
 670                         uart2_xfer: uart2-xfer {
 671                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 672                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 673                         };
 674                         /* no rts / cts for uart2 */
 675                 };
 676
 677                 spi {
 678                         spi_txd:spi-txd {
 679                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 680                         };
 681
 682                         spi_rxd:spi-rxd {
 683                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 684                         };
 685
 686                         spi_clk:spi-clk {
 687                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 688                         };
 689
 690                         spi_cs0:spi-cs0 {
 691                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 692
 693                         };
 694
 695                         spi_cs1:spi-cs1 {
 696                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 697
 698                         };
 699                 };
 700         };
 701 };