2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
69 enable-method = "rockchip,rk3036-smp";
73 compatible = "arm,cortex-a7";
75 resets = <&cru SRST_CORE0>;
80 clock-latency = <40000>;
81 clocks = <&cru ARMCLK>;
86 compatible = "arm,cortex-a7";
88 resets = <&cru SRST_CORE1>;
93 compatible = "arm,amba-bus";
99 compatible = "arm,pl330", "arm,primecell";
100 reg = <0x20078000 0x4000>;
101 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&cru ACLK_DMAC2>;
105 clock-names = "apb_pclk";
110 compatible = "arm,cortex-a7-pmu";
111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
113 interrupt-affinity = <&cpu0>, <&cpu1>;
117 compatible = "rockchip,display-subsystem";
122 compatible = "arm,armv7-timer";
123 arm,cpu-registers-not-fw-configured;
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
125 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
126 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
128 clock-frequency = <24000000>;
132 compatible = "fixed-clock";
133 clock-frequency = <24000000>;
134 clock-output-names = "xin24m";
138 bus_intmem@10080000 {
139 compatible = "mmio-sram";
140 reg = <0x10080000 0x2000>;
141 #address-cells = <1>;
143 ranges = <0 0x10080000 0x2000>;
146 compatible = "rockchip,rk3066-smp-sram";
152 compatible = "rockchip,rk3036-vop";
153 reg = <0x10118000 0x19c>;
154 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
156 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
157 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
158 reset-names = "axi", "ahb", "dclk";
163 #address-cells = <1>;
165 vop_out_hdmi: endpoint@0 {
167 remote-endpoint = <&hdmi_in_vop>;
172 vop_mmu: iommu@10118300 {
173 compatible = "rockchip,iommu";
174 reg = <0x10118300 0x100>;
175 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "vop_mmu";
181 gic: interrupt-controller@10139000 {
182 compatible = "arm,gic-400";
183 interrupt-controller;
184 #interrupt-cells = <3>;
185 #address-cells = <0>;
187 reg = <0x10139000 0x1000>,
191 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
194 usb_otg: usb@10180000 {
195 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
197 reg = <0x10180000 0x40000>;
198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru HCLK_OTG0>;
202 g-np-tx-fifo-size = <16>;
203 g-rx-fifo-size = <275>;
204 g-tx-fifo-size = <256 128 128 64 64 32>;
209 usb_host: usb@101c0000 {
210 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
212 reg = <0x101c0000 0x40000>;
213 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru HCLK_OTG1>;
220 emac: ethernet@10200000 {
221 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
222 reg = <0x10200000 0x4000>;
223 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>;
226 rockchip,grf = <&grf>;
227 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
228 clock-names = "hclk", "macref", "macclk";
230 * Fix the emac parent clock is DPLL instead of APLL.
231 * since that will cause some unstable things if the cpufreq
232 * is working. (e.g: the accurate 50MHz what mac_ref need)
234 assigned-clocks = <&cru SCLK_MACPLL>;
235 assigned-clock-parents = <&cru PLL_DPLL>;
241 sdmmc: dwmmc@10214000 {
242 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
243 reg = <0x10214000 0x4000>;
244 clock-frequency = <37500000>;
245 clock-freq-min-max = <400000 37500000>;
246 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
247 clock-names = "biu", "ciu";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
253 sdio: dwmmc@10218000 {
254 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
255 reg = <0x10218000 0x4000>;
256 clock-freq-min-max = <400000 37500000>;
257 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
258 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
259 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
265 emmc: dwmmc@1021c000 {
266 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
267 reg = <0x1021c000 0x4000>;
268 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
271 clock-frequency = <37500000>;
272 clock-freq-min-max = <400000 37500000>;
273 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
274 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
275 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
276 default-sample-phase = <158>;
280 fifo-depth = <0x100>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
290 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
291 reg = <0x10220000 0x4000>;
292 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
293 #address-cells = <1>;
295 clock-names = "i2s_clk", "i2s_hclk";
296 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
297 dmas = <&pdma 0>, <&pdma 1>;
298 dma-names = "tx", "rx";
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2s_bus>;
304 cru: clock-controller@20000000 {
305 compatible = "rockchip,rk3036-cru";
306 reg = <0x20000000 0x1000>;
307 rockchip,grf = <&grf>;
310 assigned-clocks = <&cru PLL_GPLL>;
311 assigned-clock-rates = <594000000>;
314 grf: syscon@20008000 {
315 compatible = "rockchip,rk3036-grf", "syscon";
316 reg = <0x20008000 0x1000>;
319 acodec: acodec-ana@20030000 {
320 compatible = "rk3036-codec";
321 reg = <0x20030000 0x4000>;
322 rockchip,grf = <&grf>;
323 clock-names = "acodec_pclk";
324 clocks = <&cru PCLK_ACODEC>;
328 hdmi: hdmi@20034000 {
329 compatible = "rockchip,rk3036-inno-hdmi";
330 reg = <0x20034000 0x4000>;
331 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cru PCLK_HDMI>;
333 clock-names = "pclk";
334 rockchip,grf = <&grf>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&hdmi_ctl>;
340 #address-cells = <1>;
342 hdmi_in_vop: endpoint@0 {
344 remote-endpoint = <&vop_out_hdmi>;
349 timer: timer@20044000 {
350 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
351 reg = <0x20044000 0x20>;
352 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&xin24m>, <&cru PCLK_TIMER>;
354 clock-names = "timer", "pclk";
358 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
359 reg = <0x20050000 0x10>;
361 clocks = <&cru PCLK_PWM>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pwm0_pin>;
369 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
370 reg = <0x20050010 0x10>;
372 clocks = <&cru PCLK_PWM>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&pwm1_pin>;
380 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
381 reg = <0x20050020 0x10>;
383 clocks = <&cru PCLK_PWM>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pwm2_pin>;
391 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
392 reg = <0x20050030 0x10>;
394 clocks = <&cru PCLK_PWM>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pwm3_pin>;
402 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
403 reg = <0x20056000 0x1000>;
404 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
405 #address-cells = <1>;
408 clocks = <&cru PCLK_I2C1>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c1_xfer>;
415 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
416 reg = <0x2005a000 0x1000>;
417 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
421 clocks = <&cru PCLK_I2C2>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c2_xfer>;
427 uart0: serial@20060000 {
428 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
429 reg = <0x20060000 0x100>;
430 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
433 clock-frequency = <24000000>;
434 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
435 clock-names = "baudclk", "apb_pclk";
436 pinctrl-names = "default";
437 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
441 uart1: serial@20064000 {
442 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
443 reg = <0x20064000 0x100>;
444 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
447 clock-frequency = <24000000>;
448 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
449 clock-names = "baudclk", "apb_pclk";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart1_xfer>;
455 uart2: serial@20068000 {
456 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
457 reg = <0x20068000 0x100>;
458 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
461 clock-frequency = <24000000>;
462 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
463 clock-names = "baudclk", "apb_pclk";
464 pinctrl-names = "default";
465 pinctrl-0 = <&uart2_xfer>;
470 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
471 reg = <0x20072000 0x1000>;
472 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
476 clocks = <&cru PCLK_I2C0>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c0_xfer>;
483 compatible = "rockchip,rockchip-spi";
484 reg = <0x20074000 0x1000>;
485 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
486 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
487 clock-names = "apb-pclk","spi_pclk";
488 dmas = <&pdma 8>, <&pdma 9>;
489 dma-names = "tx", "rx";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
492 #address-cells = <1>;
498 compatible = "rockchip,rk3036-pinctrl";
499 rockchip,grf = <&grf>;
500 #address-cells = <1>;
504 gpio0: gpio0@2007c000 {
505 compatible = "rockchip,gpio-bank";
506 reg = <0x2007c000 0x100>;
507 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru PCLK_GPIO0>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
517 gpio1: gpio1@20080000 {
518 compatible = "rockchip,gpio-bank";
519 reg = <0x20080000 0x100>;
520 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cru PCLK_GPIO1>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
530 gpio2: gpio2@20084000 {
531 compatible = "rockchip,gpio-bank";
532 reg = <0x20084000 0x100>;
533 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cru PCLK_GPIO2>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
543 pcfg_pull_default: pcfg_pull_default {
544 bias-pull-pin-default;
547 pcfg_pull_none: pcfg-pull-none {
553 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
559 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
565 rockchip,pins = <0 1 2 &pcfg_pull_none>;
571 rockchip,pins = <0 27 1 &pcfg_pull_none>;
576 sdmmc_clk: sdmmc-clk {
577 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
580 sdmmc_cmd: sdmmc-cmd {
581 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
585 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
588 sdmmc_bus1: sdmmc-bus1 {
589 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
592 sdmmc_bus4: sdmmc-bus4 {
593 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
594 <1 19 RK_FUNC_1 &pcfg_pull_default>,
595 <1 20 RK_FUNC_1 &pcfg_pull_default>,
596 <1 21 RK_FUNC_1 &pcfg_pull_default>;
601 sdio_bus1: sdio-bus1 {
602 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
605 sdio_bus4: sdio-bus4 {
606 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
607 <0 12 RK_FUNC_1 &pcfg_pull_default>,
608 <0 13 RK_FUNC_1 &pcfg_pull_default>,
609 <0 14 RK_FUNC_1 &pcfg_pull_default>;
613 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
617 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
623 * We run eMMC at max speed; bump up drive strength.
624 * We also have external pulls, so disable the internal ones.
627 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
631 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
634 emmc_bus8: emmc-bus8 {
635 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
636 <1 25 RK_FUNC_2 &pcfg_pull_default>,
637 <1 26 RK_FUNC_2 &pcfg_pull_default>,
638 <1 27 RK_FUNC_2 &pcfg_pull_default>,
639 <1 28 RK_FUNC_2 &pcfg_pull_default>,
640 <1 29 RK_FUNC_2 &pcfg_pull_default>,
641 <1 30 RK_FUNC_2 &pcfg_pull_default>,
642 <1 31 RK_FUNC_2 &pcfg_pull_default>;
647 emac_xfer: emac-xfer {
648 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
649 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
650 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
651 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
652 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
653 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
654 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
655 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
658 emac_mdio: emac-mdio {
659 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
660 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
665 i2c0_xfer: i2c0-xfer {
666 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
667 <0 1 RK_FUNC_1 &pcfg_pull_none>;
672 i2c1_xfer: i2c1-xfer {
673 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
674 <0 3 RK_FUNC_1 &pcfg_pull_none>;
679 i2c2_xfer: i2c2-xfer {
680 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
681 <2 21 RK_FUNC_1 &pcfg_pull_none>;
687 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
688 <1 1 RK_FUNC_1 &pcfg_pull_default>,
689 <1 2 RK_FUNC_1 &pcfg_pull_default>,
690 <1 3 RK_FUNC_1 &pcfg_pull_default>,
691 <1 4 RK_FUNC_1 &pcfg_pull_default>,
692 <1 5 RK_FUNC_1 &pcfg_pull_default>;
698 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
699 <1 9 RK_FUNC_1 &pcfg_pull_none>,
700 <1 10 RK_FUNC_1 &pcfg_pull_none>,
701 <1 11 RK_FUNC_1 &pcfg_pull_none>;
706 uart0_xfer: uart0-xfer {
707 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
708 <0 17 RK_FUNC_1 &pcfg_pull_none>;
711 uart0_cts: uart0-cts {
712 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
715 uart0_rts: uart0-rts {
716 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
721 uart1_xfer: uart1-xfer {
722 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
723 <2 23 RK_FUNC_1 &pcfg_pull_none>;
725 /* no rts / cts for uart1 */
729 uart2_xfer: uart2-xfer {
730 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
731 <1 19 RK_FUNC_2 &pcfg_pull_none>;
733 /* no rts / cts for uart2 */
738 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
742 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
746 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
750 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
755 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;