1 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include "skeleton.dtsi"
4 #include "rk3036-clocks.dtsi"
7 compatible = "rockchip,rk3036";
8 rockchip,sram = <&sram>;
9 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a7";
32 compatible = "arm,cortex-a7";
37 gic: interrupt-controller@10139000 {
38 compatible = "arm,cortex-a15-gic";
40 #interrupt-cells = <3>;
42 reg = <0x10139000 0x1000>,
47 compatible = "arm,cortex-a7-pmu";
48 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
53 compatible = "mmio-sram";
54 reg = <0x10080000 0x2000>;
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
62 clock-frequency = <24000000>;
65 watchdog: wdt@2004c000 {
66 compatible = "rockchip,watch dog";
67 reg = <0x2004c000 0x100>;
68 clocks = <&clk_gates7 15>;
69 clock-names = "pclk_wdt";
70 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
72 rockchip,timeout = <60>;
73 rockchip,atboot = <1>;
81 compatible = "arm,amba-bus";
82 interrupt-parent = <&gic>;
86 compatible = "arm,pl330", "arm,primecell";
87 reg = <0x20078000 0x4000>;
88 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
94 nandc: nandc@10500000 {
95 compatible = "rockchip,rk-nandc";
96 reg = <0x10500000 0x4000>;
97 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&clk_nandc>, <&clk_gates5 9>;
100 clock-names = "clk_nandc", "hclk_nandc";
104 compatible = "rockchip,rockchip-spi";
105 reg = <0x20074000 0x1000>;
106 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
107 #address-cells = <1>;
109 //pinctrl-names = "default";
110 //pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
111 rockchip,spi-src-clk = <0>;
113 //clocks =<&clk_spi0>, <&clk_gates7 12>;
114 //clock-names = "spi","pclk_spi0";
115 //dmas = <&pdma 8>, <&pdma 9>;
117 //dma-names = "tx", "rx";
121 uart0: serial@20060000 {
122 compatible = "rockchip,serial";
123 reg = <0x20060000 0x100>;
124 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
125 clock-frequency = <24000000>;
126 clocks = <&clk_uart0>, <&clk_gates8 0>;
127 clock-names = "sclk_uart", "pclk_uart";
130 dmas = <&pdma 2>, <&pdma 3>;
132 //pinctrl-names = "default";
133 //pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
137 uart1: serial@20064000 {
138 compatible = "rockchip,serial";
139 reg = <0x20064000 0x100>;
140 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
141 clock-frequency = <24000000>;
142 clocks = <&clk_uart1>, <&clk_gates8 1>;
143 clock-names = "sclk_uart", "pclk_uart";
146 dmas = <&pdma 4>, <&pdma 5>;
148 //pinctrl-names = "default";
149 //pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
153 uart2: serial@20068000 {
154 compatible = "rockchip,serial";
155 reg = <0x20068000 0x100>;
156 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
157 clock-frequency = <24000000>;
158 clocks = <&clk_uart2>, <&clk_gates8 2>;
159 clock-names = "sclk_uart", "pclk_uart";
162 dmas = <&pdma 6>, <&pdma 7>;
164 //pinctrl-names = "default";
165 //pinctrl-0 = <&uart2_xfer>;
170 compatible = "rockchip,fiq-debugger";
171 rockchip,serial-id = <2>;
172 rockchip,signal-irq = <106>;
173 rockchip,wake-irq = <0>;
178 compatible = "rockchip,rk30-i2c";
179 reg = <0x20072000 0x1000>;
180 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
181 #address-cells = <1>;
183 //pinctrl-names = "default", "gpio";
184 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
185 //pinctrl-1 = <&i2c0_gpio>;
186 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
187 clocks = <&clk_gates8 4>;
188 rockchip,check-idle = <1>;
193 compatible = "rockchip,rk30-i2c";
194 reg = <0x20056000 0x1000>;
195 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
198 //pinctrl-names = "default", "gpio";
199 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
200 //pinctrl-1 = <&i2c1_gpio>;
201 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
202 clocks = <&clk_gates8 5>;
203 rockchip,check-idle = <1>;
208 compatible = "rockchip,rk30-i2c";
209 reg = <0x2005a000 0x1000>;
210 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
213 //pinctrl-names = "default", "gpio";
214 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
215 //pinctrl-1 = <&i2c2_gpio>;
216 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
217 clocks = <&clk_gates8 6>;
218 rockchip,check-idle = <1>;
223 compatible = "rockchip-i2s";
224 reg = <0x10220000 0x1000>;
226 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
227 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
228 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
229 dmas = <&pdma 0>, <&pdma 1>;
231 dma-names = "tx", "rx";
232 //pinctrl-names = "default", "sleep";
233 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
234 //pinctrl-1 = <&i2s_gpio>;
237 spdif: spdif@10204000 {
238 compatible = "rockchip-spdif";
239 reg = <0x10204000 0x1000>;
240 clocks = <&clk_spdif>;
241 clock-names = "spdif_mclk";
242 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
246 //pinctrl-names = "default";
247 //pinctrl-0 = <&spdif_tx>;
251 compatible = "rockchip,rk-pwm";
252 reg = <0x20050000 0x10>;
254 //pinctrl-names = "default";
255 //pinctrl-0 = <&pwm_pin>;
256 clocks = <&clk_gates7 10>;
257 clock-names = "pclk_pwm";
261 emmc: rksdmmc@1021c000 {
262 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
263 reg = <0x1021c000 0x4000>;
264 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
267 //pinctrl-names = "default",,"suspend";
268 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
269 clocks = <&clk_emmc>, <&clk_gates7 0>;
270 clock-names = "clk_mmc", "hclk_mmc";
272 fifo-depth = <0x100>;
277 sdmmc: rksdmmc@10214000 {
278 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
279 reg = <0x10214000 0x4000>;
280 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
283 //pinctrl-names = "default", "idle";
284 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
285 //pinctrl-1 = <&sdmmc0_gpio>;
286 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
287 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
288 clock-names = "clk_mmc", "hclk_mmc";
290 fifo-depth = <0x100>;
294 sdio: rksdmmc@10218000 {
295 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
296 reg = <0x10218000 0x4000>;
297 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
298 #address-cells = <1>;
300 //pinctrl-names = "default","idle";
301 //pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
302 //pinctrl-1 = <&sdio_gpio>;
303 clocks = <&clk_sdio>, <&clk_gates5 11>;
304 clock-names = "clk_mmc", "hclk_mmc";
306 fifo-depth = <0x100>;