arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3036";
   9         rockchip,sram = <&sram>;
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17                 i2c1 = &i2c1;
  18                 i2c2 = &i2c2;
  19                 spi0 = &spi0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0xf00>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf01>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@10139000 {
  39                 compatible = "arm,cortex-a15-gic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <3>;
  42                 #address-cells = <0>;
  43                 reg = <0x10139000 0x1000>,
  44                       <0x1013a000 0x1000>;
  45         };
  46
  47         arm-pmu {
  48                 compatible = "arm,cortex-a7-pmu";
  49                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         sram: sram@10080000 {
  54                 compatible = "mmio-sram";
  55                 reg = <0x10080000 0x2000>;
  56                 map-exec;
  57         };
  58
  59         timer {
  60                 compatible = "arm,armv7-timer";
  61                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  63                 clock-frequency = <24000000>;
  64         };
  65
  66         watchdog: wdt@2004c000 {
  67                 compatible = "rockchip,watch dog";
  68                 reg = <0x2004c000 0x100>;
  69                 clocks = <&clk_gates7 15>;
  70                 clock-names = "pclk_wdt";
  71                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  72                 rockchip,irq = <1>;
  73                 rockchip,timeout = <60>;
  74                 rockchip,atboot = <1>;
  75                 rockchip,debug = <0>;
  76                 status = "disabled";
  77         };
  78
  79         amba {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "arm,amba-bus";
  83                 interrupt-parent = <&gic>;
  84                 ranges;
  85
  86                 pdma: pdma@20078000 {
  87                         compatible = "arm,pl330", "arm,primecell";
  88                         reg = <0x20078000 0x4000>;
  89                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  91                         #dma-cells = <1>;
  92                 };
  93         };
  94
  95         reset: reset@20000110{
  96                 compatible = "rockchip,reset";
  97                 reg = <0x20000110 0x24>;
  98                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
  99                 #reset-cells = <1>;
 100         };
 101
 102         nandc: nandc@10500000 {
 103                 compatible = "rockchip,rk-nandc";
 104                 reg = <0x10500000 0x4000>;
 105                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 106                 //pinctrl-names = "default";
 107                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 108                 nandc_id = <0>;
 109                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
 110                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 111         };
 112
 113         nandc0reg: nandc0@10500000 {
 114                 compatible = "rockchip,rk-nandc";
 115                 reg = <0x10500000 0x4000>;
 116         };
 117
 118         spi0: spi@20074000 {
 119                 compatible = "rockchip,rockchip-spi";
 120                 reg = <0x20074000 0x1000>;
 121                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 126                 rockchip,spi-src-clk = <0>;
 127                 num-cs = <2>;
 128                 clocks =<&clk_spi0>, <&clk_gates2 9>;
 129                 clock-names = "spi","pclk_spi0";
 130                 dmas = <&pdma 8>, <&pdma 9>;
 131                 #dma-cells = <2>;
 132                 dma-names = "tx", "rx";
 133                 status = "disabled";
 134         };
 135
 136         uart0: serial@20060000 {
 137                 compatible = "rockchip,serial";
 138                 reg = <0x20060000 0x100>;
 139                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 140                 clock-frequency = <24000000>;
 141                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 142                 clock-names = "sclk_uart", "pclk_uart";
 143                 reg-shift = <2>;
 144                 reg-io-width = <4>;
 145                 dmas = <&pdma 2>, <&pdma 3>;
 146                 #dma-cells = <2>;
 147                 pinctrl-names = "default";
 148                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 149                 status = "disabled";
 150         };
 151
 152         uart1: serial@20064000 {
 153                 compatible = "rockchip,serial";
 154                 reg = <0x20064000 0x100>;
 155                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 156                 clock-frequency = <24000000>;
 157                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 158                 clock-names = "sclk_uart", "pclk_uart";
 159                 reg-shift = <2>;
 160                 reg-io-width = <4>;
 161                 dmas = <&pdma 4>, <&pdma 5>;
 162                 #dma-cells = <2>;
 163                 pinctrl-names = "default";
 164                 pinctrl-0 = <&uart1_xfer>;
 165                 status = "disabled";
 166         };
 167
 168         uart2: serial@20068000 {
 169                 compatible = "rockchip,serial";
 170                 reg = <0x20068000 0x100>;
 171                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 172                 clock-frequency = <24000000>;
 173                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 174                 clock-names = "sclk_uart", "pclk_uart";
 175                 reg-shift = <2>;
 176                 reg-io-width = <4>;
 177                 dmas = <&pdma 6>, <&pdma 7>;
 178                 #dma-cells = <2>;
 179                 pinctrl-names = "default";
 180                 pinctrl-0 = <&uart2_xfer>;
 181                 status = "disabled";
 182         };
 183
 184         fiq-debugger {
 185                 compatible = "rockchip,fiq-debugger";
 186                 rockchip,serial-id = <2>;
 187                 rockchip,signal-irq = <106>;
 188                 rockchip,wake-irq = <0>;
 189                 status = "disabled";
 190         };
 191
 192         clocks-init{
 193                 compatible = "rockchip,clocks-init";
 194                 rockchip,clocks-init-parent =
 195                         <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 196                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 197                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 198                         <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
 199                         <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
 200                 rockchip,clocks-init-rate =
 201                         <&clk_core 816000000>, <&clk_gpll 594000000>,
 202                         <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
 203                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
 204                         <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
 205                         <&clk_gpu_pre 300000000>,        <&aclk_vio_pre 300000000>,
 206                         <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
 207                         <&clk_hevc_core 300000000>, <&clk_mac_ref_div 50000000>;
 208         /*      rockchip,clocks-uboot-has-init =
 209                         <&aclk_vio1>;*/
 210         };
 211
 212         clocks-enable {
 213                 compatible = "rockchip,clocks-enable";
 214                 clocks =
 215                                 /*PD_CORE*/
 216                                 <&clk_gates0 0>, <&clk_gates0 7>,
 217
 218                                 /*PD_CPU*/
 219                                 <&clk_gates0 3>, <&clk_gates0 4>,
 220                                 <&clk_gates0 5>,
 221
 222                                 /*TIMER*/
 223                                 <&clk_gates1 0>, <&clk_gates1 1>,
 224                                 <&clk_gates2 4>, <&clk_gates2 5>,
 225
 226                                 /*PD_PERI*/
 227                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 228                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 229
 230                                 /*aclk_cpu_pre*/
 231                                 <&clk_gates4 12>,/*aclk_intmem*/
 232                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 233
 234                                 /*hclk_cpu_pre*/
 235                                 <&clk_gates5 6>,/*hclk_rom*/
 236
 237                                 /*pclk_cpu_pre*/
 238                                 <&clk_gates5 4>,/*pclk_grf*/
 239                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 240                                 <&clk_gates5 14>,/*pclk_acodec*/
 241                                 <&clk_gates3 8>,/*pclk_hdmi*/
 242
 243                                 /*aclk_peri_pre*/
 244                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 245                                 <&clk_gates5 1>,/*aclk_dmac2*/
 246                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 247                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 248
 249                                 /*hclk_peri_pre*/
 250                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 251                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 252                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 253
 254                                 /*pclk_peri_pre*/
 255                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 256
 257                                 /*hclk_vio_pre*/
 258                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 259                                 <&clk_gates9 5>,/*hclk_lcdc*/
 260
 261                                 /*aclk_vio_pre*/
 262                                 <&clk_gates6 13>,/*aclk_vio*/
 263                                 <&clk_gates9 6>,/*aclk_lcdc*/
 264
 265                                 /*UART*/
 266                                 <&clk_gates1 12>,
 267                                 <&clk_gates1 13>,
 268                                 <&clk_gates8 2>,/*pclk_uart2*/
 269
 270                                 <&clk_gpu_pre>,
 271
 272                                 /*jtag*/
 273                                 <&clk_gates1 3>;/*clk_jtag*/
 274         };
 275
 276         i2c0: i2c@20072000 {
 277                 compatible = "rockchip,rk30-i2c";
 278                 reg = <0x20072000 0x1000>;
 279                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 pinctrl-names = "default", "gpio";
 283                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 284                 pinctrl-1 = <&i2c0_gpio>;
 285                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 286                 clocks = <&clk_gates8 4>;
 287                 rockchip,check-idle = <1>;
 288                 status = "disabled";
 289         };
 290
 291         i2c1: i2c@20056000 {
 292                 compatible = "rockchip,rk30-i2c";
 293                 reg = <0x20056000 0x1000>;
 294                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 pinctrl-names = "default", "gpio";
 298                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 299                 pinctrl-1 = <&i2c1_gpio>;
 300                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 301                 clocks = <&clk_gates8 5>;
 302                 rockchip,check-idle = <1>;
 303                 status = "disabled";
 304         };
 305
 306         i2c2: i2c@2005a000 {
 307                 compatible = "rockchip,rk30-i2c";
 308                 reg = <0x2005a000 0x1000>;
 309                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 pinctrl-names = "default", "gpio";
 313                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 314                 pinctrl-1 = <&i2c2_gpio>;
 315                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 316                 clocks = <&clk_gates8 6>;
 317                 rockchip,check-idle = <1>;
 318                 status = "disabled";
 319         };
 320
 321         i2s: i2s@10220000 {
 322                 compatible = "rockchip-i2s";
 323                 reg = <0x10220000 0x1000>;
 324                 i2s-id = <0>;
 325                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 326                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 327                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 328                 dmas = <&pdma 0>, <&pdma 1>;
 329                 //#dma-cells = <2>;
 330                 dma-names = "tx", "rx";
 331                 //pinctrl-names = "default", "sleep";
 332                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 333                 //pinctrl-1 = <&i2s_gpio>;
 334         };
 335
 336         spdif: spdif@10204000 {
 337                 compatible = "rockchip-spdif";
 338                 reg = <0x10204000 0x1000>;
 339                 clocks = <&clk_spdif>;
 340                 clock-names = "spdif_mclk";
 341                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 342                 dmas = <&pdma 13>;
 343                 //#dma-cells = <1>;
 344                 dma-names = "tx";
 345                 //pinctrl-names = "default";
 346                 //pinctrl-0 = <&spdif_tx>;
 347         };
 348
 349         pwm0: pwm@20050000 {
 350                 compatible = "rockchip,rk-pwm";
 351                 reg = <0x20050000 0x10>;
 352                 #pwm-cells = <2>;
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&pwm0_pin>;
 355                 clocks = <&clk_gates7 10>;
 356                 clock-names = "pclk_pwm";
 357                 status = "disabled";
 358         };
 359
 360         pwm1: pwm@20050010 {
 361                 compatible = "rockchip,rk-pwm";
 362                 reg = <0x20050010 0x10>;
 363                 #pwm-cells = <2>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&pwm1_pin>;
 366                 clocks = <&clk_gates7 10>;
 367                 clock-names = "pclk_pwm";
 368                 status = "disabled";
 369         };
 370
 371         pwm2: pwm@20050020 {
 372                 compatible = "rockchip,rk-pwm";
 373                 reg = <0x20050020 0x10>;
 374                 #pwm-cells = <2>;
 375                 pinctrl-names = "default";
 376                 pinctrl-0 = <&pwm2_pin>;
 377                 clocks = <&clk_gates7 10>;
 378                 clock-names = "pclk_pwm";
 379                 status = "disabled";
 380         };
 381
 382         pwm3: pwm@20050030 {
 383                 compatible = "rockchip,rk-pwm";
 384                 reg = <0x20050030 0x10>;
 385                 #pwm-cells = <2>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pwm3_pin>;
 388                 clocks = <&clk_gates7 10>;
 389                 clock-names = "pclk_pwm";
 390                 status = "disabled";
 391         };
 392
 393         emmc: rksdmmc@1021c000 {
 394                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 395                 reg = <0x1021c000 0x4000>;
 396                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 //pinctrl-names = "default",,"suspend";
 400                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 401                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 402                 clock-names = "clk_mmc", "hclk_mmc";
 403                 dmas = <&pdma 12>;
 404                 dma-names = "dw_mci";
 405                 num-slots = <1>;
 406                 fifo-depth = <0x100>;
 407                 bus-width = <8>;
 408         };
 409
 410
 411         sdmmc: rksdmmc@10214000 {
 412                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 413                 reg = <0x10214000 0x4000>;
 414                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 pinctrl-names = "default", "idle";
 418                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 419                 pinctrl-1 = <&sdmmc0_gpio>;
 420                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 421                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 422                 clock-names = "clk_mmc", "hclk_mmc";
 423                 dmas = <&pdma 10>;
 424                 dma-names = "dw_mci";
 425                 num-slots = <1>;
 426                 fifo-depth = <0x100>;
 427                 bus-width = <4>;
 428         };
 429
 430         sdio: rksdmmc@10218000 {
 431                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 432                 reg = <0x10218000 0x4000>;
 433                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 pinctrl-names = "default","idle";
 437                 pinctrl-0 = <&sdio0_clk &sdio0_cmd  &sdio0_bus4>;
 438                 pinctrl-1 = <&sdio0_gpio>;
 439                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 440                 clock-names = "clk_mmc", "hclk_mmc";
 441                 dmas = <&pdma 11>;
 442                 dma-names = "dw_mci";
 443                 num-slots = <1>;
 444                 fifo-depth = <0x100>;
 445                 bus-width = <4>;
 446         };
 447         gpu {
 448                 compatible = "arm,mali400";
 449                 reg = <0x10091000 0x200>,
 450                           <0x10090000 0x100>,
 451                           <0x10093000 0x100>,
 452                           <0x10098000 0x1100>,
 453                           <0x10094000 0x100>;
 454                 reg-names = "Mali_L2",
 455                                         "Mali_GP",
 456                                         "Mali_GP_MMU",
 457                                         "Mali_PP0",
 458                                         "Mali_PP0_MMU";
 459
 460             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 461                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 463                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 464             interrupt-names = "Mali_GP_IRQ",
 465                                                   "Mali_GP_MMU_IRQ",
 466                                                   "Mali_PP0_IRQ",
 467                                                   "Mali_PP0_MMU_IRQ";
 468           };
 469         dwc_control_usb: dwc-control-usb@20008000 {
 470                 compatible = "rockchip,rk3036-dwc-control-usb";
 471                 reg = <0x20008000 0x4>;
 472                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 473                 interrupt-names = "otg_bvalid";
 474                 clocks = <&clk_gates9 13>;
 475                 clock-names = "hclk_usb_peri";
 476                 rockchip,remote_wakeup;
 477                 rockchip,usb_irq_wakeup;
 478                 resets = <&reset RK3036_RST_USBPOR>;
 479                 reset-names = "usbphy_por";
 480                 usb_bc{
 481                         compatible = "rockchip,ctrl";
 482                         rk_usb,bvalid   = <0x14c 8 1>;
 483                         rk_usb,iddig    = <0x14c 11 1>;
 484                         rk_usb,line     = <0x14c 9 2>;
 485                         rk_usb,softctrl = <0x17c 0 1>;
 486                         rk_usb,opmode   = <0x17c 2 2>;
 487                         rk_usb,xcvrsel  = <0x17c 4 2>;
 488                         rk_usb,termsel  = <0x17c 6 1>;
 489                 };
 490         };
 491         usb0: usb@10180000 {
 492                 compatible = "rockchip,rk3036_usb20_otg";
 493                 reg = <0x10180000 0x40000>;
 494                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 496                 clock-names = "clk_usbphy0", "hclk_usb0";
 497                 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
 498                                 <&reset RK3036_RST_OTGC0>;
 499                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 500                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 501                 rockchip,usb-mode = <0>;
 502         };
 503
 504         usb1: usb@101c0000 {
 505                 compatible = "rockchip,rk3036_usb20_host";
 506                 reg = <0x101c0000 0x40000>;
 507                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 509                 clock-names = "clk_usbphy1", "hclk_usb1";
 510                 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
 511                                 <&reset RK3036_RST_OTGC1>;
 512                 reset-names = "host_ahb", "host_phy", "host_controller";
 513         };
 514
 515         fb: fb{
 516                 compatible = "rockchip,rk-fb";
 517                 rockchip,disp-mode = <NO_DUAL>;
 518         };
 519
 520         rk_screen: rk_screen{
 521                 compatible = "rockchip,screen";
 522         };
 523
 524         lcdc: lcdc@10118000 {
 525                 compatible = "rockchip,rk3036-lcdc";
 526                 reg = <0x10118000 0x200>;
 527                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 528                 status = "disabled";
 529                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 530                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 531                 rockchip,iommu-enabled = <0>;
 532         };
 533
 534         hdmi: hdmi@20034000 {
 535                 compatible = "rockchip,rk3036-hdmi";
 536                 reg = <0x20034000 0x4000>;
 537                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 538                 rockchip,hdmi_lcdc_source = <0>;
 539                 pinctrl-names = "default", "gpio";
 540                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 541                 pinctrl-1 = <&hdmi_gpio>;
 542                 clocks = <&clk_gates3 8>;
 543                 clock-names = "pclk_hdmi";
 544                 status = "disabled";
 545         };
 546
 547         tve: tve{
 548                 compatible = "rockchip,rk3036-tve";
 549                 reg = <0x10118200 0x100>;
 550                 status = "disabled";
 551         };
 552
 553         ion {
 554                 compatible = "rockchip,ion";
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557
 558                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 559                         compatible = "rockchip,ion-reserve";
 560                         rockchip,ion_heap = <1>;
 561                         reg = <0x00000000 0x10000000>; /* 256MB */
 562                 };
 563                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 564                         rockchip,ion_heap = <3>;
 565                 };
 566         };
 567
 568         vpu: vpu_service@10108000 {
 569                 compatible = "vpu_service";
 570                 reg = <0x10108000 0x800>;
 571                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 572                 interrupt-names = "irq_dec";
 573                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
 574                 clock-names = "aclk_vcodec", "hclk_vcodec";
 575                 name = "vpu_service";
 576                 status = "okay";
 577         };
 578
 579         hevc: hevc_service@1010c000 {
 580                 compatible = "rockchip,hevc_service";
 581                 reg = <0x1010c000 0x400>;
 582                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 583                 interrupt-names = "irq_dec";
 584                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 585                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 586                 name = "hevc_service";
 587                 status = "okay";
 588         };
 589
 590         vop_mmu {
 591                 dbgname = "vop";
 592                 compatible = "iommu,vop_mmu";
 593                 reg = <0x10118300 0x100>;
 594                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 595                 interrupt-names = "vop_mmu";
 596         };
 597
 598         hevc_mmu {
 599                 dbgname = "hevc";
 600                 compatible = "iommu,hevc_mmu";
 601                 reg = <0x1010c440 0x100>,
 602                       <0x1010c480 0x100>;
 603                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 604                 interrupt-names = "hevc_mmu";
 605         };
 606
 607         vpu_mmu {
 608                 dbgname = "vpu";
 609                 compatible = "iommu,vpu_mmu";
 610                 reg = <0x10108800 0x100>;
 611                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 612                 interrupt-names = "vpu_mmu";
 613         };
 614 };