1 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include "skeleton.dtsi"
4 #include "rk3036-clocks.dtsi"
7 compatible = "rockchip,rk3036";
8 rockchip,sram = <&sram>;
9 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a7";
31 compatible = "arm,cortex-a7";
36 gic: interrupt-controller@10139000 {
37 compatible = "arm,cortex-a15-gic";
39 #interrupt-cells = <3>;
41 reg = <0x10139000 0x1000>,
46 compatible = "arm,cortex-a7-pmu";
47 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
52 compatible = "mmio-sram";
53 reg = <0x10080000 0x2000>;
58 compatible = "arm,armv7-timer";
59 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
60 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
61 clock-frequency = <24000000>;
64 watchdog: wdt@2004c000 {
65 compatible = "rockchip,watch dog";
66 reg = <0x2004c000 0x100>;
67 clocks = <&clk_gates7 15>;
68 clock-names = "pclk_wdt";
69 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
71 rockchip,timeout = <60>;
72 rockchip,atboot = <1>;
80 compatible = "arm,amba-bus";
81 interrupt-parent = <&gic>;
85 compatible = "arm,pl330", "arm,primecell";
86 reg = <0x20078000 0x4000>;
87 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
93 nandc: nandc@0xff400000 {
94 compatible = "rockchip,rk-nandc";
95 reg = <0xff400000 0x4000>;
96 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&clk_nandc>, <&clk_gates5 9>;
98 clock-names = "clk_nandc", "hclk_nandc";
102 compatible = "rockchip,rockchip-spi";
103 reg = <0x20074000 0x1000>;
104 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
105 #address-cells = <1>;
107 //pinctrl-names = "default";
108 //pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
109 rockchip,spi-src-clk = <0>;
111 clocks =<&clk_spi0>, <&clk_gates7 12>;
112 clock-names = "spi","pclk_spi0";
113 //dmas = <&pdma1 11>, <&pdma1 12>;
115 //dma-names = "tx", "rx";
119 uart0: serial@20060000 {
120 compatible = "rockchip,serial";
121 reg = <0x20060000 0x100>;
122 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
123 clock-frequency = <24000000>;
124 clocks = <&clk_uart0>, <&clk_gates8 0>;
125 clock-names = "sclk_uart", "pclk_uart";
128 dmas = <&pdma 2>, <&pdma 3>;
130 //pinctrl-names = "default";
131 //pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
135 uart1: serial@20064000 {
136 compatible = "rockchip,serial";
137 reg = <0x20064000 0x100>;
138 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
139 clock-frequency = <24000000>;
140 clocks = <&clk_uart1>, <&clk_gates8 1>;
141 clock-names = "sclk_uart", "pclk_uart";
144 dmas = <&pdma 4>, <&pdma 5>;
146 //pinctrl-names = "default";
147 //pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
151 uart2: serial@20068000 {
152 compatible = "rockchip,serial";
153 reg = <0x20068000 0x100>;
154 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
155 clock-frequency = <24000000>;
156 clocks = <&clk_uart2>, <&clk_gates8 2>;
157 clock-names = "sclk_uart", "pclk_uart";
160 dmas = <&pdma 6>, <&pdma 7>;
162 //pinctrl-names = "default";
163 //pinctrl-0 = <&uart2_xfer>;
168 compatible = "rockchip,fiq-debugger";
169 rockchip,serial-id = <2>;
170 rockchip,signal-irq = <106>;
171 rockchip,wake-irq = <0>;
176 compatible = "rockchip,rk30-i2c";
177 reg = <0x20072000 0x1000>;
178 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
181 //pinctrl-names = "default", "gpio";
182 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
183 //pinctrl-1 = <&i2c0_gpio>;
184 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
185 clocks = <&clk_gates8 4>;
186 rockchip,check-idle = <1>;
191 compatible = "rockchip,rk30-i2c";
192 reg = <0x20056000 0x1000>;
193 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
196 //pinctrl-names = "default", "gpio";
197 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
198 //pinctrl-1 = <&i2c1_gpio>;
199 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
200 clocks = <&clk_gates8 5>;
201 rockchip,check-idle = <1>;
206 compatible = "rockchip,rk30-i2c";
207 reg = <0x2005a000 0x1000>;
208 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
211 //pinctrl-names = "default", "gpio";
212 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
213 //pinctrl-1 = <&i2c2_gpio>;
214 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
215 clocks = <&clk_gates8 6>;
216 rockchip,check-idle = <1>;
221 compatible = "rockchip-i2s";
222 reg = <0x10220000 0x1000>;
224 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
225 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
226 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
227 dmas = <&pdma 0>, <&pdma 1>;
229 dma-names = "tx", "rx";
230 //pinctrl-names = "default", "sleep";
231 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
232 //pinctrl-1 = <&i2s_gpio>;
235 spdif: spdif@10204000 {
236 compatible = "rockchip-spdif";
237 reg = <0x10204000 0x1000>;
238 clocks = <&clk_spdif>;
239 clock-names = "spdif_mclk";
240 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
244 //pinctrl-names = "default";
245 //pinctrl-0 = <&spdif_tx>;
249 compatible = "rockchip,rk-pwm";
250 reg = <0x20050000 0x10>;
252 //pinctrl-names = "default";
253 //pinctrl-0 = <&pwm_pin>;
254 clocks = <&clk_gates7 10>;
255 clock-names = "pclk_pwm";
259 emmc: rksdmmc@1021c000 {
260 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
261 reg = <0x1021c000 0x4000>;
262 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
263 #address-cells = <1>;
265 //pinctrl-names = "default",,"suspend";
266 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
267 clocks = <&clk_emmc>, <&clk_gates7 0>;
268 clock-names = "clk_mmc", "hclk_mmc";
270 fifo-depth = <0x100>;
275 sdmmc: rksdmmc@10214000 {
276 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
277 reg = <0x10214000 0x4000>;
278 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
281 //pinctrl-names = "default", "idle";
282 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
283 //pinctrl-1 = <&sdmmc0_gpio>;
284 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
285 clocks = <&clk_sdmmc>, <&clk_gates2 11>;
286 clock-names = "clk_mmc", "hclk_mmc";
288 fifo-depth = <0x100>;
292 sdio: rksdmmc@10218000 {
293 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
294 reg = <0x10218000 0x4000>;
295 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
298 //pinctrl-names = "default","idle";
299 //pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
300 //pinctrl-1 = <&sdio_gpio>;
301 clocks = <&clk_sdio>, <&clk_gates5 11>;
302 clock-names = "clk_mmc", "hclk_mmc";
304 fifo-depth = <0x100>;