arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include <dt-bindings/soc/rockchip_boot-mode.h>
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3036";
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 i2c0 = &i2c0;
  56                 i2c1 = &i2c1;
  57                 i2c2 = &i2c2;
  58                 mshc0 = &emmc;
  59                 mshc1 = &sdmmc;
  60                 mshc2 = &sdio;
  61                 serial0 = &uart0;
  62                 serial1 = &uart1;
  63                 serial2 = &uart2;
  64                 spi = &spi;
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70                 enable-method = "rockchip,rk3036-smp";
  71
  72                 cpu0: cpu@f00 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf00>;
  76                         resets = <&cru SRST_CORE0>;
  77                         operating-points = <
  78                                 /* KHz    uV */
  79                                  816000 1000000
  80                         >;
  81                         clock-latency = <40000>;
  82                         clocks = <&cru ARMCLK>;
  83                 };
  84
  85                 cpu1: cpu@f01 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0xf01>;
  89                         resets = <&cru SRST_CORE1>;
  90                 };
  91         };
  92
  93         amba {
  94                 compatible = "arm,amba-bus";
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 pdma: pdma@20078000 {
 100                         compatible = "arm,pl330", "arm,primecell";
 101                         reg = <0x20078000 0x4000>;
 102                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 104                         #dma-cells = <1>;
 105                         arm,pl330-broken-no-flushp;
 106                         peripherals-req-type-burst;
 107                         clocks = <&cru ACLK_DMAC2>;
 108                         clock-names = "apb_pclk";
 109                 };
 110         };
 111
 112         arm-pmu {
 113                 compatible = "arm,cortex-a7-pmu";
 114                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 115                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 116                 interrupt-affinity = <&cpu0>, <&cpu1>;
 117         };
 118
 119         display-subsystem {
 120                 compatible = "rockchip,display-subsystem";
 121                 ports = <&vop_out>;
 122         };
 123
 124         timer {
 125                 compatible = "arm,armv7-timer";
 126                 arm,cpu-registers-not-fw-configured;
 127                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 131                 clock-frequency = <24000000>;
 132         };
 133
 134         xin24m: oscillator {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <24000000>;
 137                 clock-output-names = "xin24m";
 138                 #clock-cells = <0>;
 139         };
 140
 141         bus_intmem@10080000 {
 142                 compatible = "mmio-sram";
 143                 reg = <0x10080000 0x2000>;
 144                 #address-cells = <1>;
 145                 #size-cells = <1>;
 146                 ranges = <0 0x10080000 0x2000>;
 147
 148                 smp-sram@0 {
 149                         compatible = "rockchip,rk3066-smp-sram";
 150                         reg = <0x00 0x10>;
 151                 };
 152         };
 153
 154         gpu: gpu@10090000 {
 155                 compatible = "arm,mali400";
 156
 157                 reg = <0x10091000 0x200>,
 158                       <0x10090000 0x100>,
 159                       <0x10093000 0x100>,
 160                       <0x10098000 0x1100>,
 161                       <0x10094000 0x100>;
 162
 163                 reg-names = "Mali_L2",
 164                             "Mali_GP",
 165                             "Mali_GP_MMU",
 166                             "Mali_PP0",
 167                             "Mali_PP0_MMU";
 168
 169                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 173                 interrupt-names = "Mali_GP_IRQ",
 174                                   "Mali_GP_MMU_IRQ",
 175                                   "Mali_PP0_IRQ",
 176                                   "Mali_PP0_MMU_IRQ";
 177
 178                 clocks = <&cru  SCLK_GPU>;
 179                 clock-names = "clk_mali";
 180
 181                 status = "disabled";
 182         };
 183
 184         vpu: video-codec@10108000 {
 185                 compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
 186                 reg = <0x10108000 0x800>;
 187                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 189                 interrupt-names = "vepu", "vdpu";
 190                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 191                 clock-names = "aclk", "hclk";
 192                 iommus = <&vpu_mmu>;
 193                 /*
 194                  * 3036's vpu could not run higher than 300M
 195                  */
 196                 assigned-clocks = <&cru ACLK_VCODEC>;
 197                 assigned-clock-rates = <297000000>;
 198                 assigned-clock-parents = <&cru PLL_GPLL>;
 199                 status = "disabled";
 200         };
 201
 202         vpu_mmu: iommu@10108800 {
 203                 compatible = "rockchip,iommu";
 204                 reg = <0x10108800 0x100>;
 205                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 206                 interrupt-names = "vpu_mmu";
 207                 #iommu-cells = <0>;
 208         };
 209
 210         vop: vop@10118000 {
 211                 compatible = "rockchip,rk3036-vop";
 212                 reg = <0x10118000 0x19c>;
 213                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 215                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 216                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 217                 reset-names = "axi", "ahb", "dclk";
 218                 iommus = <&vop_mmu>;
 219                 status = "disabled";
 220
 221                 vop_out: port {
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         vop_out_hdmi: endpoint@0 {
 225                                 reg = <0>;
 226                                 remote-endpoint = <&hdmi_in_vop>;
 227                         };
 228                 };
 229         };
 230
 231         vop_mmu: iommu@10118300 {
 232                 compatible = "rockchip,iommu";
 233                 reg = <0x10118300 0x100>;
 234                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 235                 interrupt-names = "vop_mmu";
 236                 #iommu-cells = <0>;
 237                 status = "disabled";
 238         };
 239
 240         gic: interrupt-controller@10139000 {
 241                 compatible = "arm,gic-400";
 242                 interrupt-controller;
 243                 #interrupt-cells = <3>;
 244                 #address-cells = <0>;
 245
 246                 reg = <0x10139000 0x1000>,
 247                       <0x1013a000 0x1000>,
 248                       <0x1013c000 0x2000>,
 249                       <0x1013e000 0x2000>;
 250                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 251         };
 252
 253         usb_otg: usb@10180000 {
 254                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 255                                 "snps,dwc2";
 256                 reg = <0x10180000 0x40000>;
 257                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&cru HCLK_OTG0>;
 259                 clock-names = "otg";
 260                 dr_mode = "otg";
 261                 g-np-tx-fifo-size = <16>;
 262                 g-rx-fifo-size = <275>;
 263                 g-tx-fifo-size = <256 128 128 64 64 32>;
 264                 g-use-dma;
 265                 status = "disabled";
 266         };
 267
 268         usb_host: usb@101c0000 {
 269                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 270                                 "snps,dwc2";
 271                 reg = <0x101c0000 0x40000>;
 272                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&cru HCLK_OTG1>;
 274                 clock-names = "otg";
 275                 dr_mode = "host";
 276                 status = "disabled";
 277         };
 278
 279         emac: ethernet@10200000 {
 280                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 281                 reg = <0x10200000 0x4000>;
 282                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 rockchip,grf = <&grf>;
 286                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 287                 clock-names = "hclk", "macref", "macclk";
 288                 /*
 289                  * Fix the emac parent clock is DPLL instead of APLL.
 290                  * since that will cause some unstable things if the cpufreq
 291                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 292                  */
 293                 assigned-clocks = <&cru SCLK_MACPLL>;
 294                 assigned-clock-parents = <&cru PLL_DPLL>;
 295                 max-speed = <100>;
 296                 phy-mode = "rmii";
 297                 status = "disabled";
 298         };
 299
 300         sdmmc: dwmmc@10214000 {
 301                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 302                 reg = <0x10214000 0x4000>;
 303                 clock-frequency = <37500000>;
 304                 clock-freq-min-max = <400000 37500000>;
 305                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 306                 clock-names = "biu", "ciu";
 307                 fifo-depth = <0x100>;
 308                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 309                 status = "disabled";
 310         };
 311
 312         sdio: dwmmc@10218000 {
 313                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 314                 reg = <0x10218000 0x4000>;
 315                 clock-freq-min-max = <400000 37500000>;
 316                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 317                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 318                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 319                 fifo-depth = <0x100>;
 320                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 321                 status = "disabled";
 322         };
 323
 324         emmc: dwmmc@1021c000 {
 325                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 326                 reg = <0x1021c000 0x4000>;
 327                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 328                 bus-width = <8>;
 329                 cap-mmc-highspeed;
 330                 clock-frequency = <37500000>;
 331                 clock-freq-min-max = <400000 37500000>;
 332                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 333                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 334                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 335                 default-sample-phase = <158>;
 336                 disable-wp;
 337                 dmas = <&pdma 12>;
 338                 dma-names = "rx-tx";
 339                 fifo-depth = <0x100>;
 340                 mmc-ddr-1_8v;
 341                 non-removable;
 342                 num-slots = <1>;
 343                 supports-emmc;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 346                 status = "disabled";
 347         };
 348
 349         i2s: i2s@10220000 {
 350                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 351                 reg = <0x10220000 0x4000>;
 352                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clock-names = "i2s_clk", "i2s_hclk";
 356                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 357                 dmas = <&pdma 0>, <&pdma 1>;
 358                 dma-names = "tx", "rx";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2s_bus>;
 361                 status = "disabled";
 362         };
 363
 364         cru: clock-controller@20000000 {
 365                 compatible = "rockchip,rk3036-cru";
 366                 reg = <0x20000000 0x1000>;
 367                 rockchip,grf = <&grf>;
 368                 #clock-cells = <1>;
 369                 #reset-cells = <1>;
 370                 assigned-clocks = <&cru PLL_GPLL>;
 371                 assigned-clock-rates = <594000000>;
 372         };
 373
 374         grf: syscon@20008000 {
 375                 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 376                 reg = <0x20008000 0x1000>;
 377                 reboot-mode {
 378                         compatible = "syscon-reboot-mode";
 379                         offset = <0x1d8>;
 380                         mode-normal = <BOOT_NORMAL>;
 381                         mode-recovery = <BOOT_RECOVERY>;
 382                         mode-bootloader = <BOOT_FASTBOOT>;
 383                         mode-loader = <BOOT_LOADER>;
 384                 };
 385         };
 386
 387         acodec: acodec-ana@20030000 {
 388                 compatible = "rk3036-codec";
 389                 reg = <0x20030000 0x4000>;
 390                 rockchip,grf = <&grf>;
 391                 clock-names = "acodec_pclk";
 392                 clocks = <&cru PCLK_ACODEC>;
 393                 status = "disabled";
 394         };
 395
 396         hdmi: hdmi@20034000 {
 397                 compatible = "rockchip,rk3036-inno-hdmi";
 398                 reg = <0x20034000 0x4000>;
 399                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&cru  PCLK_HDMI>;
 401                 clock-names = "pclk";
 402                 rockchip,grf = <&grf>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&hdmi_ctl>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 #sound-dai-cells = <0>;
 408                 status = "disabled";
 409
 410                 hdmi_in: port {
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         hdmi_in_vop: endpoint@0 {
 414                                 reg = <0>;
 415                                 remote-endpoint = <&vop_out_hdmi>;
 416                         };
 417                 };
 418         };
 419
 420         hdmi_sound: hdmi-sound {
 421                 compatible = "simple-audio-card";
 422                 simple-audio-card,name = "rockchip,hdmi";
 423                 simple-audio-card,widgets = "Headphone", "Out Jack",
 424                                             "Line", "In Jack";
 425                 status = "disabled";
 426
 427                 simple-audio-card,dai-link {
 428                         format = "i2s";
 429                         mclk-fs = <256>;
 430                         cpu {
 431                                 sound-dai = <&i2s>;
 432                         };
 433                         codec {
 434                                 sound-dai = <&hdmi>;
 435                         };
 436                 };
 437         };
 438
 439         timer: timer@20044000 {
 440                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 441                 reg = <0x20044000 0x20>;
 442                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 444                 clock-names = "timer", "pclk";
 445         };
 446
 447         pwm0: pwm@20050000 {
 448                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 449                 reg = <0x20050000 0x10>;
 450                 #pwm-cells = <3>;
 451                 clocks = <&cru PCLK_PWM>;
 452                 clock-names = "pwm";
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&pwm0_pin>;
 455                 status = "disabled";
 456         };
 457
 458         pwm1: pwm@20050010 {
 459                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 460                 reg = <0x20050010 0x10>;
 461                 #pwm-cells = <3>;
 462                 clocks = <&cru PCLK_PWM>;
 463                 clock-names = "pwm";
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&pwm1_pin>;
 466                 status = "disabled";
 467         };
 468
 469         pwm2: pwm@20050020 {
 470                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 471                 reg = <0x20050020 0x10>;
 472                 #pwm-cells = <3>;
 473                 clocks = <&cru PCLK_PWM>;
 474                 clock-names = "pwm";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&pwm2_pin>;
 477                 status = "disabled";
 478         };
 479
 480         pwm3: pwm@20050030 {
 481                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 482                 reg = <0x20050030 0x10>;
 483                 #pwm-cells = <2>;
 484                 clocks = <&cru PCLK_PWM>;
 485                 clock-names = "pwm";
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&pwm3_pin>;
 488                 status = "disabled";
 489         };
 490
 491         i2c1: i2c@20056000 {
 492                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 493                 reg = <0x20056000 0x1000>;
 494                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clock-names = "i2c";
 498                 clocks = <&cru PCLK_I2C1>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c1_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         i2c2: i2c@2005a000 {
 505                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 506                 reg = <0x2005a000 0x1000>;
 507                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 clock-names = "i2c";
 511                 clocks = <&cru PCLK_I2C2>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c2_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         uart0: serial@20060000 {
 518                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 519                 reg = <0x20060000 0x100>;
 520                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 521                 reg-shift = <2>;
 522                 reg-io-width = <4>;
 523                 clock-frequency = <24000000>;
 524                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 525                 clock-names = "baudclk", "apb_pclk";
 526                 pinctrl-names = "default";
 527                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 528                 status = "disabled";
 529         };
 530
 531         uart1: serial@20064000 {
 532                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 533                 reg = <0x20064000 0x100>;
 534                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 535                 reg-shift = <2>;
 536                 reg-io-width = <4>;
 537                 clock-frequency = <24000000>;
 538                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 539                 clock-names = "baudclk", "apb_pclk";
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&uart1_xfer>;
 542                 status = "disabled";
 543         };
 544
 545         uart2: serial@20068000 {
 546                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 547                 reg = <0x20068000 0x100>;
 548                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 549                 reg-shift = <2>;
 550                 reg-io-width = <4>;
 551                 clock-frequency = <24000000>;
 552                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 553                 clock-names = "baudclk", "apb_pclk";
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&uart2_xfer>;
 556                 status = "disabled";
 557         };
 558
 559         i2c0: i2c@20072000 {
 560                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 561                 reg = <0x20072000 0x1000>;
 562                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 clock-names = "i2c";
 566                 clocks = <&cru PCLK_I2C0>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c0_xfer>;
 569                 status = "disabled";
 570         };
 571
 572         spi: spi@20074000 {
 573                 compatible = "rockchip,rockchip-spi";
 574                 reg = <0x20074000 0x1000>;
 575                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 577                 clock-names = "apb-pclk","spi_pclk";
 578                 dmas = <&pdma 8>, <&pdma 9>;
 579                 dma-names = "tx", "rx";
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 status = "disabled";
 585         };
 586
 587         pinctrl: pinctrl {
 588                 compatible = "rockchip,rk3036-pinctrl";
 589                 rockchip,grf = <&grf>;
 590                 #address-cells = <1>;
 591                 #size-cells = <1>;
 592                 ranges;
 593
 594                 gpio0: gpio0@2007c000 {
 595                         compatible = "rockchip,gpio-bank";
 596                         reg = <0x2007c000 0x100>;
 597                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&cru PCLK_GPIO0>;
 599
 600                         gpio-controller;
 601                         #gpio-cells = <2>;
 602
 603                         interrupt-controller;
 604                         #interrupt-cells = <2>;
 605                 };
 606
 607                 gpio1: gpio1@20080000 {
 608                         compatible = "rockchip,gpio-bank";
 609                         reg = <0x20080000 0x100>;
 610                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&cru PCLK_GPIO1>;
 612
 613                         gpio-controller;
 614                         #gpio-cells = <2>;
 615
 616                         interrupt-controller;
 617                         #interrupt-cells = <2>;
 618                 };
 619
 620                 gpio2: gpio2@20084000 {
 621                         compatible = "rockchip,gpio-bank";
 622                         reg = <0x20084000 0x100>;
 623                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&cru PCLK_GPIO2>;
 625
 626                         gpio-controller;
 627                         #gpio-cells = <2>;
 628
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                 };
 632
 633                 pcfg_pull_default: pcfg_pull_default {
 634                         bias-pull-pin-default;
 635                 };
 636
 637                 pcfg_pull_none: pcfg-pull-none {
 638                         bias-disable;
 639                 };
 640
 641                 pwm0 {
 642                         pwm0_pin: pwm0-pin {
 643                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 644                         };
 645                 };
 646
 647                 pwm1 {
 648                         pwm1_pin: pwm1-pin {
 649                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 650                         };
 651                 };
 652
 653                 pwm2 {
 654                         pwm2_pin: pwm2-pin {
 655                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 656                         };
 657                 };
 658
 659                 pwm3 {
 660                         pwm3_pin: pwm3-pin {
 661                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 662                         };
 663                 };
 664
 665                 sdmmc {
 666                         sdmmc_clk: sdmmc-clk {
 667                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 668                         };
 669
 670                         sdmmc_cmd: sdmmc-cmd {
 671                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 672                         };
 673
 674                         sdmmc_cd: sdmcc-cd {
 675                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 676                         };
 677
 678                         sdmmc_bus1: sdmmc-bus1 {
 679                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 680                         };
 681
 682                         sdmmc_bus4: sdmmc-bus4 {
 683                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 684                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 685                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 686                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 687                         };
 688                 };
 689
 690                 sdio {
 691                         sdio_bus1: sdio-bus1 {
 692                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 693                         };
 694
 695                         sdio_bus4: sdio-bus4 {
 696                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 697                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 698                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 699                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 700                         };
 701
 702                         sdio_cmd: sdio-cmd {
 703                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 704                         };
 705
 706                         sdio_clk: sdio-clk {
 707                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 708                         };
 709                 };
 710
 711                 emmc {
 712                         /*
 713                          * We run eMMC at max speed; bump up drive strength.
 714                          * We also have external pulls, so disable the internal ones.
 715                          */
 716                         emmc_clk: emmc-clk {
 717                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 718                         };
 719
 720                         emmc_cmd: emmc-cmd {
 721                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 722                         };
 723
 724                         emmc_bus8: emmc-bus8 {
 725                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 726                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 727                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 728                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 729                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 730                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 731                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 732                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 733                         };
 734                 };
 735
 736                 emac {
 737                         emac_xfer: emac-xfer {
 738                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 739                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 740                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 741                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 742                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 743                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 744                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 745                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 746                         };
 747
 748                         emac_mdio: emac-mdio {
 749                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 750                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 751                         };
 752                 };
 753
 754                 i2c0 {
 755                         i2c0_xfer: i2c0-xfer {
 756                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 757                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 758                         };
 759                 };
 760
 761                 i2c1 {
 762                         i2c1_xfer: i2c1-xfer {
 763                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 764                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 765                         };
 766                 };
 767
 768                 i2c2 {
 769                         i2c2_xfer: i2c2-xfer {
 770                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 771                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 772                         };
 773                 };
 774
 775                 i2s {
 776                         i2s_bus: i2s-bus {
 777                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 778                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 779                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 780                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 781                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 782                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 783                         };
 784                 };
 785
 786                 hdmi {
 787                         hdmi_ctl: hdmi-ctl {
 788                                 rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
 789                                                 <1 9  RK_FUNC_1 &pcfg_pull_none>,
 790                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,
 791                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;
 792                         };
 793                 };
 794
 795                 uart0 {
 796                         uart0_xfer: uart0-xfer {
 797                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 798                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 799                         };
 800
 801                         uart0_cts: uart0-cts {
 802                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 803                         };
 804
 805                         uart0_rts: uart0-rts {
 806                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 807                         };
 808                 };
 809
 810                 uart1 {
 811                         uart1_xfer: uart1-xfer {
 812                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 813                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 814                         };
 815                         /* no rts / cts for uart1 */
 816                 };
 817
 818                 uart2 {
 819                         uart2_xfer: uart2-xfer {
 820                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 821                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 822                         };
 823                         /* no rts / cts for uart2 */
 824                 };
 825
 826                 spi {
 827                         spi_txd:spi-txd {
 828                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 829                         };
 830
 831                         spi_rxd:spi-rxd {
 832                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 833                         };
 834
 835                         spi_clk:spi-clk {
 836                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 837                         };
 838
 839                         spi_cs0:spi-cs0 {
 840                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 841
 842                         };
 843
 844                         spi_cs1:spi-cs1 {
 845                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 846
 847                         };
 848                 };
 849         };
 850 };