arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 serial0 = &uart0;
  59                 serial1 = &uart1;
  60                 serial2 = &uart2;
  61         };
  62
  63         memory {
  64                 device_type = "memory";
  65                 reg = <0x60000000 0x40000000>;
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71                 enable-method = "rockchip,rk3036-smp";
  72
  73                 cpu0: cpu@f00 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a7";
  76                         reg = <0xf00>;
  77                         resets = <&cru SRST_CORE0>;
  78                         operating-points = <
  79                                 /* KHz    uV */
  80                                  816000 1000000
  81                         >;
  82                         clock-latency = <40000>;
  83                         clocks = <&cru ARMCLK>;
  84                 };
  85
  86                 cpu1: cpu@f01 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a7";
  89                         reg = <0xf01>;
  90                         resets = <&cru SRST_CORE1>;
  91                 };
  92         };
  93
  94         amba {
  95                 compatible = "arm,amba-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99
 100                 pdma: pdma@20078000 {
 101                         compatible = "arm,pl330", "arm,primecell";
 102                         reg = <0x20078000 0x4000>;
 103                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 105                         #dma-cells = <1>;
 106                         clocks = <&cru ACLK_DMAC2>;
 107                         clock-names = "apb_pclk";
 108                 };
 109         };
 110
 111         arm-pmu {
 112                 compatible = "arm,cortex-a7-pmu";
 113                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 114                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 115                 interrupt-affinity = <&cpu0>, <&cpu1>;
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv7-timer";
 120                 arm,cpu-registers-not-fw-configured;
 121                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 122                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 123                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 124                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 125                 clock-frequency = <24000000>;
 126         };
 127
 128         xin24m: oscillator {
 129                 compatible = "fixed-clock";
 130                 clock-frequency = <24000000>;
 131                 clock-output-names = "xin24m";
 132                 #clock-cells = <0>;
 133         };
 134
 135         bus_intmem@10080000 {
 136                 compatible = "mmio-sram";
 137                 reg = <0x10080000 0x2000>;
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges = <0 0x10080000 0x2000>;
 141
 142                 smp-sram@0 {
 143                         compatible = "rockchip,rk3066-smp-sram";
 144                         reg = <0x00 0x10>;
 145                 };
 146         };
 147
 148         gic: interrupt-controller@10139000 {
 149                 compatible = "arm,gic-400";
 150                 interrupt-controller;
 151                 #interrupt-cells = <3>;
 152                 #address-cells = <0>;
 153
 154                 reg = <0x10139000 0x1000>,
 155                       <0x1013a000 0x1000>,
 156                       <0x1013c000 0x2000>,
 157                       <0x1013e000 0x2000>;
 158                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 159         };
 160
 161         usb_otg: usb@10180000 {
 162                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 163                                 "snps,dwc2";
 164                 reg = <0x10180000 0x40000>;
 165                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&cru HCLK_OTG0>;
 167                 clock-names = "otg";
 168                 dr_mode = "otg";
 169                 g-np-tx-fifo-size = <16>;
 170                 g-rx-fifo-size = <275>;
 171                 g-tx-fifo-size = <256 128 128 64 64 32>;
 172                 g-use-dma;
 173                 status = "disabled";
 174         };
 175
 176         usb_host: usb@101c0000 {
 177                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 178                                 "snps,dwc2";
 179                 reg = <0x101c0000 0x40000>;
 180                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&cru HCLK_OTG1>;
 182                 clock-names = "otg";
 183                 dr_mode = "host";
 184                 status = "disabled";
 185         };
 186
 187         emmc: dwmmc@1021c000 {
 188                 compatible = "rockchip,rk3288-dw-mshc";
 189                 reg = <0x1021c000 0x4000>;
 190                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 191                 broken-cd;
 192                 bus-width = <8>;
 193                 cap-mmc-highspeed;
 194                 clock-frequency = <37500000>;
 195                 clock-freq-min-max = <400000 37500000>;
 196                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 197                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 198                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 199                 default-sample-phase = <158>;
 200                 disable-wp;
 201                 dmas = <&pdma 12>;
 202                 dma-names = "rx-tx";
 203                 fifo-depth = <0x100>;
 204                 mmc-ddr-1_8v;
 205                 non-removable;
 206                 num-slots = <1>;
 207                 pinctrl-names = "default";
 208                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 209                 status = "disabled";
 210         };
 211
 212         i2s: i2s@10220000 {
 213                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 214                 reg = <0x10220000 0x4000>;
 215                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 clock-names = "i2s_hclk", "i2s_clk";
 219                 clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
 220                 dmas = <&pdma 0>, <&pdma 1>;
 221                 dma-names = "tx", "rx";
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&i2s_bus>;
 224                 status = "disabled";
 225         };
 226
 227         cru: clock-controller@20000000 {
 228                 compatible = "rockchip,rk3036-cru";
 229                 reg = <0x20000000 0x1000>;
 230                 rockchip,grf = <&grf>;
 231                 #clock-cells = <1>;
 232                 #reset-cells = <1>;
 233                 assigned-clocks = <&cru PLL_GPLL>;
 234                 assigned-clock-rates = <594000000>;
 235         };
 236
 237         grf: syscon@20008000 {
 238                 compatible = "rockchip,rk3036-grf", "syscon";
 239                 reg = <0x20008000 0x1000>;
 240         };
 241
 242         acodec: acodec-ana@20030000 {
 243                 compatible = "rk3036-codec";
 244                 reg = <0x20030000 0x4000>;
 245                 rockchip,grf = <&grf>;
 246                 clock-names = "acodec_pclk";
 247                 clocks = <&cru PCLK_ACODEC>;
 248                 status = "disabled";
 249         };
 250
 251         timer: timer@20044000 {
 252                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 253                 reg = <0x20044000 0x20>;
 254                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 256                 clock-names = "timer", "pclk";
 257         };
 258
 259         pwm0: pwm@20050000 {
 260                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 261                 reg = <0x20050000 0x10>;
 262                 #pwm-cells = <3>;
 263                 clocks = <&cru PCLK_PWM>;
 264                 clock-names = "pwm";
 265                 pinctrl-names = "default";
 266                 pinctrl-0 = <&pwm0_pin>;
 267                 status = "disabled";
 268         };
 269
 270         pwm1: pwm@20050010 {
 271                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 272                 reg = <0x20050010 0x10>;
 273                 #pwm-cells = <3>;
 274                 clocks = <&cru PCLK_PWM>;
 275                 clock-names = "pwm";
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&pwm1_pin>;
 278                 status = "disabled";
 279         };
 280
 281         pwm2: pwm@20050020 {
 282                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 283                 reg = <0x20050020 0x10>;
 284                 #pwm-cells = <3>;
 285                 clocks = <&cru PCLK_PWM>;
 286                 clock-names = "pwm";
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&pwm2_pin>;
 289                 status = "disabled";
 290         };
 291
 292         pwm3: pwm@20050030 {
 293                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 294                 reg = <0x20050030 0x10>;
 295                 #pwm-cells = <2>;
 296                 clocks = <&cru PCLK_PWM>;
 297                 clock-names = "pwm";
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&pwm3_pin>;
 300                 status = "disabled";
 301         };
 302
 303         i2c1: i2c@20056000 {
 304                 compatible = "rockchip,rk3288-i2c";
 305                 reg = <0x20056000 0x1000>;
 306                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 clock-names = "i2c";
 310                 clocks = <&cru PCLK_I2C1>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&i2c1_xfer>;
 313                 status = "disabled";
 314         };
 315
 316         i2c2: i2c@2005a000 {
 317                 compatible = "rockchip,rk3288-i2c";
 318                 reg = <0x2005a000 0x1000>;
 319                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clock-names = "i2c";
 323                 clocks = <&cru PCLK_I2C2>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c2_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         uart0: serial@20060000 {
 330                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 331                 reg = <0x20060000 0x100>;
 332                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 333                 reg-shift = <2>;
 334                 reg-io-width = <4>;
 335                 clock-frequency = <24000000>;
 336                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 337                 clock-names = "baudclk", "apb_pclk";
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 340                 status = "disabled";
 341         };
 342
 343         uart1: serial@20064000 {
 344                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 345                 reg = <0x20064000 0x100>;
 346                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 347                 reg-shift = <2>;
 348                 reg-io-width = <4>;
 349                 clock-frequency = <24000000>;
 350                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 351                 clock-names = "baudclk", "apb_pclk";
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&uart1_xfer>;
 354                 status = "disabled";
 355         };
 356
 357         uart2: serial@20068000 {
 358                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 359                 reg = <0x20068000 0x100>;
 360                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 361                 reg-shift = <2>;
 362                 reg-io-width = <4>;
 363                 clock-frequency = <24000000>;
 364                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 365                 clock-names = "baudclk", "apb_pclk";
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&uart2_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c0: i2c@20072000 {
 372                 compatible = "rockchip,rk3288-i2c";
 373                 reg = <0x20072000 0x1000>;
 374                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C0>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c0_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         pinctrl: pinctrl {
 385                 compatible = "rockchip,rk3036-pinctrl";
 386                 rockchip,grf = <&grf>;
 387                 #address-cells = <1>;
 388                 #size-cells = <1>;
 389                 ranges;
 390
 391                 gpio0: gpio0@2007c000 {
 392                         compatible = "rockchip,gpio-bank";
 393                         reg = <0x2007c000 0x100>;
 394                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 395                         clocks = <&cru PCLK_GPIO0>;
 396
 397                         gpio-controller;
 398                         #gpio-cells = <2>;
 399
 400                         interrupt-controller;
 401                         #interrupt-cells = <2>;
 402                 };
 403
 404                 gpio1: gpio1@20080000 {
 405                         compatible = "rockchip,gpio-bank";
 406                         reg = <0x20080000 0x100>;
 407                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&cru PCLK_GPIO1>;
 409
 410                         gpio-controller;
 411                         #gpio-cells = <2>;
 412
 413                         interrupt-controller;
 414                         #interrupt-cells = <2>;
 415                 };
 416
 417                 gpio2: gpio2@20084000 {
 418                         compatible = "rockchip,gpio-bank";
 419                         reg = <0x20084000 0x100>;
 420                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&cru PCLK_GPIO2>;
 422
 423                         gpio-controller;
 424                         #gpio-cells = <2>;
 425
 426                         interrupt-controller;
 427                         #interrupt-cells = <2>;
 428                 };
 429
 430                 pcfg_pull_default: pcfg_pull_default {
 431                         bias-pull-pin-default;
 432                 };
 433
 434                 pcfg_pull_none: pcfg-pull-none {
 435                         bias-disable;
 436                 };
 437
 438                 pwm0 {
 439                         pwm0_pin: pwm0-pin {
 440                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 441                         };
 442                 };
 443
 444                 pwm1 {
 445                         pwm1_pin: pwm1-pin {
 446                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 447                         };
 448                 };
 449
 450                 pwm2 {
 451                         pwm2_pin: pwm2-pin {
 452                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 453                         };
 454                 };
 455
 456                 pwm3 {
 457                         pwm3_pin: pwm3-pin {
 458                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 459                         };
 460                 };
 461
 462                 emmc {
 463                         /*
 464                          * We run eMMC at max speed; bump up drive strength.
 465                          * We also have external pulls, so disable the internal ones.
 466                          */
 467                         emmc_clk: emmc-clk {
 468                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 469                         };
 470
 471                         emmc_cmd: emmc-cmd {
 472                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 473                         };
 474
 475                         emmc_bus8: emmc-bus8 {
 476                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 477                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 478                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 479                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 480                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 481                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 482                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 483                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 484                         };
 485                 };
 486
 487                 i2c0 {
 488                         i2c0_xfer: i2c0-xfer {
 489                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 490                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 491                         };
 492                 };
 493
 494                 i2c1 {
 495                         i2c1_xfer: i2c1-xfer {
 496                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 497                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 498                         };
 499                 };
 500
 501                 i2c2 {
 502                         i2c2_xfer: i2c2-xfer {
 503                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 504                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 505                         };
 506                 };
 507
 508                 i2s {
 509                         i2s_bus: i2s-bus {
 510                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
 511                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,
 512                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,
 513                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,
 514                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,
 515                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;
 516                         };
 517                 };
 518
 519                 uart0 {
 520                         uart0_xfer: uart0-xfer {
 521                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 522                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 523                         };
 524
 525                         uart0_cts: uart0-cts {
 526                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 527                         };
 528
 529                         uart0_rts: uart0-rts {
 530                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 531                         };
 532                 };
 533
 534                 uart1 {
 535                         uart1_xfer: uart1-xfer {
 536                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 537                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 538                         };
 539                         /* no rts / cts for uart1 */
 540                 };
 541
 542                 uart2 {
 543                         uart2_xfer: uart2-xfer {
 544                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 545                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 546                         };
 547                         /* no rts / cts for uart2 */
 548                 };
 549         };
 550 };