arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         cpus {
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 enable-method = "rockchip,rk3036-smp";
  70
  71                 cpu0: cpu@f00 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a7";
  74                         reg = <0xf00>;
  75                         resets = <&cru SRST_CORE0>;
  76                         operating-points = <
  77                                 /* KHz    uV */
  78                                  816000 1000000
  79                         >;
  80                         clock-latency = <40000>;
  81                         clocks = <&cru ARMCLK>;
  82                 };
  83
  84                 cpu1: cpu@f01 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf01>;
  88                         resets = <&cru SRST_CORE1>;
  89                 };
  90         };
  91
  92         amba {
  93                 compatible = "arm,amba-bus";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97
  98                 pdma: pdma@20078000 {
  99                         compatible = "arm,pl330", "arm,primecell";
 100                         reg = <0x20078000 0x4000>;
 101                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 103                         #dma-cells = <1>;
 104                         arm,pl330-broken-no-flushp;
 105                         clocks = <&cru ACLK_DMAC2>;
 106                         clock-names = "apb_pclk";
 107                 };
 108         };
 109
 110         arm-pmu {
 111                 compatible = "arm,cortex-a7-pmu";
 112                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 114                 interrupt-affinity = <&cpu0>, <&cpu1>;
 115         };
 116
 117         display-subsystem {
 118                 compatible = "rockchip,display-subsystem";
 119                 ports = <&vop_out>;
 120         };
 121
 122         timer {
 123                 compatible = "arm,armv7-timer";
 124                 arm,cpu-registers-not-fw-configured;
 125                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 126                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 129                 clock-frequency = <24000000>;
 130         };
 131
 132         xin24m: oscillator {
 133                 compatible = "fixed-clock";
 134                 clock-frequency = <24000000>;
 135                 clock-output-names = "xin24m";
 136                 #clock-cells = <0>;
 137         };
 138
 139         bus_intmem@10080000 {
 140                 compatible = "mmio-sram";
 141                 reg = <0x10080000 0x2000>;
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 ranges = <0 0x10080000 0x2000>;
 145
 146                 smp-sram@0 {
 147                         compatible = "rockchip,rk3066-smp-sram";
 148                         reg = <0x00 0x10>;
 149                 };
 150         };
 151
 152         vop: vop@10118000 {
 153                 compatible = "rockchip,rk3036-vop";
 154                 reg = <0x10118000 0x19c>;
 155                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 157                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 158                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 159                 reset-names = "axi", "ahb", "dclk";
 160                 iommus = <&vop_mmu>;
 161                 status = "disabled";
 162
 163                 vop_out: port {
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         vop_out_hdmi: endpoint@0 {
 167                                 reg = <0>;
 168                                 remote-endpoint = <&hdmi_in_vop>;
 169                         };
 170                 };
 171         };
 172
 173         vop_mmu: iommu@10118300 {
 174                 compatible = "rockchip,iommu";
 175                 reg = <0x10118300 0x100>;
 176                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 177                 interrupt-names = "vop_mmu";
 178                 #iommu-cells = <0>;
 179                 status = "disabled";
 180         };
 181
 182         gic: interrupt-controller@10139000 {
 183                 compatible = "arm,gic-400";
 184                 interrupt-controller;
 185                 #interrupt-cells = <3>;
 186                 #address-cells = <0>;
 187
 188                 reg = <0x10139000 0x1000>,
 189                       <0x1013a000 0x1000>,
 190                       <0x1013c000 0x2000>,
 191                       <0x1013e000 0x2000>;
 192                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 193         };
 194
 195         usb_otg: usb@10180000 {
 196                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 197                                 "snps,dwc2";
 198                 reg = <0x10180000 0x40000>;
 199                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru HCLK_OTG0>;
 201                 clock-names = "otg";
 202                 dr_mode = "otg";
 203                 g-np-tx-fifo-size = <16>;
 204                 g-rx-fifo-size = <275>;
 205                 g-tx-fifo-size = <256 128 128 64 64 32>;
 206                 g-use-dma;
 207                 status = "disabled";
 208         };
 209
 210         usb_host: usb@101c0000 {
 211                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 212                                 "snps,dwc2";
 213                 reg = <0x101c0000 0x40000>;
 214                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&cru HCLK_OTG1>;
 216                 clock-names = "otg";
 217                 dr_mode = "host";
 218                 status = "disabled";
 219         };
 220
 221         emac: ethernet@10200000 {
 222                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 223                 reg = <0x10200000 0x4000>;
 224                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 rockchip,grf = <&grf>;
 228                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 229                 clock-names = "hclk", "macref", "macclk";
 230                 /*
 231                  * Fix the emac parent clock is DPLL instead of APLL.
 232                  * since that will cause some unstable things if the cpufreq
 233                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 234                  */
 235                 assigned-clocks = <&cru SCLK_MACPLL>;
 236                 assigned-clock-parents = <&cru PLL_DPLL>;
 237                 max-speed = <100>;
 238                 phy-mode = "rmii";
 239                 status = "disabled";
 240         };
 241
 242         sdmmc: dwmmc@10214000 {
 243                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 244                 reg = <0x10214000 0x4000>;
 245                 clock-frequency = <37500000>;
 246                 clock-freq-min-max = <400000 37500000>;
 247                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 248                 clock-names = "biu", "ciu";
 249                 fifo-depth = <0x100>;
 250                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 251                 status = "disabled";
 252         };
 253
 254         sdio: dwmmc@10218000 {
 255                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 256                 reg = <0x10218000 0x4000>;
 257                 clock-freq-min-max = <400000 37500000>;
 258                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 259                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 260                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 261                 fifo-depth = <0x100>;
 262                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 263                 status = "disabled";
 264         };
 265
 266         emmc: dwmmc@1021c000 {
 267                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 268                 reg = <0x1021c000 0x4000>;
 269                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 270                 bus-width = <8>;
 271                 cap-mmc-highspeed;
 272                 clock-frequency = <37500000>;
 273                 clock-freq-min-max = <400000 37500000>;
 274                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 275                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 276                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 277                 default-sample-phase = <158>;
 278                 disable-wp;
 279                 dmas = <&pdma 12>;
 280                 dma-names = "rx-tx";
 281                 fifo-depth = <0x100>;
 282                 mmc-ddr-1_8v;
 283                 non-removable;
 284                 num-slots = <1>;
 285                 supports-emmc;
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 288                 status = "disabled";
 289         };
 290
 291         i2s: i2s@10220000 {
 292                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 293                 reg = <0x10220000 0x4000>;
 294                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 clock-names = "i2s_clk", "i2s_hclk";
 298                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 299                 dmas = <&pdma 0>, <&pdma 1>;
 300                 dma-names = "tx", "rx";
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&i2s_bus>;
 303                 status = "disabled";
 304         };
 305
 306         cru: clock-controller@20000000 {
 307                 compatible = "rockchip,rk3036-cru";
 308                 reg = <0x20000000 0x1000>;
 309                 rockchip,grf = <&grf>;
 310                 #clock-cells = <1>;
 311                 #reset-cells = <1>;
 312                 assigned-clocks = <&cru PLL_GPLL>;
 313                 assigned-clock-rates = <594000000>;
 314         };
 315
 316         grf: syscon@20008000 {
 317                 compatible = "rockchip,rk3036-grf", "syscon";
 318                 reg = <0x20008000 0x1000>;
 319         };
 320
 321         acodec: acodec-ana@20030000 {
 322                 compatible = "rk3036-codec";
 323                 reg = <0x20030000 0x4000>;
 324                 rockchip,grf = <&grf>;
 325                 clock-names = "acodec_pclk";
 326                 clocks = <&cru PCLK_ACODEC>;
 327                 status = "disabled";
 328         };
 329
 330         hdmi: hdmi@20034000 {
 331                 compatible = "rockchip,rk3036-inno-hdmi";
 332                 reg = <0x20034000 0x4000>;
 333                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&cru  PCLK_HDMI>;
 335                 clock-names = "pclk";
 336                 rockchip,grf = <&grf>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&hdmi_ctl>;
 339                 status = "disabled";
 340
 341                 hdmi_in: port {
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         hdmi_in_vop: endpoint@0 {
 345                                 reg = <0>;
 346                                 remote-endpoint = <&vop_out_hdmi>;
 347                         };
 348                 };
 349         };
 350
 351         timer: timer@20044000 {
 352                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 353                 reg = <0x20044000 0x20>;
 354                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 356                 clock-names = "timer", "pclk";
 357         };
 358
 359         pwm0: pwm@20050000 {
 360                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 361                 reg = <0x20050000 0x10>;
 362                 #pwm-cells = <3>;
 363                 clocks = <&cru PCLK_PWM>;
 364                 clock-names = "pwm";
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pwm0_pin>;
 367                 status = "disabled";
 368         };
 369
 370         pwm1: pwm@20050010 {
 371                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 372                 reg = <0x20050010 0x10>;
 373                 #pwm-cells = <3>;
 374                 clocks = <&cru PCLK_PWM>;
 375                 clock-names = "pwm";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&pwm1_pin>;
 378                 status = "disabled";
 379         };
 380
 381         pwm2: pwm@20050020 {
 382                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 383                 reg = <0x20050020 0x10>;
 384                 #pwm-cells = <3>;
 385                 clocks = <&cru PCLK_PWM>;
 386                 clock-names = "pwm";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&pwm2_pin>;
 389                 status = "disabled";
 390         };
 391
 392         pwm3: pwm@20050030 {
 393                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 394                 reg = <0x20050030 0x10>;
 395                 #pwm-cells = <2>;
 396                 clocks = <&cru PCLK_PWM>;
 397                 clock-names = "pwm";
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pwm3_pin>;
 400                 status = "disabled";
 401         };
 402
 403         i2c1: i2c@20056000 {
 404                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 405                 reg = <0x20056000 0x1000>;
 406                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clock-names = "i2c";
 410                 clocks = <&cru PCLK_I2C1>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&i2c1_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         i2c2: i2c@2005a000 {
 417                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 418                 reg = <0x2005a000 0x1000>;
 419                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 clock-names = "i2c";
 423                 clocks = <&cru PCLK_I2C2>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&i2c2_xfer>;
 426                 status = "disabled";
 427         };
 428
 429         uart0: serial@20060000 {
 430                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 431                 reg = <0x20060000 0x100>;
 432                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 433                 reg-shift = <2>;
 434                 reg-io-width = <4>;
 435                 clock-frequency = <24000000>;
 436                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 437                 clock-names = "baudclk", "apb_pclk";
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 440                 status = "disabled";
 441         };
 442
 443         uart1: serial@20064000 {
 444                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 445                 reg = <0x20064000 0x100>;
 446                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 447                 reg-shift = <2>;
 448                 reg-io-width = <4>;
 449                 clock-frequency = <24000000>;
 450                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 451                 clock-names = "baudclk", "apb_pclk";
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&uart1_xfer>;
 454                 status = "disabled";
 455         };
 456
 457         uart2: serial@20068000 {
 458                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 459                 reg = <0x20068000 0x100>;
 460                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 461                 reg-shift = <2>;
 462                 reg-io-width = <4>;
 463                 clock-frequency = <24000000>;
 464                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 465                 clock-names = "baudclk", "apb_pclk";
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&uart2_xfer>;
 468                 status = "disabled";
 469         };
 470
 471         i2c0: i2c@20072000 {
 472                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 473                 reg = <0x20072000 0x1000>;
 474                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clock-names = "i2c";
 478                 clocks = <&cru PCLK_I2C0>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&i2c0_xfer>;
 481                 status = "disabled";
 482         };
 483
 484         spi: spi@20074000 {
 485                 compatible = "rockchip,rockchip-spi";
 486                 reg = <0x20074000 0x1000>;
 487                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 489                 clock-names = "apb-pclk","spi_pclk";
 490                 dmas = <&pdma 8>, <&pdma 9>;
 491                 dma-names = "tx", "rx";
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 status = "disabled";
 497         };
 498
 499         pinctrl: pinctrl {
 500                 compatible = "rockchip,rk3036-pinctrl";
 501                 rockchip,grf = <&grf>;
 502                 #address-cells = <1>;
 503                 #size-cells = <1>;
 504                 ranges;
 505
 506                 gpio0: gpio0@2007c000 {
 507                         compatible = "rockchip,gpio-bank";
 508                         reg = <0x2007c000 0x100>;
 509                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&cru PCLK_GPIO0>;
 511
 512                         gpio-controller;
 513                         #gpio-cells = <2>;
 514
 515                         interrupt-controller;
 516                         #interrupt-cells = <2>;
 517                 };
 518
 519                 gpio1: gpio1@20080000 {
 520                         compatible = "rockchip,gpio-bank";
 521                         reg = <0x20080000 0x100>;
 522                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&cru PCLK_GPIO1>;
 524
 525                         gpio-controller;
 526                         #gpio-cells = <2>;
 527
 528                         interrupt-controller;
 529                         #interrupt-cells = <2>;
 530                 };
 531
 532                 gpio2: gpio2@20084000 {
 533                         compatible = "rockchip,gpio-bank";
 534                         reg = <0x20084000 0x100>;
 535                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&cru PCLK_GPIO2>;
 537
 538                         gpio-controller;
 539                         #gpio-cells = <2>;
 540
 541                         interrupt-controller;
 542                         #interrupt-cells = <2>;
 543                 };
 544
 545                 pcfg_pull_default: pcfg_pull_default {
 546                         bias-pull-pin-default;
 547                 };
 548
 549                 pcfg_pull_none: pcfg-pull-none {
 550                         bias-disable;
 551                 };
 552
 553                 pwm0 {
 554                         pwm0_pin: pwm0-pin {
 555                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 556                         };
 557                 };
 558
 559                 pwm1 {
 560                         pwm1_pin: pwm1-pin {
 561                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 562                         };
 563                 };
 564
 565                 pwm2 {
 566                         pwm2_pin: pwm2-pin {
 567                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 568                         };
 569                 };
 570
 571                 pwm3 {
 572                         pwm3_pin: pwm3-pin {
 573                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 574                         };
 575                 };
 576
 577                 sdmmc {
 578                         sdmmc_clk: sdmmc-clk {
 579                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 580                         };
 581
 582                         sdmmc_cmd: sdmmc-cmd {
 583                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 584                         };
 585
 586                         sdmmc_cd: sdmcc-cd {
 587                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 588                         };
 589
 590                         sdmmc_bus1: sdmmc-bus1 {
 591                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 592                         };
 593
 594                         sdmmc_bus4: sdmmc-bus4 {
 595                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 596                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 597                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 598                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 599                         };
 600                 };
 601
 602                 sdio {
 603                         sdio_bus1: sdio-bus1 {
 604                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 605                         };
 606
 607                         sdio_bus4: sdio-bus4 {
 608                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 609                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 610                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 611                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 612                         };
 613
 614                         sdio_cmd: sdio-cmd {
 615                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 616                         };
 617
 618                         sdio_clk: sdio-clk {
 619                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 620                         };
 621                 };
 622
 623                 emmc {
 624                         /*
 625                          * We run eMMC at max speed; bump up drive strength.
 626                          * We also have external pulls, so disable the internal ones.
 627                          */
 628                         emmc_clk: emmc-clk {
 629                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 630                         };
 631
 632                         emmc_cmd: emmc-cmd {
 633                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 634                         };
 635
 636                         emmc_bus8: emmc-bus8 {
 637                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 638                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 639                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 640                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 641                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 642                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 643                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 644                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 645                         };
 646                 };
 647
 648                 emac {
 649                         emac_xfer: emac-xfer {
 650                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 651                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 652                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 653                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 654                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 655                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 656                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 657                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 658                         };
 659
 660                         emac_mdio: emac-mdio {
 661                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 662                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 663                         };
 664                 };
 665
 666                 i2c0 {
 667                         i2c0_xfer: i2c0-xfer {
 668                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 669                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 670                         };
 671                 };
 672
 673                 i2c1 {
 674                         i2c1_xfer: i2c1-xfer {
 675                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 676                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 677                         };
 678                 };
 679
 680                 i2c2 {
 681                         i2c2_xfer: i2c2-xfer {
 682                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 683                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 684                         };
 685                 };
 686
 687                 i2s {
 688                         i2s_bus: i2s-bus {
 689                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 690                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 691                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 692                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 693                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 694                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 695                         };
 696                 };
 697
 698                 hdmi {
 699                         hdmi_ctl: hdmi-ctl {
 700                                 rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
 701                                                 <1 9  RK_FUNC_1 &pcfg_pull_none>,
 702                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,
 703                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;
 704                         };
 705                 };
 706
 707                 uart0 {
 708                         uart0_xfer: uart0-xfer {
 709                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 710                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 711                         };
 712
 713                         uart0_cts: uart0-cts {
 714                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 715                         };
 716
 717                         uart0_rts: uart0-rts {
 718                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 719                         };
 720                 };
 721
 722                 uart1 {
 723                         uart1_xfer: uart1-xfer {
 724                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 725                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 726                         };
 727                         /* no rts / cts for uart1 */
 728                 };
 729
 730                 uart2 {
 731                         uart2_xfer: uart2-xfer {
 732                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 733                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 734                         };
 735                         /* no rts / cts for uart2 */
 736                 };
 737
 738                 spi {
 739                         spi_txd:spi-txd {
 740                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 741                         };
 742
 743                         spi_rxd:spi-rxd {
 744                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 745                         };
 746
 747                         spi_clk:spi-clk {
 748                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 749                         };
 750
 751                         spi_cs0:spi-cs0 {
 752                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 753
 754                         };
 755
 756                         spi_cs1:spi-cs1 {
 757                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 758
 759                         };
 760                 };
 761         };
 762 };