1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/pinctrl/rockchip-rk3036.h>
7 pinctrl: pinctrl@20008000 {
8 compatible = "rockchip,rk3036-pinctrl";
9 reg = <0x20008000 0xA8>,
13 reg-names = "base", "mux", "pull", "drv";
18 gpio0: gpio0@2007c000 {
19 compatible = "rockchip,gpio-bank";
20 reg = <0x2007c000 0x100>;
21 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
22 clocks = <&clk_gates8 9>;
28 #interrupt-cells = <2>;
31 gpio1: gpio1@20080000 {
32 compatible = "rockchip,gpio-bank";
33 reg = <0x20080000 0x100>;
34 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&clk_gates8 10>;
41 #interrupt-cells = <2>;
44 gpio2: gpio2@20084000 {
45 compatible = "rockchip,gpio-bank";
46 reg = <0x20084000 0x100>;
47 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&clk_gates8 11>;
54 #interrupt-cells = <2>;
57 gpio15: gpio15@20086000 {
58 compatible = "rockchip,gpio-bank";
59 reg = <0x20086000 0x100>;
60 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;//127 = 160-32-1
61 clocks = <&clk_gates8 12>;
67 #interrupt-cells = <2>;
70 pcfg_pull_up: pcfg_pull_up {
74 pcfg_pull_down: pcfg_pull_down {
78 pcfg_pull_none: pcfg_pull_none {
83 uart0_xfer: uart0-xfer {
84 rockchip,pins = <UART0_SIN>,
86 rockchip,pull = <VALUE_PULL_DEFAULT>;
91 uart0_cts: uart0-cts {
92 rockchip,pins = <UART0_CTSN>;
93 rockchip,pull = <VALUE_PULL_DEFAULT>;
98 uart0_rts: uart0-rts {
99 rockchip,pins = <UART0_RTSN>;
100 rockchip,pull = <VALUE_PULL_DEFAULT>;
105 uart0_rts_gpio: uart0-rts-gpio {
106 rockchip,pins = <FUNC_TO_GPIO(UART0_RTSN)>;
107 rockchip,pull = <VALUE_PULL_DEFAULT>;
113 uart1_xfer: uart1-xfer {
114 rockchip,pins = <UART1_SIN>,
116 rockchip,pull = <VALUE_PULL_DEFAULT>;
124 uart2_xfer: uart2-xfer {
125 rockchip,pins = <UART2_SIN>,
127 rockchip,pull = <VALUE_PULL_DEFAULT>;
131 /* no rts / cts for uart2 */
137 rockchip,pins = <I2C0_SDA>;
138 rockchip,pull = <VALUE_PULL_DEFAULT>;
144 rockchip,pins = <I2C0_SCL>;
145 rockchip,pull = <VALUE_PULL_DEFAULT>;
150 i2c0_gpio: i2c0-gpio {
151 rockchip,pins = <FUNC_TO_GPIO(I2C0_SDA)>, <FUNC_TO_GPIO(I2C0_SCL)>;
152 rockchip,pull = <VALUE_PULL_DEFAULT>;
159 rockchip,pins = <I2C1_SDA>;
160 rockchip,pull = <VALUE_PULL_DEFAULT>;
166 rockchip,pins = <I2C1_SCL>;
167 rockchip,pull = <VALUE_PULL_DEFAULT>;
172 i2c1_gpio: i2c1-gpio {
173 rockchip,pins = <FUNC_TO_GPIO(I2C1_SDA)>, <FUNC_TO_GPIO(I2C1_SCL)>;
174 rockchip,pull = <VALUE_PULL_DEFAULT>;
181 rockchip,pins = <I2C2_SDA>;
182 rockchip,pull = <VALUE_PULL_DEFAULT>;
188 rockchip,pins = <I2C2_SCL>;
189 rockchip,pull = <VALUE_PULL_DEFAULT>;
194 i2c2_gpio: i2c2-gpio {
195 rockchip,pins = <FUNC_TO_GPIO(I2C2_SDA)>, <FUNC_TO_GPIO(I2C2_SCL)>;
196 rockchip,pull = <VALUE_PULL_DEFAULT>;
203 rockchip,pins = <SPI0_TXD>;
204 rockchip,pull = <VALUE_PULL_DEFAULT>;
210 rockchip,pins = <SPI0_RXD>;
211 rockchip,pull = <VALUE_PULL_DEFAULT>;
217 rockchip,pins = <SPI0_CLK>;
218 rockchip,pull = <VALUE_PULL_DEFAULT>;
224 rockchip,pins = <SPI0_CS0>;
225 rockchip,pull = <VALUE_PULL_DEFAULT>;
231 rockchip,pins = <SPI0_CS1>;
232 rockchip,pull = <VALUE_PULL_DEFAULT>;
241 rockchip,pins = <HDMI_CEC>;
242 rockchip,pull = <VALUE_PULL_DEFAULT>;
243 //rockchip,drive = <VALUE_DRV_DEFAULT>;
247 rockchip,pins = <HDMI_SDA>;
248 rockchip,pull = <VALUE_PULL_DEFAULT>;
249 //rockchip,drive = <VALUE_DRV_DEFAULT>;
253 rockchip,pins = <HDMI_SCL>;
254 rockchip,pull = <VALUE_PULL_DEFAULT>;
255 //rockchip,drive = <VALUE_DRV_DEFAULT>;
259 rockchip,pins = <HDMI_HPD>;
260 rockchip,pull = <VALUE_PULL_DEFAULT>;
261 //rockchip,drive = <VALUE_DRV_DEFAULT>;
265 hdmi_gpio: hdmi-gpio {
266 rockchip,pins = <FUNC_TO_GPIO(HDMI_CEC)>, <FUNC_TO_GPIO(HDMI_SDA)>, <FUNC_TO_GPIO(HDMI_SCL)>, <FUNC_TO_GPIO(HDMI_HPD)>;
267 rockchip,pull = <VALUE_PULL_DEFAULT>;
268 //rockchip,drive = <VALUE_DRV_DEFAULT>;
273 i2s0_mclk:i2s0-mclk {
274 rockchip,pins = <I2S0_MCLK>;
275 rockchip,pull = <VALUE_PULL_DEFAULT>;
279 i2s0_sclk:i2s0-sclk {
280 rockchip,pins = <I2S0_SCLK>;
281 rockchip,pull = <VALUE_PULL_DEFAULT>;
285 i2s0_lrckrx:i2s0-lrckrx {
286 rockchip,pins = <I2S0_LRCKRX>;
287 rockchip,pull = <VALUE_PULL_DEFAULT>;
291 i2s0_lrcktx:i2s0-lrcktx {
292 rockchip,pins = <I2S0_LRCKTX>;
293 rockchip,pull = <VALUE_PULL_DEFAULT>;
298 rockchip,pins = <I2S0_SDO>;
299 rockchip,pull = <VALUE_PULL_DEFAULT>;
304 rockchip,pins = <I2S0_SDI>;
305 rockchip,pull = <VALUE_PULL_DEFAULT>;
309 i2s0_gpio: i2s0-gpio {
310 rockchip,pins = <FUNC_TO_GPIO(I2S0_MCLK)>,
311 <FUNC_TO_GPIO(I2S0_SCLK)>,
312 <FUNC_TO_GPIO(I2S0_LRCKRX)>,
313 <FUNC_TO_GPIO(I2S0_LRCKTX)>,
314 <FUNC_TO_GPIO(I2S0_SDO)>,
315 <FUNC_TO_GPIO(I2S0_SDI)>;
316 rockchip,pull = <VALUE_PULL_DEFAULT>;
323 rockchip,pins = <SPDIF_TX>;
324 rockchip,pull = <VALUE_PULL_DEFAULT>;
330 emmc0_clk: emmc0-clk {
331 rockchip,pins = <EMMC_CLKOUT>;
332 rockchip,pull = <VALUE_PULL_DEFAULT>;
337 emmc0_cmd: emmc0-cmd {
338 rockchip,pins = <EMMC_CMD>;
339 rockchip,pull = <VALUE_PULL_UP>;
345 emmc0_bus1: emmc0-bus-width1 {
346 rockchip,pins = <EMMC_D0>;
347 rockchip,pull = <VALUE_PULL_UP>;
352 emmc0_bus4: emmc0-bus-width4 {
353 rockchip,pins = <EMMC_D0>,
357 rockchip,pull = <VALUE_PULL_UP>;
364 sdmmc0_clk: sdmmc0-clk {
365 rockchip,pins = <MMC0_CLKOUT>;
366 rockchip,pull = <VALUE_PULL_DEFAULT>;
371 sdmmc0_cmd: sdmmc0-cmd {
372 rockchip,pins = <MMC0_CMD>;
373 rockchip,pull = <VALUE_PULL_UP>;
377 sdmmc0_dectn: sdmmc0-dectn{
378 rockchip,pins = <MMC0_DETN>;
379 rockchip,pull = <VALUE_PULL_UP>;
385 sdmmc0_bus1: sdmmc0-bus-width1 {
386 rockchip,pins = <MMC0_D0>;
387 rockchip,pull = <VALUE_PULL_UP>;
392 sdmmc0_bus4: sdmmc0-bus-width4 {
393 rockchip,pins = <MMC0_D0>,
397 rockchip,pull = <VALUE_PULL_UP>;
402 sdmmc0_gpio: sdmmc0_gpio{
411 rockchip,pull = <VALUE_PULL_UP>;
419 nandc_ale:nandc-ale {
420 rockchip,pins = <NAND_ALE>;
421 rockchip,pull = <VALUE_PULL_DEFAULT>;
424 nandc_cle:nandc-cle {
425 rockchip,pins = <NAND_CLE>;
426 rockchip,pull = <VALUE_PULL_DEFAULT>;
429 nandc_wrn:nandc-wrn {
430 rockchip,pins = <NAND_WRN>;
431 rockchip,pull = <VALUE_PULL_DEFAULT>;
434 nandc_rdn:nandc-rdn {
435 rockchip,pins = <NAND_RDN>;
436 rockchip,pull = <VALUE_PULL_DEFAULT>;
439 nandc_rdy:nandc-rdy {
440 rockchip,pins = <NAND_RDY>;
441 rockchip,pull = <VALUE_PULL_DEFAULT>;
444 nandc_cs0:nandc-cs0 {
445 rockchip,pins = <NAND_CS0>;
446 rockchip,pull = <VALUE_PULL_DEFAULT>;
450 nandc_data: nandc-data {
451 rockchip,pins = <NAND_D0>,
459 rockchip,pull = <VALUE_PULL_DEFAULT>;
466 sdio0_clk: sdio0_clk {
467 rockchip,pins = <MMC1_CLKOUT>;
468 rockchip,pull = <VALUE_PULL_DEFAULT>;
473 sdio0_cmd: sdio0_cmd {
474 rockchip,pins = <MMC1_CMD>;
475 rockchip,pull = <VALUE_PULL_UP>;
480 sdio0_bus1: sdio0-bus-width1 {
481 rockchip,pins = <MMC1_D0>;
482 rockchip,pull = <VALUE_PULL_UP>;
487 sdio0_bus4: sdio0-bus-width4 {
488 rockchip,pins = <MMC1_D0>,
492 rockchip,pull = <VALUE_PULL_UP>;
497 sdio0_gpio: sdio0-all-gpio{
505 rockchip,pull = <VALUE_PULL_UP>;
513 rockchip,pins = <PWM0>;
514 rockchip,pull = <VALUE_PULL_DEFAULT>;
520 rockchip,pins = <PWM1>;
521 rockchip,pull = <VALUE_PULL_DEFAULT>;
527 rockchip,pins = <PWM2>;
528 rockchip,pull = <VALUE_PULL_DEFAULT>;
534 rockchip,pins = <PWM3(IR)>;
535 rockchip,pull = <VALUE_PULL_DEFAULT>;
543 rockchip,pins = <MAC_CLKOUT>;
544 rockchip,pull = <VALUE_PULL_DEFAULT>;
547 mac_txpins: mac-txpins {
548 rockchip,pins = <MAC_TXD0>, <MAC_TXD1>, <MAC_TXEN>;
549 rockchip,pull = <VALUE_PULL_DEFAULT>;
554 mac_rxpins: mac-rxpins {
555 rockchip,pins = <MAC_RXD0>, <MAC_RXD1>,<MAC_RXER>;
556 rockchip,pull = <VALUE_PULL_DEFAULT>;
562 rockchip,pins = <MAC_CRS>;
563 rockchip,pull = <VALUE_PULL_DEFAULT>;
568 mac_mdpins: mac-mdpins {
569 rockchip,pins = <MAC_MDIO>, <MAC_MDC>;
570 rockchip,pull = <VALUE_PULL_DEFAULT>;