2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3036.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x1f0>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
42 rmii_clkin: rmii_clkin {
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "rmii_clkin";
45 clock-frequency = <0>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "usb_480m";
52 clock-frequency = <480000000>;
56 i2s_clkin: i2s_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "i2s_clkin";
59 clock-frequency = <0>;
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_tck";
66 clock-frequency = <0>;
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "dummy";
73 clock-frequency = <0>;
77 dummy_cpll: dummy_cpll {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "dummy_cpll";
80 clock-frequency = <0>;
87 compatible = "rockchip,rk-fixed-factor-cons";
89 otgphy0_12m: otgphy0_12m {
90 compatible = "rockchip,rk-fixed-factor-clock";
91 clocks = <&clk_gates1 5>;
92 clock-output-names = "otgphy0_12m";
100 compatible = "rockchip,rk-clock-regs";
101 #address-cells = <1>;
103 reg = <0x0000 0x01f0>;
106 /* PLL control regs */
108 compatible = "rockchip,rk-pll-cons";
109 #address-cells = <1>;
113 clk_apll: pll-clk@0000 {
114 compatible = "rockchip,rk3188-pll-clk";
116 mode-reg = <0x0040 0>;
117 status-reg = <0x0004 10>;
119 clock-output-names = "clk_apll";
120 rockchip,pll-type = <CLK_PLL_3036_APLL>;
124 clk_dpll: pll-clk@0010 {
125 compatible = "rockchip,rk3188-pll-clk";
127 mode-reg = <0x0040 4>;
128 status-reg = <0x0014 10>;
130 clock-output-names = "clk_dpll";
131 rockchip,pll-type = <CLK_PLL_3188PLUS>;
135 clk_gpll: pll-clk@0030 {
136 compatible = "rockchip,rk3188-pll-clk";
138 mode-reg = <0x0040 12>;
139 status-reg = <0x0034 10>;
141 clock-output-names = "clk_gpll";
142 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
144 #clock-init-cells = <1>;
149 /* Select control regs */
151 compatible = "rockchip,rk-sel-cons";
152 #address-cells = <1>;
156 clk_sel_con0: sel-con@0044 {
157 compatible = "rockchip,rk3188-selcon";
159 #address-cells = <1>;
162 clk_core_pre_div: clk_core_pre_div {
163 compatible = "rockchip,rk3188-div-con";
164 rockchip,bits = <0 5>;
165 clocks = <&clk_core_pre>;
166 clock-output-names = "clk_core_pre";
167 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
169 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
170 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
171 CLK_SET_RATE_NO_REPARENT)>;
174 /* reg[6:5]: reserved */
176 clk_core_pre: clk_core_pre_mux {
177 compatible = "rockchip,rk3188-mux-con";
178 rockchip,bits = <7 1>;
179 clocks = <&clk_apll>, <&clk_gates0 6>;
180 clock-output-names = "clk_core_pre";
182 #clock-init-cells = <1>;
185 aclk_cpu_pre_div: aclk_cpu_pre_div {
186 compatible = "rockchip,rk3188-div-con";
187 rockchip,bits = <8 5>;
188 clocks = <&aclk_cpu_pre>;
189 clock-output-names = "aclk_cpu_pre";
190 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
192 rockchip,clkops-idx =
193 <CLKOPS_RATE_MUX_DIV>;
194 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
197 /* reg[13]: reserved */
199 aclk_cpu_pre: aclk_cpu_pre_mux {
200 compatible = "rockchip,rk3188-mux-con";
201 rockchip,bits = <14 2>;
202 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
203 clock-output-names = "aclk_cpu_pre";
205 #clock-init-cells = <1>;
210 clk_sel_con1: sel-con@0048 {
211 compatible = "rockchip,rk3188-selcon";
213 #address-cells = <1>;
216 pclk_dbg_div: pclk_dbg_div {
217 compatible = "rockchip,rk3188-div-con";
218 rockchip,bits = <0 4>;
219 clocks = <&clk_core_pre>;
220 clock-output-names = "pclk_dbg";
221 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
223 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
226 aclk_core_pre: aclk_core_pre_div {
227 compatible = "rockchip,rk3188-div-con";
228 rockchip,bits = <4 3>;
229 clocks = <&clk_core_pre>;
230 clock-output-names = "aclk_core_pre";
231 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
233 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
236 /* reg[7]: reserved */
238 hclk_cpu_pre: hclk_cpu_pre_div {
239 compatible = "rockchip,rk3188-div-con";
240 rockchip,bits = <8 2>;
241 clocks = <&aclk_cpu_pre>;
242 clock-output-names = "hclk_cpu_pre";
243 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
245 #clock-init-cells = <1>;
248 /* reg[11:10]: reserved */
250 pclk_cpu_pre: pclk_cpu_pre_div {
251 compatible = "rockchip,rk3188-div-con";
252 rockchip,bits = <12 3>;
253 clocks = <&aclk_cpu_pre>;
254 clock-output-names = "pclk_cpu_pre";
255 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
257 #clock-init-cells = <1>;
260 /* reg[15]: reserved */
263 clk_sel_con2: sel-con@004c {
264 compatible = "rockchip,rk3188-selcon";
266 #address-cells = <1>;
269 /* reg[3:0]: reserved */
271 clk_timer0: clk_timer0_mux {
272 compatible = "rockchip,rk3188-mux-con";
273 rockchip,bits = <4 1>;
274 clocks = <&xin24m>, <&aclk_peri_pre>;
275 clock-output-names = "clk_timer0";
277 #clock-init-cells = <1>;
280 clk_timer1: clk_timer1_mux {
281 compatible = "rockchip,rk3188-mux-con";
282 rockchip,bits = <5 1>;
283 clocks = <&xin24m>, <&aclk_peri_pre>;
284 clock-output-names = "clk_timer1";
286 #clock-init-cells = <1>;
289 clk_timer2: clk_timer2_mux {
290 compatible = "rockchip,rk3188-mux-con";
291 rockchip,bits = <6 1>;
292 clocks = <&xin24m>, <&aclk_peri_pre>;
293 clock-output-names = "clk_timer2";
295 #clock-init-cells = <1>;
298 clk_timer3: clk_timer3_mux {
299 compatible = "rockchip,rk3188-mux-con";
300 rockchip,bits = <7 1>;
301 clocks = <&xin24m>, <&aclk_peri_pre>;
302 clock-output-names = "clk_timer3";
304 #clock-init-cells = <1>;
307 /* reg[15:8]: reserved */
310 clk_sel_con3: sel-con@0050 {
311 compatible = "rockchip,rk3188-selcon";
313 #address-cells = <1>;
316 clk_i2s_pll_div: clk_i2s_pll_div {
317 compatible = "rockchip,rk3188-div-con";
318 rockchip,bits = <0 7>;
319 clocks = <&clk_i2s_pll>;
320 clock-output-names = "clk_i2s_pll";
321 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
323 rockchip,clkops-idx =
324 <CLKOPS_RATE_MUX_DIV>;
325 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
328 /* reg[7]: reserved */
330 clk_i2s: clk_i2s_mux {
331 compatible = "rockchip,rk3188-mux-con";
332 rockchip,bits = <8 2>;
333 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
334 clock-output-names = "clk_i2s";
336 rockchip,clkops-idx =
337 <CLKOPS_RATE_RK3288_I2S>;
338 rockchip,flags = <CLK_SET_RATE_PARENT>;
341 /* reg[11:10]: reserved */
343 clk_i2s_out: i2s_outclk_mux {
344 compatible = "rockchip,rk3188-mux-con";
345 rockchip,bits = <12 1>;
346 clocks = <&xin12m>, <&clk_i2s>;
347 clock-output-names = "i2s_clkout";
351 /* reg[13]: reserved */
353 clk_i2s_pll: i2s_pll_mux {
354 compatible = "rockchip,rk3188-mux-con";
355 rockchip,bits = <14 2>;
356 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
357 clock-output-names = "clk_i2s_pll";
359 #clock-init-cells = <1>;
364 clk_sel_con5: sel-con@0058 {
365 compatible = "rockchip,rk3188-selcon";
367 #address-cells = <1>;
370 spdif_div: spdif_div {
371 compatible = "rockchip,rk3188-div-con";
372 rockchip,bits = <0 7>;
373 clocks = <&clk_spdif_pll>;
374 clock-output-names = "clk_spdif_pll";
375 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
377 rockchip,clkops-idx =
378 <CLKOPS_RATE_MUX_DIV>;
379 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
382 /* reg[7]: reserved */
384 clk_spdif: spdif_mux {
385 compatible = "rockchip,rk3188-mux-con";
386 rockchip,bits = <8 2>;
387 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
388 clock-output-names = "clk_spdif";
390 rockchip,clkops-idx =
391 <CLKOPS_RATE_RK3288_I2S>;
392 rockchip,flags = <CLK_SET_RATE_PARENT>;
395 clk_spdif_pll: spdif_pll_mux {
396 compatible = "rockchip,rk3188-mux-con";
397 rockchip,bits = <10 2>;
398 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
399 clock-output-names = "clk_spdif_pll";
401 #clock-init-cells = <1>;
404 /* reg[15:12]: reserved */
407 clk_sel_con7: sel-con@0060 {
408 compatible = "rockchip,rk3188-selcon";
410 #address-cells = <1>;
414 compatible = "rockchip,rk3188-frac-con";
415 clocks = <&clk_i2s_pll>;
416 clock-output-names = "i2s_frac";
417 /* numerator denominator */
418 rockchip,bits = <0 32>;
419 rockchip,clkops-idx =
425 clk_sel_con9: sel-con@0068 {
426 compatible = "rockchip,rk3188-selcon";
428 #address-cells = <1>;
431 spdif_frac: spdif_frac {
432 compatible = "rockchip,rk3188-frac-con";
433 clocks = <&spdif_div>;
434 clock-output-names = "spdif_frac";
435 /* numerator denominator */
436 rockchip,bits = <0 32>;
437 rockchip,clkops-idx =
443 clk_sel_con10: sel-con@006c {
444 compatible = "rockchip,rk3188-selcon";
446 #address-cells = <1>;
449 aclk_peri_pre_div: aclk_peri_pre_div {
450 compatible = "rockchip,rk3188-div-con";
451 rockchip,bits = <0 5>;
452 clocks = <&aclk_peri_pre>;
453 clock-output-names = "aclk_peri_pre";
454 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
456 rockchip,clkops-idx =
457 <CLKOPS_RATE_MUX_DIV>;
458 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
461 /* reg[7:5]: reserved */
463 hclk_peri_pre: hclk_peri_pre_div {
464 compatible = "rockchip,rk3188-div-con";
465 rockchip,bits = <8 2>;
466 clocks = <&aclk_peri_pre>;
467 clock-output-names = "hclk_peri_pre";
468 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
469 rockchip,div-relations =
474 #clock-init-cells = <1>;
477 /* reg[11:10]: reserved */
479 pclk_peri_pre: pclk_peri_div {
480 compatible = "rockchip,rk3188-div-con";
481 rockchip,bits = <12 2>;
482 clocks = <&aclk_peri_pre>;
483 clock-output-names = "pclk_peri_pre";
484 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
485 rockchip,div-relations =
491 #clock-init-cells = <1>;
494 aclk_peri_pre: aclk_peri_pre_mux {
495 compatible = "rockchip,rk3188-mux-con";
496 rockchip,bits = <14 2>;
497 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
498 clock-output-names = "aclk_peri_pre";
500 #clock-init-cells = <1>;
504 clk_sel_con11: sel-con@0070 {
505 compatible = "rockchip,rk3188-selcon";
507 #address-cells = <1>;
510 clk_sdmmc0_div: clk_sdmmc0_div {
511 compatible = "rockchip,rk3188-div-con";
512 rockchip,bits = <0 6>;
513 clocks = <&clk_sdmmc0>;
514 clock-output-names = "clk_sdmmc0";
515 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
517 rockchip,clkops-idx =
518 <CLKOPS_RATE_MUX_EVENDIV>;
521 /* reg[7]: reserved */
523 clk_sdio_div: clk_sdio_div {
524 compatible = "rockchip,rk3188-div-con";
525 rockchip,bits = <8 7>;
526 clocks = <&clk_sdio>;
527 clock-output-names = "clk_sdio";
528 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
530 rockchip,clkops-idx =
531 <CLKOPS_RATE_MUX_EVENDIV>;
534 /* reg[15]: reserved */
538 clk_sel_con12: sel-con@0074 {
539 compatible = "rockchip,rk3188-selcon";
541 #address-cells = <1>;
544 clk_emmc_div: clk_emmc_div {
545 compatible = "rockchip,rk3188-div-con";
546 rockchip,bits = <0 7>;
547 clocks = <&clk_emmc>;
548 clock-output-names = "clk_emmc";
549 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
551 rockchip,clkops-idx =
552 <CLKOPS_RATE_MUX_EVENDIV>;
555 /* reg[7]: reserved */
557 clk_sdmmc0: clk_sdmmc0_mux {
558 compatible = "rockchip,rk3188-mux-con";
559 rockchip,bits = <8 2>;
560 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
561 clock-output-names = "clk_sdmmc0";
565 clk_sdio: clk_sdio_mux {
566 compatible = "rockchip,rk3188-mux-con";
567 rockchip,bits = <10 2>;
568 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
569 clock-output-names = "clk_sdio";
573 clk_emmc: clk_emmc_mux {
574 compatible = "rockchip,rk3188-mux-con";
575 rockchip,bits = <12 2>;
576 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
577 clock-output-names = "clk_emmc";
581 /* reg[15:14]: reserved */
584 clk_sel_con13: sel-con@0078 {
585 compatible = "rockchip,rk3188-selcon";
587 #address-cells = <1>;
590 clk_uart0_div: clk_uart0_div {
591 compatible = "rockchip,rk3188-div-con";
592 rockchip,bits = <0 7>;
593 clocks = <&clk_uart_pll>;
594 clock-output-names = "clk_uart0_div";
595 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
599 /* reg[7]: reserved */
601 clk_uart0: clk_uart0_mux {
602 compatible = "rockchip,rk3188-mux-con";
603 rockchip,bits = <8 2>;
604 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
605 clock-output-names = "clk_uart0";
607 rockchip,clkops-idx =
608 <CLKOPS_RATE_RK3288_I2S>;
609 rockchip,flags = <CLK_SET_RATE_PARENT>;
612 clk_uart_pll: clk_uart_pll_mux {
613 compatible = "rockchip,rk3188-mux-con";
614 rockchip,bits = <10 2>;
615 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
616 clock-output-names = "clk_uart_pll";
618 #clock-init-cells = <1>;
621 /* reg[15:12]: reserved */
625 clk_sel_con14: sel-con@007c {
626 compatible = "rockchip,rk3188-selcon";
628 #address-cells = <1>;
631 clk_uart1_div: clk_uart1_div {
632 compatible = "rockchip,rk3188-div-con";
633 rockchip,bits = <0 7>;
634 clocks = <&clk_uart_pll>;
635 clock-output-names = "clk_uart1_div";
636 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
640 /* reg[7]: reserved */
642 clk_uart1: clk_uart1_mux {
643 compatible = "rockchip,rk3188-mux-con";
644 rockchip,bits = <8 2>;
645 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
646 clock-output-names = "clk_uart1";
648 rockchip,clkops-idx =
649 <CLKOPS_RATE_RK3288_I2S>;
650 rockchip,flags = <CLK_SET_RATE_PARENT>;
653 /* reg[15:10]: reserved */
656 clk_sel_con15: sel-con@0080 {
657 compatible = "rockchip,rk3188-selcon";
659 #address-cells = <1>;
662 clk_uart2_div: clk_uart2_div {
663 compatible = "rockchip,rk3188-div-con";
664 rockchip,bits = <0 7>;
665 clocks = <&clk_uart_pll>;
666 clock-output-names = "clk_uart2_div";
667 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
671 /* reg[7]: reserved */
673 clk_uart2: clk_uart2_mux {
674 compatible = "rockchip,rk3188-mux-con";
675 rockchip,bits = <8 2>;
676 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
677 clock-output-names = "clk_uart2";
679 rockchip,clkops-idx =
680 <CLKOPS_RATE_RK3288_I2S>;
681 rockchip,flags = <CLK_SET_RATE_PARENT>;
684 /* reg[15:10]: reserved */
687 clk_sel_con16: sel-con@0084 {
688 compatible = "rockchip,rk3188-selcon";
690 #address-cells = <1>;
693 clk_sfc: clk_sfc_mux {
694 compatible = "rockchip,rk3188-mux-con";
695 rockchip,bits = <0 2>;
696 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
697 clock-output-names = "clk_sfc";
701 clk_sfc_div: clk_sfc_div {
702 compatible = "rockchip,rk3188-div-con";
703 rockchip,bits = <2 5>;
705 clock-output-names = "clk_sfc";
706 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
708 rockchip,clkops-idx =
709 <CLKOPS_RATE_MUX_DIV>;
712 /* reg[7]: reserved */
714 clk_nandc: clk_nandc_mux {
715 compatible = "rockchip,rk3188-mux-con";
716 rockchip,bits = <8 2>;
717 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
718 clock-output-names = "clk_nandc";
722 clk_nandc_div: clk_nandc_div {
723 compatible = "rockchip,rk3188-div-con";
724 rockchip,bits = <10 5>;
725 clocks = <&clk_nandc>;
726 clock-output-names = "clk_nandc";
727 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
729 rockchip,clkops-idx =
730 <CLKOPS_RATE_MUX_DIV>;
733 /* reg[31:15]: reserved */
736 clk_sel_con17: sel-con@0088 {
737 compatible = "rockchip,rk3188-selcon";
739 #address-cells = <1>;
742 uart0_frac: uart0_frac {
743 compatible = "rockchip,rk3188-frac-con";
744 clocks = <&clk_uart0_div>;
745 clock-output-names = "uart0_frac";
746 /* numerator denominator */
747 rockchip,bits = <0 32>;
748 rockchip,clkops-idx =
754 clk_sel_con18: sel-con@008c {
755 compatible = "rockchip,rk3188-selcon";
757 #address-cells = <1>;
760 uart1_frac: uart1_frac {
761 compatible = "rockchip,rk3188-frac-con";
762 clocks = <&clk_uart1_div>;
763 clock-output-names = "uart1_frac";
764 /* numerator denominator */
765 rockchip,bits = <0 32>;
766 rockchip,clkops-idx =
772 clk_sel_con19: sel-con@0090 {
773 compatible = "rockchip,rk3188-selcon";
775 #address-cells = <1>;
778 uart2_frac: uart2_frac {
779 compatible = "rockchip,rk3188-frac-con";
780 clocks = <&clk_uart2_div>;
781 clock-output-names = "uart2_frac";
782 /* numerator denominator */
783 rockchip,bits = <0 32>;
784 rockchip,clkops-idx =
791 clk_sel_con20: sel-con@0094 {
792 compatible = "rockchip,rk3188-selcon";
794 #address-cells = <1>;
797 clk_hevc_core: clk_hevc_core_mux {
798 compatible = "rockchip,rk3188-mux-con";
799 rockchip,bits = <0 2>;
800 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
801 clock-output-names = "clk_hevc_core";
803 #clock-init-cells = <1>;
806 clk_hevc_core_div: clk_hevc_core_div {
807 compatible = "rockchip,rk3188-div-con";
808 rockchip,bits = <2 5>;
809 clocks = <&clk_hevc_core>;
810 clock-output-names = "clk_hevc_core";
811 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
813 rockchip,clkops-idx =
814 <CLKOPS_RATE_MUX_DIV>;
817 /* reg[31:7]: reserved */
821 clk_sel_con21: sel-con@0098 {
822 compatible = "rockchip,rk3188-selcon";
824 #address-cells = <1>;
827 clk_mac_pll: clk_mac_pll_mux {
828 compatible = "rockchip,rk3188-mux-con";
829 rockchip,bits = <0 2>;
830 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
831 clock-output-names = "clk_mac_pll";
835 /* reg[2]: reserved */
837 clk_mac_ref: clk_mac_ref_mux {
838 compatible = "rockchip,rk3188-mux-con";
839 rockchip,bits = <3 1>;
840 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
841 clock-output-names = "clk_mac_ref";
843 rockchip,clkops-idx =
844 <CLKOPS_RATE_MAC_REF>;
845 rockchip,flags = <CLK_SET_RATE_PARENT>;
846 #clock-init-cells = <1>;
849 clk_mac_pll_div: clk_mac_pll_div {
850 compatible = "rockchip,rk3188-div-con";
851 rockchip,bits = <4 5>;
852 clocks = <&clk_mac_pll>;
853 clock-output-names = "clk_mac_pll";
854 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
856 rockchip,clkops-idx =
857 <CLKOPS_RATE_MUX_DIV>;
860 clk_mac_ref_div: clk_mac_ref_div {
861 compatible = "rockchip,rk3188-div-con";
862 rockchip,bits = <9 5>;
863 clocks = <&clk_mac_ref>;
864 clock-output-names = "clk_mac";
865 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
867 #clock-init-cells = <1>;
870 /* reg[15:14]: reserved */
873 clk_sel_con25: sel-con@00a8 {
874 compatible = "rockchip,rk3188-selcon";
876 #address-cells = <1>;
879 clk_spi0_div: clk_spi0_div {
880 compatible = "rockchip,rk3188-div-con";
881 rockchip,bits = <0 7>;
882 clocks = <&clk_spi0>;
883 clock-output-names = "clk_spi0";
884 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
886 rockchip,clkops-idx =
887 <CLKOPS_RATE_MUX_DIV>;
890 /* reg[7]: reserved */
892 clk_spi0: clk_spi0_mux {
893 compatible = "rockchip,rk3188-mux-con";
894 rockchip,bits = <8 2>;
895 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
896 clock-output-names = "clk_spi0";
900 /* reg[15:10]: reserved */
904 clk_sel_con26: sel-con@00ac {
905 compatible = "rockchip,rk3188-selcon";
907 #address-cells = <1>;
911 compatible = "rockchip,rk3188-div-con";
912 rockchip,bits = <0 2>;
914 clock-output-names = "clk_ddr";
915 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
916 rockchip,div-relations =
921 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
922 CLK_SET_RATE_NO_REPARENT)>;
923 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
926 /* reg[7:1]: reserved */
928 clk_ddr: ddr_clk_pll_mux {
929 compatible = "rockchip,rk3188-mux-con";
930 rockchip,bits = <8 1>;
931 clocks = <&clk_gates0 2>, <&clk_gates0 8>;
932 clock-output-names = "clk_ddr";
936 /* reg[15:9]: reserved */
939 clk_sel_con28: sel-con@00b4 {
940 compatible = "rockchip,rk3188-selcon";
942 #address-cells = <1>;
945 dclk_lcdc1: dclk_lcdc1_mux {
946 compatible = "rockchip,rk3188-mux-con";
947 rockchip,bits = <0 2>;
948 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
949 clock-output-names = "dclk_lcdc1";
951 #clock-init-cells = <1>;
954 /* reg[7:2]: reserved */
956 dclk_lcdc1_div: dclk_lcdc1_div {
957 compatible = "rockchip,rk3188-div-con";
958 rockchip,bits = <8 8>;
959 clocks = <&dclk_lcdc1>;
960 clock-output-names = "dclk_lcdc1";
961 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
963 rockchip,clkops-idx =
964 <CLKOPS_RATE_MUX_DIV>;
965 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
969 clk_sel_con30: sel-con@00bc {
970 compatible = "rockchip,rk3188-selcon";
972 #address-cells = <1>;
975 clk_testout_div: clk_testout_div {
976 compatible = "rockchip,rk3188-div-con";
977 rockchip,bits = <0 5>;
979 clock-output-names = "clk_testout";
980 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
982 #clock-init-cells = <1>;
985 /* reg[7:5]: reserved */
987 hclk_vio_pre_div: hclk_vio_pre_div {
988 compatible = "rockchip,rk3188-div-con";
989 rockchip,bits = <8 5>;
990 clocks = <&hclk_vio_pre>;
991 clock-output-names = "hclk_vio_pre";
992 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
994 rockchip,clkops-idx =
995 <CLKOPS_RATE_MUX_DIV>;
996 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
999 /* reg[13]: reserved */
1001 hclk_vio_pre: hclk_vio_pre_mux {
1002 compatible = "rockchip,rk3188-mux-con";
1003 rockchip,bits = <14 2>;
1004 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1005 clock-output-names = "hclk_vio_pre";
1007 #clock-init-cells = <1>;
1012 clk_sel_con31: sel-con@00c0 {
1013 compatible = "rockchip,rk3188-selcon";
1015 #address-cells = <1>;
1018 clk_hdmi: clk_hdmi_mux {
1019 compatible = "rockchip,rk3188-mux-con";
1020 rockchip,bits = <0 1>;
1021 clocks = <&dclk_lcdc1_div>, <&dummy>;
1022 clock-output-names = "clk_hdmi";
1026 /* reg[7:1]: reserved */
1028 aclk_vio_pre_div: aclk_vio_pre_div {
1029 compatible = "rockchip,rk3188-div-con";
1030 rockchip,bits = <8 5>;
1031 clocks = <&aclk_vio_pre>;
1032 clock-output-names = "aclk_vio_pre";
1033 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1035 rockchip,clkops-idx =
1036 <CLKOPS_RATE_MUX_DIV>;
1037 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1040 /* reg[13]: reserved */
1042 aclk_vio_pre: aclk_vio_pre_mux {
1043 compatible = "rockchip,rk3188-mux-con";
1044 rockchip,bits = <14 2>;
1045 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1046 clock-output-names = "aclk_vio_pre";
1048 #clock-init-cells = <1>;
1053 clk_sel_con32: sel-con@00c4 {
1054 compatible = "rockchip,rk3188-selcon";
1056 #address-cells = <1>;
1059 /* reg[7:0]: reserved */
1061 aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1062 compatible = "rockchip,rk3188-div-con";
1063 rockchip,bits = <8 5>;
1064 clocks = <&aclk_vcodec_pre>;
1065 clock-output-names = "aclk_vcodec_pre";
1066 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1068 rockchip,clkops-idx =
1069 <CLKOPS_RATE_MUX_DIV>;
1072 /* reg[13]: reserved */
1074 aclk_vcodec_pre: aclk_vcodec_pre_mux {
1075 compatible = "rockchip,rk3188-mux-con";
1076 rockchip,bits = <14 2>;
1077 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1078 clock-output-names = "aclk_vcodec_pre";
1080 #clock-init-cells = <1>;
1084 clk_sel_con34: sel-con@00cc {
1085 compatible = "rockchip,rk3188-selcon";
1087 #address-cells = <1>;
1090 clk_gpu_pre_div: clk_gpu_pre_div {
1091 compatible = "rockchip,rk3188-div-con";
1092 rockchip,bits = <0 5>;
1093 clocks = <&clk_gpu_pre>;
1094 clock-output-names = "clk_gpu_pre";
1095 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1097 rockchip,clkops-idx =
1098 <CLKOPS_RATE_MUX_DIV>;
1099 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1102 /* reg[7:5]: reserved */
1104 clk_gpu_pre: clk_gpu_pre_mux {
1105 compatible = "rockchip,rk3188-mux-con";
1106 rockchip,bits = <8 2>;
1107 clocks = <&dummy>, <&clk_dpll>, <&clk_gpll>;
1108 clock-output-names = "clk_gpu_pre";
1110 #clock-init-cells = <1>;
1113 /* reg[15:10]: reserved */
1120 /* Gate control regs */
1122 compatible = "rockchip,rk-gate-cons";
1123 #address-cells = <1>;
1127 clk_gates0: gate-clk@00d0{
1128 compatible = "rockchip,rk3188-gate-clk";
1131 <&clk_core_pre>, <&clk_gpll>,
1132 <&clk_dpll>, <&aclk_cpu_pre>,
1134 <&aclk_cpu_pre>, <&aclk_cpu_pre>,
1135 <&clk_gpll>, <&clk_core_pre>,
1137 <&clk_gpll>, <&clk_i2s_pll>,
1138 <&i2s_frac>, <&hclk_vio_pre>,
1140 <&dummy>, <&clk_i2s_out>,
1141 <&clk_i2s>, <&dummy>;
1143 clock-output-names =
1144 "pclk_dbg", "reserved", /* do not use bit1 = "cpu_gpll" */
1145 "reserved", "aclk_cpu_pre",
1147 "hclk_cpu_pre", "pclk_cpu_pre",
1148 "reserved", "aclk_core_pre",
1150 "reserved", "clk_i2s_pll",
1151 "i2s_frac", "hclk_vio_pre",
1153 "clk_cryto", "clk_i2s_out",
1154 "clk_i2s", "clk_testout";
1155 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1160 clk_gates1: gate-clk@00d4{
1161 compatible = "rockchip,rk3188-gate-clk";
1164 <&clk_timer0>, <&clk_timer1>,
1165 <&dummy>, <&jtag_tck>,
1167 <&aclk_vio_pre>, <&xin12m>,
1170 <&clk_uart0_div>, <&uart0_frac>,
1171 <&clk_uart1_div>, <&uart1_frac>,
1173 <&clk_uart2_div>, <&uart2_frac>,
1176 clock-output-names =
1177 "clk_timer0", "clk_timer1",
1178 "reserved", "clk_jatg",
1180 "aclk_vio_pre", "clk_otgphy0",
1181 "clk_otgphy1", "reserved",
1183 "clk_uart0_div", "uart0_frac",
1184 "clk_uart1_div", "uart1_frac",
1186 "clk_uart2_div", "uart2_frac",
1187 "reserved", "reserved";
1189 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1193 clk_gates2: gate-clk@00d8 {
1194 compatible = "rockchip,rk3188-gate-clk";
1197 <&aclk_peri_pre>, <&aclk_peri_pre>,
1198 <&aclk_peri_pre>, <&aclk_peri_pre>,
1200 <&clk_timer2>, <&clk_timer3>,
1201 <&clk_mac_ref>, <&dummy>,
1203 <&dummy>, <&clk_spi0>,
1204 <&clk_spdif_pll>, <&clk_sdmmc0>,
1206 <&spdif_frac>, <&clk_sdio>,
1207 <&clk_emmc>, <&dummy>;
1209 clock-output-names =
1210 "aclk_peri", "aclk_peri_pre",
1211 "hclk_peri_pre", "pclk_peri_pre",
1213 "clk_timer2", "clk_timer3",
1214 "clk_mac", "reserved",
1216 "reserved", "clk_spi0",
1217 "clk_spdif_pll", "clk_sdmmc0",
1219 "spdif_frac", "clk_sdio",
1220 "clk_emmc", "reserved";
1221 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1226 clk_gates3: gate-clk@00dc {
1227 compatible = "rockchip,rk3188-gate-clk";
1231 <&dclk_lcdc1>, <&dummy>,
1236 <&pclk_cpu_pre>, <&dummy>,
1237 <&dummy>, <&aclk_vcodec_pre>,
1239 <&aclk_vcodec_pre>, <&clk_gpu_pre>,
1240 <&hclk_peri_pre>, <&dummy>;
1242 clock-output-names =
1243 "reserved", "reserved",
1244 "dclk_lcdc1", "reserved",
1246 "reserved", "reserved",
1247 "reserved", "reserved",
1249 "g_pclk_hdmi", "reserved",
1250 "reserved", "aclk_vcodec_pre",
1252 "hclk_vcodec", "clk_gpu_pre",
1253 "g_hclk_sfc", "reserved";
1254 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1259 clk_gates4: gate-clk@00e0{
1260 compatible = "rockchip,rk3188-gate-clk";
1263 <&hclk_peri_pre>, <&pclk_peri_pre>,
1264 <&aclk_peri_pre>, <&aclk_peri_pre>,
1270 <&aclk_cpu_pre>, <&dummy>,
1272 <&aclk_cpu_pre>, <&dummy>,
1275 clock-output-names =
1276 "g_hp_axi_matrix", "g_pp_axi_matrix",
1277 "g_aclk_cpu_peri", "g_ap_axi_matrix",
1279 "reserved", "reserved",
1280 "reserved", "reserved",
1282 "reserved", "reserved",
1283 "g_aclk_strc_sys", "reserved",
1285 /* Not use these ddr gates */
1286 "g_aclk_intmem", "reserved",
1287 "reserved", "reserved";
1289 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1293 clk_gates5: gate-clk@00e4 {
1294 compatible = "rockchip,rk3188-gate-clk";
1297 <&dummy>, <&aclk_peri_pre>,
1298 <&pclk_peri_pre>, <&dummy>,
1300 <&pclk_cpu_pre>, <&dummy>,
1301 <&hclk_cpu_pre>, <&pclk_cpu_pre>,
1303 <&dummy>, <&hclk_peri_pre>,
1304 <&hclk_peri_pre>, <&hclk_peri_pre>,
1306 <&dummy>, <&hclk_peri_pre>,
1307 <&pclk_cpu_pre>, <&dummy>;
1309 clock-output-names =
1310 "reserved", "g_aclk_dmac2",
1311 "g_pclk_efuse", "reserved",
1313 "g_pclk_grf", "reserved",
1314 "g_hclk_rom", "g_pclk_ddrupctl",
1316 "reserved", "g_hclk_nandc",
1317 "g_hclk_sdmmc0", "g_hclk_sdio",
1319 "reserved", "g_hclk_otg0",
1320 "g_pclk_acodec", "reserved";
1322 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1327 clk_gates6: gate-clk@00e8 {
1328 compatible = "rockchip,rk3188-gate-clk";
1340 <&hclk_vio_pre>, <&aclk_vio_pre>,
1343 clock-output-names =
1344 "reserved", "reserved",
1345 "reserved", "reserved",
1347 "reserved", "reserved",
1348 "reserved", "reserved",
1350 "reserved", "reserved",
1351 "reserved", "reserved",
1353 "g_hclk_vio_bus", "g_aclk_vio",
1354 "reserved", "reserved";
1356 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1361 clk_gates7: gate-clk@00ec {
1362 compatible = "rockchip,rk3188-gate-clk";
1365 <&hclk_peri_pre>, <&dummy>,
1366 <&hclk_peri_pre>, <&hclk_peri_pre>,
1369 <&dummy>, <&pclk_peri_pre>,
1372 <&pclk_peri_pre>, <&dummy>,
1374 <&pclk_peri_pre>, <&dummy>,
1375 <&dummy>, <&pclk_peri_pre>;
1377 clock-output-names =
1378 "g_hclk_emmc", "reserved",
1379 "g_hclk_i2s", "g_hclk_otg1",
1381 "reserved", "reserved",
1382 "reserved", "g_pclk_timer0",
1384 "reserved", "reserved",
1385 "g_pclk_pwm", "reserved",
1387 "g_pclk_spi", "reserved",
1388 "reserved", "g_pclk_wdt";
1390 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1395 clk_gates8: gate-clk@00f0 {
1396 compatible = "rockchip,rk3188-gate-clk";
1399 <&pclk_peri_pre>, <&pclk_peri_pre>,
1400 <&pclk_peri_pre>, <&dummy>,
1402 <&pclk_peri_pre>, <&pclk_peri_pre>,
1403 <&pclk_peri_pre>, <&dummy>,
1405 <&dummy>, <&pclk_peri_pre>,
1406 <&pclk_peri_pre>, <&pclk_peri_pre>,
1411 clock-output-names =
1412 "g_pclk_uart0", "g_pclk_uart1",
1413 "g_pclk_uart2", "reserved",
1415 "g_pclk_i2c0", "g_pclk_i2c1",
1416 "g_pclk_i2c2", "reserved",
1418 "reserved", "g_pclk_gpio0",
1419 "g_pclk_gpio1", "g_pclk_gpio2",
1421 "reserved", "reserved",
1422 "reserved", "reserved";
1424 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1428 clk_gates9: gate-clk@00f4 {
1429 compatible = "rockchip,rk3188-gate-clk";
1435 <&dummy>, <&hclk_vio_pre>,
1436 <&aclk_vio_pre>, <&dummy>,
1441 <&dummy>, <&hclk_peri_pre>,
1442 <&hclk_peri_pre>, <&aclk_peri_pre>;
1444 clock-output-names =
1445 "reserved", "reserved",
1446 "reserved", "reserved",
1448 "reserved", "g_hclk_lcdc",
1449 "g_aclk_lcdc", "reserved",
1451 "reserved", "reserved",
1452 "reserved", "reserved",
1454 "reserved", "g_hclk_usb_peri",
1455 "g_hclk_pe_arbi", "g_aclk_peri_niu";
1457 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1462 clk_gates10: gate-clk@00f8 {
1463 compatible = "rockchip,rk3188-gate-clk";
1466 <&xin24m>, <&xin24m>,
1467 <&xin24m>, <&dummy>,
1469 <&clk_nandc>, <&clk_sfc>,
1470 <&clk_hevc_core>, <&dummy>,
1472 <&clk_dpll>, <&dummy>,
1478 clock-output-names =
1479 "g_clk_pvtm_core", "g_clk_pvtm_gpu",
1480 "g_pvtm_video", "reserved",
1482 "clk_nandc", "clk_sfc",
1483 "clk_hevc_core", "reserved",
1485 "reserved", "reserved",
1486 "reserved", "reserved",
1488 "reserved", "reserved",
1489 "reserved", "reserved";
1491 rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */