arch/arm/boot/dts/rk3036-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3036.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         rmii_clkin: rmii_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "rmii_clkin";
  45                                 clock-frequency = <0>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb_480m: usb_480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb_480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         dummy: dummy {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "dummy";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         dummy_cpll: dummy_cpll {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "dummy_cpll";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84                 };
  85
  86                 fixed_factor_cons {
  87                         compatible = "rockchip,rk-fixed-factor-cons";
  88
  89                         otgphy0_12m: otgphy0_12m {
  90                                 compatible = "rockchip,rk-fixed-factor-clock";
  91                                 clocks = <&clk_gates1 5>;
  92                                 clock-output-names = "otgphy0_12m";
  93                                 clock-div = <1>;
  94                                 clock-mult = <20>;
  95                                 #clock-cells = <0>;
  96                         };
  97
  98                         hclk_vcodec: hclk_vcodec {
  99                                 compatible = "rockchip,rk-fixed-factor-clock";
 100                                 clocks = <&aclk_vcodec_pre>;
 101                                 clock-output-names = "hclk_vcodec";
 102                                 clock-div = <4>;
 103                                 clock-mult = <1>;
 104                                 #clock-cells = <0>;
 105                         };
 106
 107                 };
 108
 109                 clock_regs {
 110                         compatible = "rockchip,rk-clock-regs";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         reg = <0x0000 0x01f0>;
 114                         ranges;
 115
 116                         /* PLL control regs */
 117                         pll_cons {
 118                                 compatible = "rockchip,rk-pll-cons";
 119                                 #address-cells = <1>;
 120                                 #size-cells = <1>;
 121                                 ranges ;
 122
 123                                 clk_apll: pll-clk@0000 {
 124                                         compatible = "rockchip,rk3188-pll-clk";
 125                                         reg = <0x0000 0x10>;
 126                                         mode-reg = <0x0040 0>;
 127                                         status-reg = <0x0004 10>;
 128                                         clocks = <&xin24m>;
 129                                         clock-output-names = "clk_apll";
 130                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 131                                         #clock-cells = <0>;
 132                                 };
 133
 134                                 clk_dpll: pll-clk@0010 {
 135                                         compatible = "rockchip,rk3188-pll-clk";
 136                                         reg = <0x0010 0x10>;
 137                                         mode-reg = <0x0040 4>;
 138                                         status-reg = <0x0014 10>;
 139                                         clocks = <&xin24m>;
 140                                         clock-output-names = "clk_dpll";
 141                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 142                                         #clock-cells = <0>;
 143                                 };
 144
 145                                 clk_gpll: pll-clk@0030 {
 146                                         compatible = "rockchip,rk3188-pll-clk";
 147                                         reg = <0x0030 0x10>;
 148                                         mode-reg = <0x0040 12>;
 149                                         status-reg = <0x0034 10>;
 150                                         clocks = <&xin24m>;
 151                                         clock-output-names = "clk_gpll";
 152                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 153                                         #clock-cells = <0>;
 154                                         #clock-init-cells = <1>;
 155                                 };
 156
 157                         };
 158
 159                         /* Select control regs */
 160                         clk_sel_cons {
 161                                 compatible = "rockchip,rk-sel-cons";
 162                                 #address-cells = <1>;
 163                                 #size-cells = <1>;
 164                                 ranges;
 165
 166                                 clk_sel_con0: sel-con@0044 {
 167                                         compatible = "rockchip,rk3188-selcon";
 168                                         reg = <0x0044 0x4>;
 169                                         #address-cells = <1>;
 170                                         #size-cells = <1>;
 171
 172                                         clk_core_pre_div: clk_core_pre_div {
 173                                                 compatible = "rockchip,rk3188-div-con";
 174                                                 rockchip,bits = <0 5>;
 175                                                 clocks = <&clk_core_pre>;
 176                                                 clock-output-names = "clk_core_pre";
 177                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 178                                                 #clock-cells = <0>;
 179                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 180                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 181                                                                         CLK_SET_RATE_NO_REPARENT)>;
 182                                         };
 183
 184                                         /* reg[6:5]: reserved */
 185
 186                                         clk_core_pre: clk_core_pre_mux {
 187                                                 compatible = "rockchip,rk3188-mux-con";
 188                                                 rockchip,bits = <7 1>;
 189                                                 clocks = <&clk_apll>, <&clk_gates0 6>;
 190                                                 clock-output-names = "clk_core_pre";
 191                                                 #clock-cells = <0>;
 192                                                 #clock-init-cells = <1>;
 193                                         };
 194
 195                                         aclk_cpu_pre_div: aclk_cpu_pre_div {
 196                                                 compatible = "rockchip,rk3188-div-con";
 197                                                 rockchip,bits = <8 5>;
 198                                                 clocks = <&aclk_cpu_pre>;
 199                                                 clock-output-names = "aclk_cpu_pre";
 200                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 201                                                 #clock-cells = <0>;
 202                                                 rockchip,clkops-idx =
 203                                                         <CLKOPS_RATE_MUX_DIV>;
 204                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 205                                         };
 206
 207                                         /* reg[13]: reserved */
 208
 209                                         aclk_cpu_pre: aclk_cpu_pre_mux {
 210                                                 compatible = "rockchip,rk3188-mux-con";
 211                                                 rockchip,bits = <14 2>;
 212                                                 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
 213                                                 clock-output-names = "aclk_cpu_pre";
 214                                                 #clock-cells = <0>;
 215                                                 #clock-init-cells = <1>;
 216                                         };
 217
 218                                 };
 219
 220                                 clk_sel_con1: sel-con@0048 {
 221                                         compatible = "rockchip,rk3188-selcon";
 222                                         reg = <0x0048 0x4>;
 223                                         #address-cells = <1>;
 224                                         #size-cells = <1>;
 225
 226                                         pclk_dbg_div:  pclk_dbg_div {
 227                                                 compatible = "rockchip,rk3188-div-con";
 228                                                 rockchip,bits = <0 4>;
 229                                                 clocks = <&clk_core_pre>;
 230                                                 clock-output-names = "pclk_dbg";
 231                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 232                                                 #clock-cells = <0>;
 233                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 234                                         };
 235
 236                                         aclk_core_pre: aclk_core_pre_div {
 237                                                 compatible = "rockchip,rk3188-div-con";
 238                                                 rockchip,bits = <4 3>;
 239                                                 clocks = <&clk_core_pre>;
 240                                                 clock-output-names = "aclk_core_pre";
 241                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 242                                                 #clock-cells = <0>;
 243                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 244                                         };
 245
 246                                         /* reg[7]: reserved */
 247
 248                                         hclk_cpu_pre: hclk_cpu_pre_div {
 249                                                 compatible = "rockchip,rk3188-div-con";
 250                                                 rockchip,bits = <8 2>;
 251                                                 clocks = <&aclk_cpu_pre>;
 252                                                 clock-output-names = "hclk_cpu_pre";
 253                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 254                                                 #clock-cells = <0>;
 255                                                 #clock-init-cells = <1>;
 256                                         };
 257
 258                                         /* reg[11:10]: reserved */
 259
 260                                         pclk_cpu_pre: pclk_cpu_pre_div {
 261                                                 compatible = "rockchip,rk3188-div-con";
 262                                                 rockchip,bits = <12 3>;
 263                                                 clocks = <&aclk_cpu_pre>;
 264                                                 clock-output-names = "pclk_cpu_pre";
 265                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 266                                                 #clock-cells = <0>;
 267                                                 #clock-init-cells = <1>;
 268                                         };
 269
 270                                         /* reg[15]: reserved */
 271                                 };
 272
 273                                 clk_sel_con2: sel-con@004c {
 274                                         compatible = "rockchip,rk3188-selcon";
 275                                         reg = <0x004c 0x4>;
 276                                         #address-cells = <1>;
 277                                         #size-cells = <1>;
 278
 279                                         /* reg[3:0]: reserved */
 280
 281                                         clk_timer0: clk_timer0_mux {
 282                                                 compatible = "rockchip,rk3188-mux-con";
 283                                                 rockchip,bits = <4 1>;
 284                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 285                                                 clock-output-names = "clk_timer0";
 286                                                 #clock-cells = <0>;
 287                                                 #clock-init-cells = <1>;
 288                                         };
 289
 290                                         clk_timer1: clk_timer1_mux {
 291                                                 compatible = "rockchip,rk3188-mux-con";
 292                                                 rockchip,bits = <5 1>;
 293                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 294                                                 clock-output-names = "clk_timer1";
 295                                                 #clock-cells = <0>;
 296                                                 #clock-init-cells = <1>;
 297                                         };
 298
 299                                         clk_timer2: clk_timer2_mux {
 300                                                 compatible = "rockchip,rk3188-mux-con";
 301                                                 rockchip,bits = <6 1>;
 302                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 303                                                 clock-output-names = "clk_timer2";
 304                                                 #clock-cells = <0>;
 305                                                 #clock-init-cells = <1>;
 306                                         };
 307
 308                                         clk_timer3: clk_timer3_mux {
 309                                                 compatible = "rockchip,rk3188-mux-con";
 310                                                 rockchip,bits = <7 1>;
 311                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 312                                                 clock-output-names = "clk_timer3";
 313                                                 #clock-cells = <0>;
 314                                                 #clock-init-cells = <1>;
 315                                         };
 316
 317                                         /* reg[15:8]: reserved */
 318                                 };
 319
 320                                 clk_sel_con3: sel-con@0050 {
 321                                         compatible = "rockchip,rk3188-selcon";
 322                                         reg = <0x0050 0x4>;
 323                                         #address-cells = <1>;
 324                                         #size-cells = <1>;
 325
 326                                         clk_i2s_pll_div: clk_i2s_pll_div {
 327                                                 compatible = "rockchip,rk3188-div-con";
 328                                                 rockchip,bits = <0 7>;
 329                                                 clocks = <&clk_i2s_pll>;
 330                                                 clock-output-names = "clk_i2s_pll";
 331                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 332                                                 #clock-cells = <0>;
 333                                                 rockchip,clkops-idx =
 334                                                         <CLKOPS_RATE_MUX_DIV>;
 335                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 336                                         };
 337
 338                                         /* reg[7]: reserved */
 339
 340                                         clk_i2s: clk_i2s_mux {
 341                                                 compatible = "rockchip,rk3188-mux-con";
 342                                                 rockchip,bits = <8 2>;
 343                                                 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
 344                                                 clock-output-names = "clk_i2s";
 345                                                 #clock-cells = <0>;
 346                                                 rockchip,clkops-idx =
 347                                                         <CLKOPS_RATE_RK3288_I2S>;
 348                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 349                                         };
 350
 351                                         /* reg[11:10]: reserved */
 352
 353                                         clk_i2s_out: i2s_outclk_mux {
 354                                                 compatible = "rockchip,rk3188-mux-con";
 355                                                 rockchip,bits = <12 1>;
 356                                                 clocks = <&xin12m>, <&clk_i2s>;
 357                                                 clock-output-names = "i2s_clkout";
 358                                                 #clock-cells = <0>;
 359                                         };
 360
 361                                         /* reg[13]: reserved */
 362
 363                                         clk_i2s_pll: i2s_pll_mux {
 364                                                 compatible = "rockchip,rk3188-mux-con";
 365                                                 rockchip,bits = <14 2>;
 366                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 367                                                 clock-output-names = "clk_i2s_pll";
 368                                                 #clock-cells = <0>;
 369                                                 #clock-init-cells = <1>;
 370                                         };
 371
 372                                 };
 373
 374                                 clk_sel_con5: sel-con@0058 {
 375                                         compatible = "rockchip,rk3188-selcon";
 376                                         reg = <0x0058 0x4>;
 377                                         #address-cells = <1>;
 378                                         #size-cells = <1>;
 379
 380                                         spdif_div: spdif_div {
 381                                                 compatible = "rockchip,rk3188-div-con";
 382                                                 rockchip,bits = <0 7>;
 383                                                 clocks = <&clk_spdif_pll>;
 384                                                 clock-output-names = "clk_spdif_pll";
 385                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 386                                                 #clock-cells = <0>;
 387                                                 rockchip,clkops-idx =
 388                                                         <CLKOPS_RATE_MUX_DIV>;
 389                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 390                                         };
 391
 392                                         /* reg[7]: reserved */
 393
 394                                         clk_spdif: spdif_mux {
 395                                                 compatible = "rockchip,rk3188-mux-con";
 396                                                 rockchip,bits = <8 2>;
 397                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 398                                                 clock-output-names = "clk_spdif";
 399                                                 #clock-cells = <0>;
 400                                                 rockchip,clkops-idx =
 401                                                         <CLKOPS_RATE_RK3288_I2S>;
 402                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 403                                         };
 404
 405                                         clk_spdif_pll: spdif_pll_mux {
 406                                                 compatible = "rockchip,rk3188-mux-con";
 407                                                 rockchip,bits = <10 2>;
 408                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 409                                                 clock-output-names = "clk_spdif_pll";
 410                                                 #clock-cells = <0>;
 411                                                 #clock-init-cells = <1>;
 412                                         };
 413
 414                                         /* reg[15:12]: reserved */
 415                                 };
 416
 417                                 clk_sel_con7: sel-con@0060 {
 418                                         compatible = "rockchip,rk3188-selcon";
 419                                         reg = <0x0060 0x4>;
 420                                         #address-cells = <1>;
 421                                         #size-cells = <1>;
 422
 423                                         i2s_frac: i2s_frac {
 424                                                 compatible = "rockchip,rk3188-frac-con";
 425                                                 clocks = <&clk_i2s_pll>;
 426                                                 clock-output-names = "i2s_frac";
 427                                                 /* numerator    denominator */
 428                                                 rockchip,bits = <0 32>;
 429                                                 rockchip,clkops-idx =
 430                                                         <CLKOPS_RATE_FRAC>;
 431                                                 #clock-cells = <0>;
 432                                         };
 433                                 };
 434
 435                                 clk_sel_con9: sel-con@0068 {
 436                                         compatible = "rockchip,rk3188-selcon";
 437                                         reg = <0x0068 0x4>;
 438                                         #address-cells = <1>;
 439                                         #size-cells = <1>;
 440
 441                                         spdif_frac: spdif_frac {
 442                                                 compatible = "rockchip,rk3188-frac-con";
 443                                                 clocks = <&spdif_div>;
 444                                                 clock-output-names = "spdif_frac";
 445                                                 /* numerator    denominator */
 446                                                 rockchip,bits = <0 32>;
 447                                                 rockchip,clkops-idx =
 448                                                         <CLKOPS_RATE_FRAC>;
 449                                                 #clock-cells = <0>;
 450                                         };
 451                                 };
 452
 453                                 clk_sel_con10: sel-con@006c {
 454                                         compatible = "rockchip,rk3188-selcon";
 455                                         reg = <0x006c 0x4>;
 456                                         #address-cells = <1>;
 457                                         #size-cells = <1>;
 458
 459                                         aclk_peri_pre_div: aclk_peri_pre_div {
 460                                                 compatible = "rockchip,rk3188-div-con";
 461                                                 rockchip,bits = <0 5>;
 462                                                 clocks = <&aclk_peri_pre>;
 463                                                 clock-output-names = "aclk_peri_pre";
 464                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 465                                                 #clock-cells = <0>;
 466                                                 rockchip,clkops-idx =
 467                                                         <CLKOPS_RATE_MUX_DIV>;
 468                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 469                                         };
 470
 471                                         /* reg[7:5]: reserved */
 472
 473                                         hclk_peri_pre: hclk_peri_pre_div {
 474                                                 compatible = "rockchip,rk3188-div-con";
 475                                                 rockchip,bits = <8 2>;
 476                                                 clocks = <&aclk_peri_pre>;
 477                                                 clock-output-names = "hclk_peri_pre";
 478                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 479                                                 rockchip,div-relations =
 480                                                                 <0x0 1
 481                                                                  0x1 2
 482                                                                  0x2 4>;
 483                                                 #clock-cells = <0>;
 484                                                 #clock-init-cells = <1>;
 485                                         };
 486
 487                                         /* reg[11:10]: reserved */
 488
 489                                         pclk_peri_pre: pclk_peri_div {
 490                                                 compatible = "rockchip,rk3188-div-con";
 491                                                 rockchip,bits = <12 2>;
 492                                                 clocks = <&aclk_peri_pre>;
 493                                                 clock-output-names = "pclk_peri_pre";
 494                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 495                                                 rockchip,div-relations =
 496                                                                 <0x0 1
 497                                                                  0x1 2
 498                                                                  0x2 4
 499                                                                  0x3 8>;
 500                                                 #clock-cells = <0>;
 501                                                 #clock-init-cells = <1>;
 502                                         };
 503
 504                                         aclk_peri_pre: aclk_peri_pre_mux {
 505                                                 compatible = "rockchip,rk3188-mux-con";
 506                                                 rockchip,bits = <14 2>;
 507                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 508                                                 clock-output-names = "aclk_peri_pre";
 509                                                 #clock-cells = <0>;
 510                                                 #clock-init-cells = <1>;
 511                                         };
 512                                 };
 513
 514                                 clk_sel_con11: sel-con@0070 {
 515                                         compatible = "rockchip,rk3188-selcon";
 516                                         reg = <0x0070 0x4>;
 517                                         #address-cells = <1>;
 518                                         #size-cells = <1>;
 519
 520                                         clk_sdmmc0_div: clk_sdmmc0_div {
 521                                                 compatible = "rockchip,rk3188-div-con";
 522                                                 rockchip,bits = <0 6>;
 523                                                 clocks = <&clk_sdmmc0>;
 524                                                 clock-output-names = "clk_sdmmc0";
 525                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 526                                                 #clock-cells = <0>;
 527                                                 rockchip,clkops-idx =
 528                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 529                                         };
 530
 531                                         /* reg[7]: reserved */
 532
 533                                         clk_sdio_div: clk_sdio_div {
 534                                                 compatible = "rockchip,rk3188-div-con";
 535                                                 rockchip,bits = <8 7>;
 536                                                 clocks = <&clk_sdio>;
 537                                                 clock-output-names = "clk_sdio";
 538                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 539                                                 #clock-cells = <0>;
 540                                                 rockchip,clkops-idx =
 541                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 542                                         };
 543
 544                                         /* reg[15]: reserved */
 545
 546                                 };
 547
 548                                 clk_sel_con12: sel-con@0074 {
 549                                         compatible = "rockchip,rk3188-selcon";
 550                                         reg = <0x0074 0x4>;
 551                                         #address-cells = <1>;
 552                                         #size-cells = <1>;
 553
 554                                         clk_emmc_div: clk_emmc_div {
 555                                                 compatible = "rockchip,rk3188-div-con";
 556                                                 rockchip,bits = <0 7>;
 557                                                 clocks = <&clk_emmc>;
 558                                                 clock-output-names = "clk_emmc";
 559                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 560                                                 #clock-cells = <0>;
 561                                                 rockchip,clkops-idx =
 562                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 563                                         };
 564
 565                                         /* reg[7]: reserved */
 566
 567                                         clk_sdmmc0: clk_sdmmc0_mux {
 568                                                 compatible = "rockchip,rk3188-mux-con";
 569                                                 rockchip,bits = <8 2>;
 570                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 571                                                 clock-output-names = "clk_sdmmc0";
 572                                                 #clock-cells = <0>;
 573                                         };
 574
 575                                         clk_sdio: clk_sdio_mux {
 576                                                 compatible = "rockchip,rk3188-mux-con";
 577                                                 rockchip,bits = <10 2>;
 578                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 579                                                 clock-output-names = "clk_sdio";
 580                                                 #clock-cells = <0>;
 581                                         };
 582
 583                                         clk_emmc: clk_emmc_mux {
 584                                                 compatible = "rockchip,rk3188-mux-con";
 585                                                 rockchip,bits = <12 2>;
 586                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 587                                                 clock-output-names = "clk_emmc";
 588                                                 #clock-cells = <0>;
 589                                         };
 590
 591                                         /* reg[15:14]: reserved */
 592                                 };
 593
 594                                 clk_sel_con13: sel-con@0078 {
 595                                         compatible = "rockchip,rk3188-selcon";
 596                                         reg = <0x0078 0x4>;
 597                                         #address-cells = <1>;
 598                                         #size-cells = <1>;
 599
 600                                         clk_uart0_div: clk_uart0_div {
 601                                                 compatible = "rockchip,rk3188-div-con";
 602                                                 rockchip,bits = <0 7>;
 603                                                 clocks = <&clk_uart_pll>;
 604                                                 clock-output-names = "clk_uart0_div";
 605                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 606                                                 #clock-cells = <0>;
 607                                         };
 608
 609                                         /* reg[7]: reserved */
 610
 611                                         clk_uart0: clk_uart0_mux {
 612                                                 compatible = "rockchip,rk3188-mux-con";
 613                                                 rockchip,bits = <8 2>;
 614                                                 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
 615                                                 clock-output-names = "clk_uart0";
 616                                                 #clock-cells = <0>;
 617                                                 rockchip,clkops-idx =
 618                                                         <CLKOPS_RATE_RK3288_I2S>;
 619                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 620                                         };
 621
 622                                         clk_uart_pll: clk_uart_pll_mux {
 623                                                 compatible = "rockchip,rk3188-mux-con";
 624                                                 rockchip,bits = <10 2>;
 625                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
 626                                                 clock-output-names = "clk_uart_pll";
 627                                                 #clock-cells = <0>;
 628                                                 #clock-init-cells = <1>;
 629                                         };
 630
 631                                         /* reg[15:12]: reserved */
 632
 633                                 };
 634
 635                                 clk_sel_con14: sel-con@007c {
 636                                         compatible = "rockchip,rk3188-selcon";
 637                                         reg = <0x007c 0x4>;
 638                                         #address-cells = <1>;
 639                                         #size-cells = <1>;
 640
 641                                         clk_uart1_div: clk_uart1_div {
 642                                                 compatible = "rockchip,rk3188-div-con";
 643                                                 rockchip,bits = <0 7>;
 644                                                 clocks = <&clk_uart_pll>;
 645                                                 clock-output-names = "clk_uart1_div";
 646                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 647                                                 #clock-cells = <0>;
 648                                         };
 649
 650                                         /* reg[7]: reserved */
 651
 652                                         clk_uart1: clk_uart1_mux {
 653                                                 compatible = "rockchip,rk3188-mux-con";
 654                                                 rockchip,bits = <8 2>;
 655                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 656                                                 clock-output-names = "clk_uart1";
 657                                                 #clock-cells = <0>;
 658                                                 rockchip,clkops-idx =
 659                                                         <CLKOPS_RATE_RK3288_I2S>;
 660                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 661                                         };
 662
 663                                         /* reg[15:10]: reserved */
 664                                 };
 665
 666                                 clk_sel_con15: sel-con@0080 {
 667                                         compatible = "rockchip,rk3188-selcon";
 668                                         reg = <0x0080 0x4>;
 669                                         #address-cells = <1>;
 670                                         #size-cells = <1>;
 671
 672                                         clk_uart2_div: clk_uart2_div {
 673                                                 compatible = "rockchip,rk3188-div-con";
 674                                                 rockchip,bits = <0 7>;
 675                                                 clocks = <&clk_uart_pll>;
 676                                                 clock-output-names = "clk_uart2_div";
 677                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 678                                                 #clock-cells = <0>;
 679                                         };
 680
 681                                         /* reg[7]: reserved */
 682
 683                                         clk_uart2: clk_uart2_mux {
 684                                                 compatible = "rockchip,rk3188-mux-con";
 685                                                 rockchip,bits = <8 2>;
 686                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 687                                                 clock-output-names = "clk_uart2";
 688                                                 #clock-cells = <0>;
 689                                                 rockchip,clkops-idx =
 690                                                         <CLKOPS_RATE_RK3288_I2S>;
 691                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 692                                         };
 693
 694                                         /* reg[15:10]: reserved */
 695                                 };
 696
 697                                 clk_sel_con16: sel-con@0084 {
 698                                         compatible = "rockchip,rk3188-selcon";
 699                                         reg = <0x0084 0x4>;
 700                                         #address-cells = <1>;
 701                                         #size-cells = <1>;
 702
 703                                         clk_sfc: clk_sfc_mux {
 704                                                 compatible = "rockchip,rk3188-mux-con";
 705                                                 rockchip,bits = <0 2>;
 706                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
 707                                                 clock-output-names = "clk_sfc";
 708                                                 #clock-cells = <0>;
 709                                         };
 710
 711                                         clk_sfc_div: clk_sfc_div {
 712                                                 compatible = "rockchip,rk3188-div-con";
 713                                                 rockchip,bits = <2 5>;
 714                                                 clocks = <&clk_sfc>;
 715                                                 clock-output-names = "clk_sfc";
 716                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 717                                                 #clock-cells = <0>;
 718                                                 rockchip,clkops-idx =
 719                                                         <CLKOPS_RATE_MUX_DIV>;
 720                                         };
 721
 722                                         /* reg[7]: reserved */
 723
 724                                         clk_nandc: clk_nandc_mux {
 725                                                 compatible = "rockchip,rk3188-mux-con";
 726                                                 rockchip,bits = <8 2>;
 727                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 728                                                 clock-output-names = "clk_nandc";
 729                                                 #clock-cells = <0>;
 730                                         };
 731
 732                                         clk_nandc_div: clk_nandc_div {
 733                                                 compatible = "rockchip,rk3188-div-con";
 734                                                 rockchip,bits = <10 5>;
 735                                                 clocks = <&clk_nandc>;
 736                                                 clock-output-names = "clk_nandc";
 737                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 738                                                 #clock-cells = <0>;
 739                                                 rockchip,clkops-idx =
 740                                                         <CLKOPS_RATE_MUX_DIV>;
 741                                         };
 742
 743                                         /* reg[31:15]: reserved */
 744                                 };
 745
 746                                 clk_sel_con17: sel-con@0088 {
 747                                         compatible = "rockchip,rk3188-selcon";
 748                                         reg = <0x0088 0x4>;
 749                                         #address-cells = <1>;
 750                                         #size-cells = <1>;
 751
 752                                         uart0_frac: uart0_frac {
 753                                                 compatible = "rockchip,rk3188-frac-con";
 754                                                 clocks = <&clk_uart0_div>;
 755                                                 clock-output-names = "uart0_frac";
 756                                                 /* numerator    denominator */
 757                                                 rockchip,bits = <0 32>;
 758                                                 rockchip,clkops-idx =
 759                                                         <CLKOPS_RATE_FRAC>;
 760                                                 #clock-cells = <0>;
 761                                         };
 762                                 };
 763
 764                                 clk_sel_con18: sel-con@008c {
 765                                         compatible = "rockchip,rk3188-selcon";
 766                                         reg = <0x008c 0x4>;
 767                                         #address-cells = <1>;
 768                                         #size-cells = <1>;
 769
 770                                         uart1_frac: uart1_frac {
 771                                                 compatible = "rockchip,rk3188-frac-con";
 772                                                 clocks = <&clk_uart1_div>;
 773                                                 clock-output-names = "uart1_frac";
 774                                                 /* numerator    denominator */
 775                                                 rockchip,bits = <0 32>;
 776                                                 rockchip,clkops-idx =
 777                                                         <CLKOPS_RATE_FRAC>;
 778                                                 #clock-cells = <0>;
 779                                         };
 780                                 };
 781
 782                                 clk_sel_con19: sel-con@0090 {
 783                                         compatible = "rockchip,rk3188-selcon";
 784                                         reg = <0x0090 0x4>;
 785                                         #address-cells = <1>;
 786                                         #size-cells = <1>;
 787
 788                                         uart2_frac: uart2_frac {
 789                                                 compatible = "rockchip,rk3188-frac-con";
 790                                                 clocks = <&clk_uart2_div>;
 791                                                 clock-output-names = "uart2_frac";
 792                                                 /* numerator    denominator */
 793                                                 rockchip,bits = <0 32>;
 794                                                 rockchip,clkops-idx =
 795                                                         <CLKOPS_RATE_FRAC>;
 796                                                 #clock-cells = <0>;
 797                                         };
 798
 799                                 };
 800
 801                                 clk_sel_con20: sel-con@0094 {
 802                                         compatible = "rockchip,rk3188-selcon";
 803                                         reg = <0x0094 0x4>;
 804                                         #address-cells = <1>;
 805                                         #size-cells = <1>;
 806
 807                                         clk_hevc_core: clk_hevc_core_mux {
 808                                                 compatible = "rockchip,rk3188-mux-con";
 809                                                 rockchip,bits = <0 2>;
 810                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 811                                                 clock-output-names = "clk_hevc_core";
 812                                                 #clock-cells = <0>;
 813                                                 #clock-init-cells = <1>;
 814                                         };
 815
 816                                         clk_hevc_core_div: clk_hevc_core_div {
 817                                                 compatible = "rockchip,rk3188-div-con";
 818                                                 rockchip,bits = <2 5>;
 819                                                 clocks = <&clk_hevc_core>;
 820                                                 clock-output-names = "clk_hevc_core";
 821                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 822                                                 #clock-cells = <0>;
 823                                                 rockchip,clkops-idx =
 824                                                         <CLKOPS_RATE_MUX_DIV>;
 825                                         };
 826
 827                                         /* reg[31:7]: reserved */
 828
 829                                 };
 830
 831                                 clk_sel_con21: sel-con@0098 {
 832                                         compatible = "rockchip,rk3188-selcon";
 833                                         reg = <0x0098 0x4>;
 834                                         #address-cells = <1>;
 835                                         #size-cells = <1>;
 836
 837                                         clk_mac_pll: clk_mac_pll_mux {
 838                                                 compatible = "rockchip,rk3188-mux-con";
 839                                                 rockchip,bits = <0 2>;
 840                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 841                                                 clock-output-names = "clk_mac_pll";
 842                                                 #clock-cells = <0>;
 843                                                 #clock-init-cells = <1>;
 844                                         };
 845
 846                                         /* reg[2]: reserved */
 847
 848                                         clk_mac_ref: clk_mac_ref_mux {
 849                                                 compatible = "rockchip,rk3188-mux-con";
 850                                                 rockchip,bits = <3 1>;
 851                                                 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
 852                                                 clock-output-names = "clk_mac_ref";
 853                                                 #clock-cells = <0>;
 854                                                 rockchip,clkops-idx =
 855                                                         <CLKOPS_RATE_MAC_REF>;
 856                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 857                                                 #clock-init-cells = <1>;
 858                                         };
 859
 860                                         clk_mac_pll_div: clk_mac_pll_div {
 861                                                 compatible = "rockchip,rk3188-div-con";
 862                                                 rockchip,bits = <4 5>;
 863                                                 clocks = <&clk_mac_pll>;
 864                                                 clock-output-names = "clk_mac_pll";
 865                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 866                                                 #clock-cells = <0>;
 867                                                 rockchip,clkops-idx =
 868                                                         <CLKOPS_RATE_MUX_DIV>;
 869                                         };
 870
 871                                         clk_mac_ref_div: clk_mac_ref_div {
 872                                                 compatible = "rockchip,rk3188-div-con";
 873                                                 rockchip,bits = <9 5>;
 874                                                 clocks = <&clk_mac_ref>;
 875                                                 clock-output-names = "clk_mac";
 876                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 877                                                 #clock-cells = <0>;
 878                                                 #clock-init-cells = <1>;
 879                                         };
 880
 881                                         /* reg[15:14]: reserved */
 882                                 };
 883
 884                                 clk_sel_con25: sel-con@00a8 {
 885                                         compatible = "rockchip,rk3188-selcon";
 886                                         reg = <0x00a8 0x4>;
 887                                         #address-cells = <1>;
 888                                         #size-cells = <1>;
 889
 890                                         clk_spi0_div: clk_spi0_div {
 891                                                 compatible = "rockchip,rk3188-div-con";
 892                                                 rockchip,bits = <0 7>;
 893                                                 clocks = <&clk_spi0>;
 894                                                 clock-output-names = "clk_spi0";
 895                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 896                                                 #clock-cells = <0>;
 897                                                 rockchip,clkops-idx =
 898                                                         <CLKOPS_RATE_MUX_DIV>;
 899                                         };
 900
 901                                         /* reg[7]: reserved */
 902
 903                                         clk_spi0: clk_spi0_mux {
 904                                                 compatible = "rockchip,rk3188-mux-con";
 905                                                 rockchip,bits = <8 2>;
 906                                                 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
 907                                                 clock-output-names = "clk_spi0";
 908                                                 #clock-cells = <0>;
 909                                         };
 910
 911                                         /* reg[15:10]: reserved */
 912
 913                                 };
 914
 915                                 clk_sel_con26: sel-con@00ac {
 916                                         compatible = "rockchip,rk3188-selcon";
 917                                         reg = <0x00ac 0x4>;
 918                                         #address-cells = <1>;
 919                                         #size-cells = <1>;
 920
 921                                         ddr_div: ddr_div {
 922                                                 compatible = "rockchip,rk3188-div-con";
 923                                                 rockchip,bits = <0 2>;
 924                                                 clocks = <&clk_ddr>;
 925                                                 clock-output-names = "clk_ddr";
 926                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 927                                                 rockchip,div-relations =
 928                                                                 <0x0 1
 929                                                                  0x1 2
 930                                                                  0x3 4>;
 931                                                 #clock-cells = <0>;
 932                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 933                                                                         CLK_SET_RATE_NO_REPARENT)>;
 934                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
 935                                         };
 936
 937                                         /* reg[7:1]: reserved */
 938
 939                                         clk_ddr: ddr_clk_pll_mux {
 940                                                 compatible = "rockchip,rk3188-mux-con";
 941                                                 rockchip,bits = <8 1>;
 942                                                 clocks = <&clk_gates0 2>, <&clk_gates0 8>;
 943                                                 clock-output-names = "clk_ddr";
 944                                                 #clock-cells = <0>;
 945                                         };
 946
 947                                         /* reg[15:9]: reserved */
 948                                 };
 949
 950                                 clk_sel_con28: sel-con@00b4 {
 951                                         compatible = "rockchip,rk3188-selcon";
 952                                         reg = <0x00b4 0x4>;
 953                                         #address-cells = <1>;
 954                                         #size-cells = <1>;
 955
 956                                         dclk_lcdc1: dclk_lcdc1_mux {
 957                                                 compatible = "rockchip,rk3188-mux-con";
 958                                                 rockchip,bits = <0 2>;
 959                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 960                                                 clock-output-names = "dclk_lcdc1";
 961                                                 #clock-cells = <0>;
 962                                                 #clock-init-cells = <1>;
 963                                         };
 964
 965                                         /* reg[7:2]: reserved */
 966
 967                                         dclk_lcdc1_div: dclk_lcdc1_div {
 968                                                 compatible = "rockchip,rk3188-div-con";
 969                                                 rockchip,bits = <8 8>;
 970                                                 clocks = <&dclk_lcdc1>;
 971                                                 clock-output-names = "dclk_lcdc1";
 972                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 973                                                 #clock-cells = <0>;
 974                                                 rockchip,clkops-idx =
 975                                                         <CLKOPS_RATE_MUX_DIV>;
 976                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 977                                         };
 978                                 };
 979
 980                                 clk_sel_con30: sel-con@00bc {
 981                                         compatible = "rockchip,rk3188-selcon";
 982                                         reg = <0x00bc 0x4>;
 983                                         #address-cells = <1>;
 984                                         #size-cells = <1>;
 985
 986                                         clk_testout_div: clk_testout_div {
 987                                                 compatible = "rockchip,rk3188-div-con";
 988                                                 rockchip,bits = <0 5>;
 989                                                 clocks = <&dummy>;
 990                                                 clock-output-names = "clk_testout";
 991                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 992                                                 #clock-cells = <0>;
 993                                                 #clock-init-cells = <1>;
 994                                         };
 995
 996                                         /* reg[7:5]: reserved */
 997
 998                                         hclk_vio_pre_div: hclk_vio_pre_div {
 999                                                 compatible = "rockchip,rk3188-div-con";
1000                                                 rockchip,bits = <8 5>;
1001                                                 clocks = <&hclk_vio_pre>;
1002                                                 clock-output-names = "hclk_vio_pre";
1003                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1004                                                 #clock-cells = <0>;
1005                                                 rockchip,clkops-idx =
1006                                                         <CLKOPS_RATE_MUX_DIV>;
1007                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1008                                         };
1009
1010                                         /* reg[13]: reserved */
1011
1012                                         hclk_vio_pre: hclk_vio_pre_mux {
1013                                                 compatible = "rockchip,rk3188-mux-con";
1014                                                 rockchip,bits = <14 2>;
1015                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1016                                                 clock-output-names = "hclk_vio_pre";
1017                                                 #clock-cells = <0>;
1018                                                 #clock-init-cells = <1>;
1019                                         };
1020
1021                                 };
1022
1023                                 clk_sel_con31: sel-con@00c0 {
1024                                         compatible = "rockchip,rk3188-selcon";
1025                                         reg = <0x00c0 0x4>;
1026                                         #address-cells = <1>;
1027                                         #size-cells = <1>;
1028
1029                                         clk_hdmi: clk_hdmi_mux {
1030                                                 compatible = "rockchip,rk3188-mux-con";
1031                                                 rockchip,bits = <0 1>;
1032                                                 clocks = <&dclk_lcdc1_div>, <&dummy>;
1033                                                 clock-output-names = "clk_hdmi";
1034                                                 #clock-cells = <0>;
1035                                         };
1036
1037                                         /* reg[7:1]: reserved */
1038
1039                                         aclk_vio_pre_div: aclk_vio_pre_div {
1040                                                 compatible = "rockchip,rk3188-div-con";
1041                                                 rockchip,bits = <8 5>;
1042                                                 clocks = <&aclk_vio_pre>;
1043                                                 clock-output-names = "aclk_vio_pre";
1044                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1045                                                 #clock-cells = <0>;
1046                                                 rockchip,clkops-idx =
1047                                                         <CLKOPS_RATE_MUX_DIV>;
1048                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1049                                         };
1050
1051                                         /* reg[13]: reserved */
1052
1053                                         aclk_vio_pre: aclk_vio_pre_mux {
1054                                                 compatible = "rockchip,rk3188-mux-con";
1055                                                 rockchip,bits = <14 2>;
1056                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1057                                                 clock-output-names = "aclk_vio_pre";
1058                                                 #clock-cells = <0>;
1059                                                 #clock-init-cells = <1>;
1060                                         };
1061
1062                                 };
1063
1064                                 clk_sel_con32: sel-con@00c4 {
1065                                         compatible = "rockchip,rk3188-selcon";
1066                                         reg = <0x00c4 0x4>;
1067                                         #address-cells = <1>;
1068                                         #size-cells = <1>;
1069
1070                                         /* reg[7:0]: reserved */
1071
1072                                         aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1073                                                 compatible = "rockchip,rk3188-div-con";
1074                                                 rockchip,bits = <8 5>;
1075                                                 clocks = <&aclk_vcodec_pre>;
1076                                                 clock-output-names = "aclk_vcodec_pre";
1077                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1078                                                 #clock-cells = <0>;
1079                                                 rockchip,clkops-idx =
1080                                                         <CLKOPS_RATE_MUX_DIV>;
1081                                         };
1082
1083                                         /* reg[13]: reserved */
1084
1085                                         aclk_vcodec_pre: aclk_vcodec_pre_mux {
1086                                                 compatible = "rockchip,rk3188-mux-con";
1087                                                 rockchip,bits = <14 2>;
1088                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1089                                                 clock-output-names = "aclk_vcodec_pre";
1090                                                 #clock-cells = <0>;
1091                                                 #clock-init-cells = <1>;
1092                                         };
1093                                 };
1094
1095                                 clk_sel_con34: sel-con@00cc {
1096                                         compatible = "rockchip,rk3188-selcon";
1097                                         reg = <0x00cc 0x4>;
1098                                         #address-cells = <1>;
1099                                         #size-cells = <1>;
1100
1101                                         clk_gpu_pre_div: clk_gpu_pre_div {
1102                                                 compatible = "rockchip,rk3188-div-con";
1103                                                 rockchip,bits = <0 5>;
1104                                                 clocks = <&clk_gpu_pre>;
1105                                                 clock-output-names = "clk_gpu_pre";
1106                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1107                                                 #clock-cells = <0>;
1108                                                 rockchip,clkops-idx =
1109                                                         <CLKOPS_RATE_MUX_DIV>;
1110                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1111                                         };
1112
1113                                         /* reg[7:5]: reserved */
1114
1115                                         clk_gpu_pre: clk_gpu_pre_mux {
1116                                                 compatible = "rockchip,rk3188-mux-con";
1117                                                 rockchip,bits = <8 2>;
1118                                                 clocks = <&dummy>, <&clk_dpll>, <&clk_gpll>;
1119                                                 clock-output-names = "clk_gpu_pre";
1120                                                 #clock-cells = <0>;
1121                                                 #clock-init-cells = <1>;
1122                                         };
1123
1124                                         /* reg[15:10]: reserved */
1125
1126                                 };
1127
1128                         };
1129
1130
1131                         /* Gate control regs */
1132                         clk_gate_cons {
1133                                 compatible = "rockchip,rk-gate-cons";
1134                                 #address-cells = <1>;
1135                                 #size-cells = <1>;
1136                                 ranges ;
1137
1138                                 clk_gates0: gate-clk@00d0{
1139                                         compatible = "rockchip,rk3188-gate-clk";
1140                                         reg = <0x00d0 0x4>;
1141                                         clocks =
1142                                                 <&clk_core_pre>,                <&clk_gpll>,
1143                                                 <&clk_dpll>,    <&aclk_cpu_pre>,
1144
1145                                                 <&aclk_cpu_pre>,        <&aclk_cpu_pre>,
1146                                                 <&clk_gpll>,            <&clk_core_pre>,
1147
1148                                                 <&clk_gpll>,    <&clk_i2s_pll>,
1149                                                 <&i2s_frac>,    <&hclk_vio_pre>,
1150
1151                                                 <&dummy>,               <&clk_i2s_out>,
1152                                                 <&clk_i2s>,             <&dummy>;
1153
1154                                         clock-output-names =
1155                                                 "pclk_dbg",                     "reserved",      /* do not use bit1 = "cpu_gpll" */
1156                                                 "reserved",             "aclk_cpu_pre",
1157
1158                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1159                                                 "reserved",             "aclk_core_pre",
1160
1161                                                 "reserved",             "clk_i2s_pll",
1162                                                 "i2s_frac",             "hclk_vio_pre",
1163
1164                                                 "clk_cryto",            "clk_i2s_out",
1165                                                 "clk_i2s",              "clk_testout";
1166                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1167
1168                                         #clock-cells = <1>;
1169                                 };
1170
1171                                 clk_gates1: gate-clk@00d4{
1172                                         compatible = "rockchip,rk3188-gate-clk";
1173                                         reg = <0x00d4 0x4>;
1174                                         clocks =
1175                                                 <&clk_timer0>,          <&clk_timer1>,
1176                                                 <&dummy>,               <&jtag_tck>,
1177
1178                                                 <&aclk_vio_pre>,                <&xin12m>,
1179                                                 <&dummy>,               <&dummy>,
1180
1181                                                 <&clk_uart0_div>,               <&uart0_frac>,
1182                                                 <&clk_uart1_div>,               <&uart1_frac>,
1183
1184                                                 <&clk_uart2_div>,               <&uart2_frac>,
1185                                                 <&dummy>,               <&dummy>;
1186
1187                                         clock-output-names =
1188                                                 "clk_timer0",           "clk_timer1",
1189                                                 "reserved",             "clk_jatg",
1190
1191                                                 "aclk_vio_pre",         "clk_otgphy0",
1192                                                 "clk_otgphy1",                  "reserved",
1193
1194                                                 "clk_uart0_div",        "uart0_frac",
1195                                                 "clk_uart1_div",        "uart1_frac",
1196
1197                                                 "clk_uart2_div",        "uart2_frac",
1198                                                 "reserved",     "reserved";
1199
1200                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
1201                                         #clock-cells = <1>;
1202                                 };
1203
1204                                 clk_gates2: gate-clk@00d8 {
1205                                         compatible = "rockchip,rk3188-gate-clk";
1206                                         reg = <0x00d8 0x4>;
1207                                         clocks =
1208                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1209                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1210
1211                                                 <&clk_timer2>,          <&clk_timer3>,
1212                                                 <&clk_mac_ref>,         <&dummy>,
1213
1214                                                 <&dummy>,               <&clk_spi0>,
1215                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1216
1217                                                 <&spdif_frac>,          <&clk_sdio>,
1218                                                 <&clk_emmc>,            <&dummy>;
1219
1220                                         clock-output-names =
1221                                                 "aclk_peri",            "aclk_peri_pre",
1222                                                 "hclk_peri_pre",                "pclk_peri_pre",
1223
1224                                                 "clk_timer2",           "clk_timer3",
1225                                                 "clk_mac",              "reserved",
1226
1227                                                 "reserved",             "clk_spi0",
1228                                                 "clk_spdif_pll",                "clk_sdmmc0",
1229
1230                                                 "spdif_frac",           "clk_sdio",
1231                                                 "clk_emmc",             "reserved";
1232                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
1233
1234                                         #clock-cells = <1>;
1235                                 };
1236
1237                                 clk_gates3: gate-clk@00dc {
1238                                         compatible = "rockchip,rk3188-gate-clk";
1239                                         reg = <0x00dc 0x4>;
1240                                         clocks =
1241                                                 <&dummy>,               <&dummy>,
1242                                                 <&dclk_lcdc1>,          <&dummy>,
1243
1244                                                 <&dummy>,                       <&dummy>,
1245                                                 <&dummy>,               <&dummy>,
1246
1247                                                 <&pclk_cpu_pre>,                <&dummy>,
1248                                                 <&dummy>,               <&aclk_vcodec_pre>,
1249
1250                                                 <&aclk_vcodec_pre>,             <&clk_gpu_pre>,
1251                                                 <&hclk_peri_pre>,               <&dummy>;
1252
1253                                         clock-output-names =
1254                                                 "reserved",             "reserved",
1255                                                 "dclk_lcdc1",           "reserved",
1256
1257                                                 "reserved",             "reserved",
1258                                                 "reserved",             "reserved",
1259
1260                                                 "g_pclk_hdmi",          "reserved",
1261                                                 "reserved",             "aclk_vcodec_pre",
1262
1263                                                 "hclk_vcodec",          "clk_gpu_pre",
1264                                                 "g_hclk_sfc",           "reserved";
1265                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1266
1267                                         #clock-cells = <1>;
1268                                 };
1269
1270                                 clk_gates4: gate-clk@00e0{
1271                                         compatible = "rockchip,rk3188-gate-clk";
1272                                         reg = <0x00e0 0x4>;
1273                                         clocks =
1274                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1275                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1276
1277                                                 <&dummy>,               <&dummy>,
1278                                                 <&dummy>,               <&dummy>,
1279
1280                                                 <&dummy>,               <&dummy>,
1281                                                 <&aclk_cpu_pre>,                <&dummy>,
1282
1283                                                 <&aclk_cpu_pre>,                <&dummy>,
1284                                                 <&dummy>,               <&dummy>;
1285
1286                                         clock-output-names =
1287                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1288                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1289
1290                                                 "reserved",             "reserved",
1291                                                 "reserved",             "reserved",
1292
1293                                                 "reserved",             "reserved",
1294                                                 "g_aclk_strc_sys",              "reserved",
1295
1296                                                 /* Not use these ddr gates */
1297                                                 "g_aclk_intmem",                "reserved",
1298                                                 "reserved",             "reserved";
1299
1300                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1301                                         #clock-cells = <1>;
1302                                 };
1303
1304                                 clk_gates5: gate-clk@00e4 {
1305                                         compatible = "rockchip,rk3188-gate-clk";
1306                                         reg = <0x00e4 0x4>;
1307                                         clocks =
1308                                                 <&dummy>,               <&aclk_peri_pre>,
1309                                                 <&pclk_peri_pre>,               <&dummy>,
1310
1311                                                 <&pclk_cpu_pre>,                <&dummy>,
1312                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1313
1314                                                 <&dummy>,               <&hclk_peri_pre>,
1315                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1316
1317                                                 <&dummy>,               <&hclk_peri_pre>,
1318                                                 <&pclk_cpu_pre>,                <&dummy>;
1319
1320                                         clock-output-names =
1321                                                 "reserved",             "g_aclk_dmac2",
1322                                                 "g_pclk_efuse", "reserved",
1323
1324                                                 "g_pclk_grf",           "reserved",
1325                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1326
1327                                                 "reserved",             "g_hclk_nandc",
1328                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1329
1330                                                 "reserved",             "g_hclk_otg0",
1331                                                 "g_pclk_acodec",                "reserved";
1332
1333                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1334
1335                                         #clock-cells = <1>;
1336                                 };
1337
1338                                 clk_gates6: gate-clk@00e8 {
1339                                         compatible = "rockchip,rk3188-gate-clk";
1340                                         reg = <0x00e8 0x4>;
1341                                         clocks =
1342                                                 <&dummy>,               <&dummy>,
1343                                                 <&dummy>,               <&dummy>,
1344
1345                                                 <&dummy>,               <&dummy>,
1346                                                 <&dummy>,               <&dummy>,
1347
1348                                                 <&dummy>,               <&dummy>,
1349                                                 <&dummy>,                       <&dummy>,
1350
1351                                                 <&hclk_vio_pre>,                <&aclk_vio_pre>,
1352                                                 <&dummy>,               <&dummy>;
1353
1354                                         clock-output-names =
1355                                                 "reserved",             "reserved",
1356                                                 "reserved",             "reserved",
1357
1358                                                 "reserved",             "reserved",
1359                                                 "reserved",             "reserved",
1360
1361                                                 "reserved",             "reserved",
1362                                                 "reserved",             "reserved",
1363
1364                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1365                                                 "reserved",             "reserved";
1366
1367                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1368
1369                                         #clock-cells = <1>;
1370                                 };
1371
1372                                 clk_gates7: gate-clk@00ec {
1373                                         compatible = "rockchip,rk3188-gate-clk";
1374                                         reg = <0x00ec 0x4>;
1375                                         clocks =
1376                                                 <&hclk_peri_pre>,               <&dummy>,
1377                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1378
1379                                                 <&dummy>,               <&dummy>,
1380                                                 <&dummy>,               <&pclk_peri_pre>,
1381
1382                                                 <&dummy>,               <&dummy>,
1383                                                 <&pclk_peri_pre>,               <&dummy>,
1384
1385                                                 <&pclk_peri_pre>,               <&dummy>,
1386                                                 <&dummy>,               <&pclk_peri_pre>;
1387
1388                                         clock-output-names =
1389                                                 "g_hclk_emmc",          "reserved",
1390                                                 "g_hclk_i2s",           "g_hclk_otg1",
1391
1392                                                 "reserved",             "reserved",
1393                                                 "reserved",             "g_pclk_timer0",
1394
1395                                                 "reserved",             "reserved",
1396                                                 "g_pclk_pwm",           "reserved",
1397
1398                                                 "g_pclk_spi",           "reserved",
1399                                                 "reserved",             "g_pclk_wdt";
1400
1401                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1402
1403                                         #clock-cells = <1>;
1404                                 };
1405
1406                                 clk_gates8: gate-clk@00f0 {
1407                                         compatible = "rockchip,rk3188-gate-clk";
1408                                         reg = <0x00f0 0x4>;
1409                                         clocks =
1410                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1411                                                 <&pclk_peri_pre>,               <&dummy>,
1412
1413                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1414                                                 <&pclk_peri_pre>,               <&dummy>,
1415
1416                                                 <&dummy>,               <&pclk_peri_pre>,
1417                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1418
1419                                                 <&dummy>,               <&dummy>,
1420                                                 <&dummy>,               <&dummy>;
1421
1422                                         clock-output-names =
1423                                                 "g_pclk_uart0",         "g_pclk_uart1",
1424                                                 "g_pclk_uart2",         "reserved",
1425
1426                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1427                                                 "g_pclk_i2c2",          "reserved",
1428
1429                                                 "reserved",             "g_pclk_gpio0",
1430                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1431
1432                                                 "reserved",             "reserved",
1433                                                 "reserved",             "reserved";
1434
1435                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1436                                         #clock-cells = <1>;
1437                                 };
1438
1439                                 clk_gates9: gate-clk@00f4 {
1440                                         compatible = "rockchip,rk3188-gate-clk";
1441                                         reg = <0x00f4 0x4>;
1442                                         clocks =
1443                                                 <&dummy>,               <&dummy>,
1444                                                 <&dummy>,               <&dummy>,
1445
1446                                                 <&dummy>,               <&hclk_vio_pre>,
1447                                                 <&aclk_vio_pre>,                <&dummy>,
1448
1449                                                 <&dummy>,               <&dummy>,
1450                                                 <&dummy>,               <&dummy>,
1451
1452                                                 <&dummy>,               <&hclk_peri_pre>,
1453                                                 <&hclk_peri_pre>,               <&aclk_peri_pre>;
1454
1455                                         clock-output-names =
1456                                                 "reserved",             "reserved",
1457                                                 "reserved",             "reserved",
1458
1459                                                 "reserved",             "g_hclk_lcdc",
1460                                                 "g_aclk_lcdc",          "reserved",
1461
1462                                                 "reserved",             "reserved",
1463                                                 "reserved",             "reserved",
1464
1465                                                 "reserved",             "g_hclk_usb_peri",
1466                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1467
1468                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1469
1470                                         #clock-cells = <1>;
1471                                 };
1472
1473                                 clk_gates10: gate-clk@00f8 {
1474                                         compatible = "rockchip,rk3188-gate-clk";
1475                                         reg = <0x00f8 0x4>;
1476                                         clocks =
1477                                                 <&xin24m>,              <&xin24m>,
1478                                                 <&xin24m>,              <&dummy>,
1479
1480                                                 <&clk_nandc>,           <&clk_sfc>,
1481                                                 <&clk_hevc_core>,               <&dummy>,
1482
1483                                                 <&clk_dpll>,            <&dummy>,
1484                                                 <&dummy>,               <&dummy>,
1485
1486                                                 <&dummy>,               <&dummy>,
1487                                                 <&dummy>,               <&dummy>;
1488
1489                                         clock-output-names =
1490                                                 "g_clk_pvtm_core",              "g_clk_pvtm_gpu",
1491                                                 "g_pvtm_video",         "reserved",
1492
1493                                                 "clk_nandc",            "clk_sfc",
1494                                                 "clk_hevc_core",                "reserved",
1495
1496                                                 "reserved",             "reserved",
1497                                                 "reserved",             "reserved",
1498
1499                                                 "reserved",             "reserved",
1500                                                 "reserved",             "reserved";
1501
1502                                         rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */
1503
1504                                         #clock-cells = <1>;
1505                                 };
1506
1507                         };
1508                 };
1509         };
1510 };