2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3036.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x1f0>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
42 rmii_clkin: rmii_clkin {
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "rmii_clkin";
45 clock-frequency = <0>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "usb_480m";
52 clock-frequency = <480000000>;
56 i2s_clkin: i2s_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "i2s_clkin";
59 clock-frequency = <0>;
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "dummy";
66 clock-frequency = <0>;
70 dummy_cpll: dummy_cpll {
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "dummy_cpll";
73 clock-frequency = <0>;
80 compatible = "rockchip,rk-fixed-factor-cons";
82 otgphy0_12m: otgphy0_12m {
83 compatible = "rockchip,rk-fixed-factor-clock";
84 clocks = <&clk_gates1 5>;
85 clock-output-names = "otgphy0_12m";
93 compatible = "rockchip,rk-clock-regs";
96 reg = <0x0000 0x01f0>;
99 /* PLL control regs */
101 compatible = "rockchip,rk-pll-cons";
102 #address-cells = <1>;
106 clk_apll: pll-clk@0000 {
107 compatible = "rockchip,rk3188-pll-clk";
109 mode-reg = <0x0040 0>;
110 status-reg = <0x0004 10>;
112 clock-output-names = "clk_apll";
113 rockchip,pll-type = <CLK_PLL_3036_APLL>;
117 clk_dpll: pll-clk@0010 {
118 compatible = "rockchip,rk3188-pll-clk";
120 mode-reg = <0x0040 4>;
121 status-reg = <0x0014 10>;
123 clock-output-names = "clk_dpll";
124 rockchip,pll-type = <CLK_PLL_3188PLUS>;
128 clk_gpll: pll-clk@0030 {
129 compatible = "rockchip,rk3188-pll-clk";
131 mode-reg = <0x0040 12>;
132 status-reg = <0x0034 10>;
134 clock-output-names = "clk_gpll";
135 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
137 #clock-init-cells = <1>;
142 /* Select control regs */
144 compatible = "rockchip,rk-sel-cons";
145 #address-cells = <1>;
149 clk_sel_con0: sel-con@0044 {
150 compatible = "rockchip,rk3188-selcon";
152 #address-cells = <1>;
155 clk_core_pre_div: clk_core_pre_div {
156 compatible = "rockchip,rk3188-div-con";
157 rockchip,bits = <0 5>;
158 clocks = <&clk_core_pre>;
159 clock-output-names = "clk_core_pre";
160 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
162 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
163 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
164 CLK_SET_RATE_NO_REPARENT)>;
167 /* reg[6:5]: reserved */
169 clk_core_pre: clk_core_pre_mux {
170 compatible = "rockchip,rk3188-mux-con";
171 rockchip,bits = <7 1>;
172 clocks = <&clk_apll>, <&clk_gates0 6>;
173 clock-output-names = "clk_core_pre";
175 #clock-init-cells = <1>;
178 aclk_cpu_pre_div: aclk_cpu_pre_div {
179 compatible = "rockchip,rk3188-div-con";
180 rockchip,bits = <8 5>;
181 clocks = <&aclk_cpu_pre>;
182 clock-output-names = "aclk_cpu_pre";
183 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
185 rockchip,clkops-idx =
186 <CLKOPS_RATE_MUX_DIV>;
187 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
190 /* reg[13]: reserved */
192 aclk_cpu_pre: aclk_cpu_pre_mux {
193 compatible = "rockchip,rk3188-mux-con";
194 rockchip,bits = <14 2>;
195 clocks = <&clk_apll>, <&clk_gates10 8>,<&clk_gates0 1>;
196 clock-output-names = "aclk_cpu_pre";
198 #clock-init-cells = <1>;
203 clk_sel_con1: sel-con@0048 {
204 compatible = "rockchip,rk3188-selcon";
206 #address-cells = <1>;
209 pclk_dbg_div: pclk_dbg_div {
210 compatible = "rockchip,rk3188-div-con";
211 rockchip,bits = <0 4>;
212 clocks = <&clk_core_pre>;
213 clock-output-names = "pclk_dbg";
214 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
216 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
219 aclk_core_pre: aclk_core_pre_div {
220 compatible = "rockchip,rk3188-div-con";
221 rockchip,bits = <4 3>;
222 clocks = <&clk_core_pre>;
223 clock-output-names = "aclk_core_pre";
224 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
226 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
229 /* reg[7]: reserved */
231 hclk_cpu_pre: hclk_cpu_pre_div {
232 compatible = "rockchip,rk3188-div-con";
233 rockchip,bits = <8 2>;
234 clocks = <&aclk_cpu_pre>;
235 clock-output-names = "hclk_cpu_pre";
236 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
238 #clock-init-cells = <1>;
241 /* reg[11:10]: reserved */
243 pclk_cpu_pre: pclk_cpu_pre_div {
244 compatible = "rockchip,rk3188-div-con";
245 rockchip,bits = <12 3>;
246 clocks = <&aclk_cpu_pre>;
247 clock-output-names = "pclk_cpu_pre";
248 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
250 #clock-init-cells = <1>;
253 /* reg[15]: reserved */
256 clk_sel_con2: sel-con@004c {
257 compatible = "rockchip,rk3188-selcon";
259 #address-cells = <1>;
262 /* reg[3:0]: reserved */
264 clk_timer0: clk_timer0_mux {
265 compatible = "rockchip,rk3188-mux-con";
266 rockchip,bits = <4 1>;
267 clocks = <&xin24m>, <&aclk_peri_pre>;
268 clock-output-names = "clk_timer0";
270 #clock-init-cells = <1>;
273 clk_timer1: clk_timer1_mux {
274 compatible = "rockchip,rk3188-mux-con";
275 rockchip,bits = <5 1>;
276 clocks = <&xin24m>, <&aclk_peri_pre>;
277 clock-output-names = "clk_timer1";
279 #clock-init-cells = <1>;
282 clk_timer2: clk_timer2_mux {
283 compatible = "rockchip,rk3188-mux-con";
284 rockchip,bits = <6 1>;
285 clocks = <&xin24m>, <&aclk_peri_pre>;
286 clock-output-names = "clk_timer2";
288 #clock-init-cells = <1>;
291 clk_timer3: clk_timer3_mux {
292 compatible = "rockchip,rk3188-mux-con";
293 rockchip,bits = <7 1>;
294 clocks = <&xin24m>, <&aclk_peri_pre>;
295 clock-output-names = "clk_timer3";
297 #clock-init-cells = <1>;
300 /* reg[15:8]: reserved */
303 clk_sel_con3: sel-con@0050 {
304 compatible = "rockchip,rk3188-selcon";
306 #address-cells = <1>;
309 clk_i2s_pll_div: clk_i2s_pll_div {
310 compatible = "rockchip,rk3188-div-con";
311 rockchip,bits = <0 7>;
312 clocks = <&clk_i2s_pll>;
313 clock-output-names = "clk_i2s_pll";
314 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
316 rockchip,clkops-idx =
317 <CLKOPS_RATE_MUX_DIV>;
318 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
321 /* reg[7]: reserved */
323 clk_i2s: clk_i2s_mux {
324 compatible = "rockchip,rk3188-mux-con";
325 rockchip,bits = <8 2>;
326 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
327 clock-output-names = "clk_i2s";
329 rockchip,clkops-idx =
330 <CLKOPS_RATE_RK3288_I2S>;
331 rockchip,flags = <CLK_SET_RATE_PARENT>;
334 /* reg[11:10]: reserved */
336 clk_i2s_out: i2s_outclk_mux {
337 compatible = "rockchip,rk3188-mux-con";
338 rockchip,bits = <12 1>;
339 clocks = <&xin12m>, <&clk_i2s>;
340 clock-output-names = "i2s_clkout";
344 /* reg[13]: reserved */
346 clk_i2s_pll: i2s_pll_mux {
347 compatible = "rockchip,rk3188-mux-con";
348 rockchip,bits = <14 2>;
349 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
350 clock-output-names = "clk_i2s_pll";
352 #clock-init-cells = <1>;
357 clk_sel_con5: sel-con@0058 {
358 compatible = "rockchip,rk3188-selcon";
360 #address-cells = <1>;
363 spdif_div: spdif_div {
364 compatible = "rockchip,rk3188-div-con";
365 rockchip,bits = <0 7>;
366 clocks = <&clk_spdif_pll>;
367 clock-output-names = "clk_spdif_pll";
368 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
370 rockchip,clkops-idx =
371 <CLKOPS_RATE_MUX_DIV>;
372 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
375 /* reg[7]: reserved */
377 clk_spdif: spdif_mux {
378 compatible = "rockchip,rk3188-mux-con";
379 rockchip,bits = <8 2>;
380 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
381 clock-output-names = "clk_spdif";
383 rockchip,clkops-idx =
384 <CLKOPS_RATE_RK3288_I2S>;
385 rockchip,flags = <CLK_SET_RATE_PARENT>;
388 clk_spdif_pll: spdif_pll_mux {
389 compatible = "rockchip,rk3188-mux-con";
390 rockchip,bits = <10 2>;
391 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
392 clock-output-names = "clk_spdif_pll";
394 #clock-init-cells = <1>;
397 /* reg[15:12]: reserved */
400 clk_sel_con7: sel-con@0060 {
401 compatible = "rockchip,rk3188-selcon";
403 #address-cells = <1>;
407 compatible = "rockchip,rk3188-frac-con";
408 clocks = <&clk_i2s_pll>;
409 clock-output-names = "i2s_frac";
410 /* numerator denominator */
411 rockchip,bits = <0 32>;
412 rockchip,clkops-idx =
418 clk_sel_con9: sel-con@0068 {
419 compatible = "rockchip,rk3188-selcon";
421 #address-cells = <1>;
424 spdif_frac: spdif_frac {
425 compatible = "rockchip,rk3188-frac-con";
426 clocks = <&spdif_div>;
427 clock-output-names = "spdif_frac";
428 /* numerator denominator */
429 rockchip,bits = <0 32>;
430 rockchip,clkops-idx =
436 clk_sel_con10: sel-con@006c {
437 compatible = "rockchip,rk3188-selcon";
439 #address-cells = <1>;
442 aclk_peri_pre_div: aclk_peri_pre_div {
443 compatible = "rockchip,rk3188-div-con";
444 rockchip,bits = <0 5>;
445 clocks = <&aclk_peri_pre>;
446 clock-output-names = "aclk_peri_pre";
447 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
449 rockchip,clkops-idx =
450 <CLKOPS_RATE_MUX_DIV>;
451 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
454 /* reg[7:5]: reserved */
456 hclk_peri_pre: hclk_peri_pre_div {
457 compatible = "rockchip,rk3188-div-con";
458 rockchip,bits = <8 2>;
459 clocks = <&aclk_peri_pre>;
460 clock-output-names = "hclk_peri_pre";
461 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
462 rockchip,div-relations =
467 #clock-init-cells = <1>;
470 /* reg[11:10]: reserved */
472 pclk_peri_pre: pclk_peri_div {
473 compatible = "rockchip,rk3188-div-con";
474 rockchip,bits = <12 2>;
475 clocks = <&aclk_peri_pre>;
476 clock-output-names = "pclk_peri_pre";
477 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
478 rockchip,div-relations =
484 #clock-init-cells = <1>;
487 aclk_peri_pre: aclk_peri_pre_mux {
488 compatible = "rockchip,rk3188-mux-con";
489 rockchip,bits = <14 2>;
490 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
491 clock-output-names = "aclk_peri_pre";
493 #clock-init-cells = <1>;
497 clk_sel_con11: sel-con@0070 {
498 compatible = "rockchip,rk3188-selcon";
500 #address-cells = <1>;
503 clk_sdmmc0_div: clk_sdmmc0_div {
504 compatible = "rockchip,rk3188-div-con";
505 rockchip,bits = <0 6>;
506 clocks = <&clk_sdmmc0>;
507 clock-output-names = "clk_sdmmc0";
508 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
510 rockchip,clkops-idx =
511 <CLKOPS_RATE_MUX_EVENDIV>;
514 /* reg[7]: reserved */
516 clk_sdio_div: clk_sdio_div {
517 compatible = "rockchip,rk3188-div-con";
518 rockchip,bits = <8 7>;
519 clocks = <&clk_sdio>;
520 clock-output-names = "clk_sdio";
521 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
523 rockchip,clkops-idx =
524 <CLKOPS_RATE_MUX_EVENDIV>;
527 /* reg[15]: reserved */
531 clk_sel_con12: sel-con@0074 {
532 compatible = "rockchip,rk3188-selcon";
534 #address-cells = <1>;
537 clk_emmc_div: clk_emmc_div {
538 compatible = "rockchip,rk3188-div-con";
539 rockchip,bits = <0 7>;
540 clocks = <&clk_emmc>;
541 clock-output-names = "clk_emmc";
542 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
544 rockchip,clkops-idx =
545 <CLKOPS_RATE_MUX_EVENDIV>;
548 /* reg[7]: reserved */
550 clk_sdmmc0: clk_sdmmc0_mux {
551 compatible = "rockchip,rk3188-mux-con";
552 rockchip,bits = <8 2>;
553 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
554 clock-output-names = "clk_sdmmc0";
558 clk_sdio: clk_sdio_mux {
559 compatible = "rockchip,rk3188-mux-con";
560 rockchip,bits = <10 2>;
561 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
562 clock-output-names = "clk_sdio";
566 clk_emmc: clk_emmc_mux {
567 compatible = "rockchip,rk3188-mux-con";
568 rockchip,bits = <12 2>;
569 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
570 clock-output-names = "clk_emmc";
574 /* reg[15:14]: reserved */
577 clk_sel_con13: sel-con@0078 {
578 compatible = "rockchip,rk3188-selcon";
580 #address-cells = <1>;
583 clk_uart0_div: clk_uart0_div {
584 compatible = "rockchip,rk3188-div-con";
585 rockchip,bits = <0 7>;
586 clocks = <&clk_uart_pll>;
587 clock-output-names = "clk_uart0_div";
588 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
592 /* reg[7]: reserved */
594 clk_uart0: clk_uart0_mux {
595 compatible = "rockchip,rk3188-mux-con";
596 rockchip,bits = <8 2>;
597 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
598 clock-output-names = "clk_uart0";
600 rockchip,clkops-idx =
601 <CLKOPS_RATE_RK3288_I2S>;
602 rockchip,flags = <CLK_SET_RATE_PARENT>;
605 clk_uart_pll: clk_uart_pll_mux {
606 compatible = "rockchip,rk3188-mux-con";
607 rockchip,bits = <10 2>;
608 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
609 clock-output-names = "clk_uart_pll";
613 /* reg[15:12]: reserved */
617 clk_sel_con14: sel-con@007c {
618 compatible = "rockchip,rk3188-selcon";
620 #address-cells = <1>;
623 clk_uart1_div: clk_uart1_div {
624 compatible = "rockchip,rk3188-div-con";
625 rockchip,bits = <0 7>;
626 clocks = <&clk_uart_pll>;
627 clock-output-names = "clk_uart1_div";
628 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
632 /* reg[7]: reserved */
634 clk_uart1: clk_uart1_mux {
635 compatible = "rockchip,rk3188-mux-con";
636 rockchip,bits = <8 2>;
637 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
638 clock-output-names = "clk_uart1";
640 rockchip,clkops-idx =
641 <CLKOPS_RATE_RK3288_I2S>;
642 rockchip,flags = <CLK_SET_RATE_PARENT>;
645 /* reg[15:10]: reserved */
648 clk_sel_con15: sel-con@0080 {
649 compatible = "rockchip,rk3188-selcon";
651 #address-cells = <1>;
654 clk_uart2_div: clk_uart2_div {
655 compatible = "rockchip,rk3188-div-con";
656 rockchip,bits = <0 7>;
657 clocks = <&clk_uart_pll>;
658 clock-output-names = "clk_uart2_div";
659 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
663 /* reg[7]: reserved */
665 clk_uart2: clk_uart2_mux {
666 compatible = "rockchip,rk3188-mux-con";
667 rockchip,bits = <8 2>;
668 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
669 clock-output-names = "clk_uart2";
671 rockchip,clkops-idx =
672 <CLKOPS_RATE_RK3288_I2S>;
673 rockchip,flags = <CLK_SET_RATE_PARENT>;
676 /* reg[15:10]: reserved */
679 clk_sel_con16: sel-con@0084 {
680 compatible = "rockchip,rk3188-selcon";
682 #address-cells = <1>;
685 clk_sfc: clk_sfc_mux {
686 compatible = "rockchip,rk3188-mux-con";
687 rockchip,bits = <0 2>;
688 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
689 clock-output-names = "clk_sfc";
693 clk_sfc_div: clk_sfc_div {
694 compatible = "rockchip,rk3188-div-con";
695 rockchip,bits = <2 5>;
697 clock-output-names = "clk_sfc";
698 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
700 rockchip,clkops-idx =
701 <CLKOPS_RATE_MUX_DIV>;
704 /* reg[7]: reserved */
706 clk_nandc: clk_nandc_mux {
707 compatible = "rockchip,rk3188-mux-con";
708 rockchip,bits = <8 2>;
709 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
710 clock-output-names = "clk_nandc";
714 clk_nandc_div: clk_nandc_div {
715 compatible = "rockchip,rk3188-div-con";
716 rockchip,bits = <10 5>;
717 clocks = <&clk_nandc>;
718 clock-output-names = "clk_nandc";
719 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
721 rockchip,clkops-idx =
722 <CLKOPS_RATE_MUX_DIV>;
725 /* reg[31:15]: reserved */
728 clk_sel_con17: sel-con@0088 {
729 compatible = "rockchip,rk3188-selcon";
731 #address-cells = <1>;
734 uart0_frac: uart0_frac {
735 compatible = "rockchip,rk3188-frac-con";
736 clocks = <&clk_uart0_div>;
737 clock-output-names = "uart0_frac";
738 /* numerator denominator */
739 rockchip,bits = <0 32>;
740 rockchip,clkops-idx =
746 clk_sel_con18: sel-con@008c {
747 compatible = "rockchip,rk3188-selcon";
749 #address-cells = <1>;
752 uart1_frac: uart1_frac {
753 compatible = "rockchip,rk3188-frac-con";
754 clocks = <&clk_uart1_div>;
755 clock-output-names = "uart1_frac";
756 /* numerator denominator */
757 rockchip,bits = <0 32>;
758 rockchip,clkops-idx =
764 clk_sel_con19: sel-con@0090 {
765 compatible = "rockchip,rk3188-selcon";
767 #address-cells = <1>;
770 uart2_frac: uart2_frac {
771 compatible = "rockchip,rk3188-frac-con";
772 clocks = <&clk_uart2_div>;
773 clock-output-names = "uart2_frac";
774 /* numerator denominator */
775 rockchip,bits = <0 32>;
776 rockchip,clkops-idx =
783 clk_sel_con20: sel-con@0094 {
784 compatible = "rockchip,rk3188-selcon";
786 #address-cells = <1>;
789 clk_hevc_core: clk_hevc_core_mux {
790 compatible = "rockchip,rk3188-mux-con";
791 rockchip,bits = <0 2>;
792 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
793 clock-output-names = "clk_hevc_core";
797 clk_hevc_core_div: clk_hevc_core_div {
798 compatible = "rockchip,rk3188-div-con";
799 rockchip,bits = <2 5>;
800 clocks = <&clk_hevc_core>;
801 clock-output-names = "clk_hevc_core";
802 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
804 rockchip,clkops-idx =
805 <CLKOPS_RATE_MUX_DIV>;
808 /* reg[31:7]: reserved */
812 clk_sel_con21: sel-con@0098 {
813 compatible = "rockchip,rk3188-selcon";
815 #address-cells = <1>;
818 clk_mac_pll: clk_mac_pll_mux {
819 compatible = "rockchip,rk3188-mux-con";
820 rockchip,bits = <0 2>;
821 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
822 clock-output-names = "clk_mac_pll";
826 /* reg[2]: reserved */
828 clk_mac_ref: clk_mac_ref_mux {
829 compatible = "rockchip,rk3188-mux-con";
830 rockchip,bits = <3 1>;
831 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
832 clock-output-names = "clk_mac_ref";
834 rockchip,clkops-idx =
835 <CLKOPS_RATE_MAC_REF>;
836 rockchip,flags = <CLK_SET_RATE_PARENT>;
837 #clock-init-cells = <1>;
840 clk_mac_pll_div: clk_mac_pll_div {
841 compatible = "rockchip,rk3188-div-con";
842 rockchip,bits = <4 5>;
843 clocks = <&clk_mac_pll>;
844 clock-output-names = "clk_mac_pll";
845 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
847 rockchip,clkops-idx =
848 <CLKOPS_RATE_MUX_DIV>;
851 clk_mac_ref_div: clk_mac_ref_div {
852 compatible = "rockchip,rk3188-div-con";
853 rockchip,bits = <9 5>;
854 clocks = <&clk_mac_ref>;
855 clock-output-names = "clk_mac";
856 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
860 /* reg[15:14]: reserved */
863 clk_sel_con25: sel-con@00a8 {
864 compatible = "rockchip,rk3188-selcon";
866 #address-cells = <1>;
869 clk_spi0_div: clk_spi0_div {
870 compatible = "rockchip,rk3188-div-con";
871 rockchip,bits = <0 7>;
872 clocks = <&clk_spi0>;
873 clock-output-names = "clk_spi0";
874 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
876 rockchip,clkops-idx =
877 <CLKOPS_RATE_MUX_DIV>;
880 /* reg[7]: reserved */
882 clk_spi0: clk_spi0_mux {
883 compatible = "rockchip,rk3188-mux-con";
884 rockchip,bits = <8 2>;
885 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
886 clock-output-names = "clk_spi0";
890 /* reg[15:10]: reserved */
894 clk_sel_con26: sel-con@00ac {
895 compatible = "rockchip,rk3188-selcon";
897 #address-cells = <1>;
901 compatible = "rockchip,rk3188-div-con";
902 rockchip,bits = <0 2>;
904 clock-output-names = "clk_ddr";
905 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
906 rockchip,div-relations =
911 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
912 CLK_SET_RATE_NO_REPARENT)>;
913 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
916 /* reg[7:1]: reserved */
918 clk_ddr: ddr_clk_pll_mux {
919 compatible = "rockchip,rk3188-mux-con";
920 rockchip,bits = <8 1>;
921 clocks = <&clk_gates0 2>, <&clk_gates0 8>;
922 clock-output-names = "clk_ddr";
926 /* reg[15:9]: reserved */
929 clk_sel_con28: sel-con@00b4 {
930 compatible = "rockchip,rk3188-selcon";
932 #address-cells = <1>;
935 dclk_lcdc1: dclk_lcdc1_mux {
936 compatible = "rockchip,rk3188-mux-con";
937 rockchip,bits = <0 2>;
938 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
939 clock-output-names = "dclk_lcdc1";
943 /* reg[7:2]: reserved */
945 dclk_lcdc1_div: dclk_lcdc1_div {
946 compatible = "rockchip,rk3188-div-con";
947 rockchip,bits = <8 8>;
948 clocks = <&dclk_lcdc1>;
949 clock-output-names = "dclk_lcdc1";
950 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
952 rockchip,clkops-idx =
953 <CLKOPS_RATE_RK3288_DCLK_LCDC0>;
954 rockchip,flags = <CLK_SET_RATE_PARENT>;
958 clk_sel_con30: sel-con@00bc {
959 compatible = "rockchip,rk3188-selcon";
961 #address-cells = <1>;
964 clk_testout_div: clk_testout_div {
965 compatible = "rockchip,rk3188-div-con";
966 rockchip,bits = <0 5>;
968 clock-output-names = "clk_testout";
969 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
971 #clock-init-cells = <1>;
974 /* reg[7:5]: reserved */
976 hclk_vio_pre_div: hclk_vio_pre_div {
977 compatible = "rockchip,rk3188-div-con";
978 rockchip,bits = <8 5>;
979 clocks = <&hclk_vio_pre>;
980 clock-output-names = "hclk_vio_pre";
981 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
983 rockchip,clkops-idx =
984 <CLKOPS_RATE_MUX_DIV>;
985 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
988 /* reg[13]: reserved */
990 hclk_vio_pre: hclk_vio_pre_mux {
991 compatible = "rockchip,rk3188-mux-con";
992 rockchip,bits = <14 2>;
993 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
994 clock-output-names = "hclk_vio_pre";
996 #clock-init-cells = <1>;
1001 clk_sel_con31: sel-con@00c0 {
1002 compatible = "rockchip,rk3188-selcon";
1004 #address-cells = <1>;
1007 clk_hdmi: clk_hdmi_mux {
1008 compatible = "rockchip,rk3188-mux-con";
1009 rockchip,bits = <0 1>;
1010 clocks = <&dclk_lcdc1_div>, <&dummy>;
1011 clock-output-names = "clk_hdmi";
1015 /* reg[7:1]: reserved */
1017 aclk_vio_pre_div: aclk_vio_pre_div {
1018 compatible = "rockchip,rk3188-div-con";
1019 rockchip,bits = <8 5>;
1020 clocks = <&aclk_vio_pre>;
1021 clock-output-names = "aclk_vio_pre";
1022 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1024 rockchip,clkops-idx =
1025 <CLKOPS_RATE_MUX_DIV>;
1026 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1029 /* reg[13]: reserved */
1031 aclk_vio_pre: aclk_vio_pre_mux {
1032 compatible = "rockchip,rk3188-mux-con";
1033 rockchip,bits = <14 2>;
1034 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1035 clock-output-names = "aclk_vio_pre";
1037 #clock-init-cells = <1>;
1042 clk_sel_con32: sel-con@00c4 {
1043 compatible = "rockchip,rk3188-selcon";
1045 #address-cells = <1>;
1048 /* reg[7:0]: reserved */
1050 aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1051 compatible = "rockchip,rk3188-div-con";
1052 rockchip,bits = <8 5>;
1053 clocks = <&aclk_vcodec_pre>;
1054 clock-output-names = "aclk_vcodec_pre";
1055 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1057 rockchip,clkops-idx =
1058 <CLKOPS_RATE_MUX_DIV>;
1061 /* reg[13]: reserved */
1063 aclk_vcodec_pre: aclk_vcodec_pre_mux {
1064 compatible = "rockchip,rk3188-mux-con";
1065 rockchip,bits = <14 2>;
1066 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1067 clock-output-names = "aclk_vcodec_pre";
1069 #clock-init-cells = <1>;
1073 clk_sel_con34: sel-con@00cc {
1074 compatible = "rockchip,rk3188-selcon";
1076 #address-cells = <1>;
1079 clk_gpu_pre_div: clk_gpu_pre_div {
1080 compatible = "rockchip,rk3188-div-con";
1081 rockchip,bits = <0 5>;
1082 clocks = <&clk_gpu_pre>;
1083 clock-output-names = "clk_gpu_pre";
1084 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1086 rockchip,clkops-idx =
1087 <CLKOPS_RATE_MUX_DIV>;
1088 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1091 /* reg[7:5]: reserved */
1093 clk_gpu_pre: clk_gpu_pre_mux {
1094 compatible = "rockchip,rk3188-mux-con";
1095 rockchip,bits = <8 2>;
1096 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1097 clock-output-names = "clk_gpu_pre";
1099 #clock-init-cells = <1>;
1102 /* reg[15:10]: reserved */
1109 /* Gate control regs */
1111 compatible = "rockchip,rk-gate-cons";
1112 #address-cells = <1>;
1116 clk_gates0: gate-clk@00d0{
1117 compatible = "rockchip,rk3188-gate-clk";
1120 <&clk_core_pre>, <&clk_gpll>,
1121 <&clk_dpll>, <&aclk_cpu_pre>,
1123 <&aclk_cpu_pre>, <&aclk_cpu_pre>,
1124 <&clk_gpll>, <&clk_core_pre>,
1126 <&clk_gpll>, <&clk_i2s_pll>,
1127 <&i2s_frac>, <&hclk_vio_pre>,
1129 <&dummy>, <&clk_i2s_out>,
1130 <&clk_i2s>, <&dummy>;
1132 clock-output-names =
1133 "clk_core_pre", "reserved", /* do not use bit1 = "cpu_gpll" */
1134 "reserved", "aclk_cpu_pre",
1136 "hclk_cpu_pre", "pclk_cpu_pre",
1137 "reserved", "aclk_core_pre",
1139 "reserved", "clk_i2s_pll",
1140 "i2s_frac", "hclk_vio_pre",
1142 "clk_cryto", "clk_i2s_out",
1143 "clk_i2s", "clk_testout";
1144 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1149 clk_gates1: gate-clk@00d4{
1150 compatible = "rockchip,rk3188-gate-clk";
1153 <&clk_timer0>, <&clk_timer1>,
1156 <&aclk_vio_pre>, <&xin12m>,
1159 <&clk_uart0_div>, <&uart0_frac>,
1160 <&clk_uart1_div>, <&uart1_frac>,
1162 <&clk_uart2_div>, <&uart2_frac>,
1165 clock-output-names =
1166 "clk_timer0", "clk_timer1",
1167 "reserved", "clk_jatg",
1169 "aclk_vio_pre", "clk_otgphy0",
1170 "clk_otgphy1", "reserved",
1172 "clk_uart0_div", "uart0_frac",
1173 "clk_uart1_div", "uart1_frac",
1175 "clk_uart2_div", "uart2_frac",
1176 "reserved", "reserved";
1178 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1182 clk_gates2: gate-clk@00d8 {
1183 compatible = "rockchip,rk3188-gate-clk";
1186 <&aclk_peri_pre>, <&aclk_peri_pre>,
1187 <&aclk_peri_pre>, <&aclk_peri_pre>,
1189 <&clk_timer2>, <&clk_timer3>,
1190 <&clk_mac_ref>, <&dummy>,
1192 <&dummy>, <&clk_spi0>,
1193 <&clk_spdif_pll>, <&clk_sdmmc0>,
1195 <&spdif_frac>, <&clk_sdio>,
1196 <&clk_emmc>, <&dummy>;
1198 clock-output-names =
1199 "aclk_peri", "aclk_peri_pre",
1200 "hclk_peri_pre", "pclk_peri_pre",
1202 "clk_timer2", "clk_timer3",
1203 "clk_mac", "reserved",
1205 "reserved", "clk_spi0",
1206 "clk_spdif_pll", "clk_sdmmc0",
1208 "spdif_frac", "clk_sdio",
1209 "clk_emmc", "reserved";
1210 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1215 clk_gates3: gate-clk@00dc {
1216 compatible = "rockchip,rk3188-gate-clk";
1220 <&dclk_lcdc1>, <&dummy>,
1225 <&pclk_cpu_pre>, <&dummy>,
1226 <&dummy>, <&aclk_vcodec_pre>,
1228 <&aclk_vcodec_pre>, <&clk_gpu_pre>,
1229 <&hclk_peri_pre>, <&dummy>;
1231 clock-output-names =
1232 "reserved", "reserved",
1233 "dclk_lcdc1", "reserved",
1235 "reserved", "reserved",
1236 "reserved", "reserved",
1238 "g_pclk_hdmi", "reserved",
1239 "reserved", "aclk_vcodec_pre",
1241 "hclk_vcodec", "clk_gpu_pre",
1242 "g_hclk_sfc", "reserved";
1243 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1248 clk_gates4: gate-clk@00e0{
1249 compatible = "rockchip,rk3188-gate-clk";
1252 <&hclk_peri_pre>, <&pclk_peri_pre>,
1253 <&aclk_peri_pre>, <&aclk_peri_pre>,
1259 <&aclk_cpu_pre>, <&dummy>,
1261 <&aclk_cpu_pre>, <&dummy>,
1264 clock-output-names =
1265 "g_hp_axi_matrix", "g_pp_axi_matrix",
1266 "g_aclk_cpu_peri", "g_ap_axi_matrix",
1268 "reserved", "reserved",
1269 "reserved", "reserved",
1271 "reserved", "reserved",
1272 "g_aclk_strc_sys", "reserved",
1274 /* Not use these ddr gates */
1275 "g_aclk_intmem", "reserved",
1276 "reserved", "reserved";
1278 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1282 clk_gates5: gate-clk@00e4 {
1283 compatible = "rockchip,rk3188-gate-clk";
1286 <&dummy>, <&aclk_peri_pre>,
1287 <&pclk_peri_pre>, <&dummy>,
1289 <&pclk_cpu_pre>, <&dummy>,
1290 <&hclk_cpu_pre>, <&pclk_cpu_pre>,
1292 <&dummy>, <&hclk_peri_pre>,
1293 <&hclk_peri_pre>, <&hclk_peri_pre>,
1295 <&dummy>, <&hclk_peri_pre>,
1296 <&pclk_cpu_pre>, <&dummy>;
1298 clock-output-names =
1299 "reserved", "g_aclk_dmac2",
1300 "g_pclk_efuse", "reserved",
1302 "g_pclk_grf", "reserved",
1303 "g_hclk_rom", "g_pclk_ddrupctl",
1305 "reserved", "g_hclk_nandc",
1306 "g_hclk_sdmmc0", "g_hclk_sdio",
1308 "reserved", "g_hclk_otg0",
1309 "g_pclk_acodec", "reserved";
1311 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1316 clk_gates6: gate-clk@00e8 {
1317 compatible = "rockchip,rk3188-gate-clk";
1329 <&hclk_vio_pre>, <&aclk_vio_pre>,
1332 clock-output-names =
1333 "reserved", "reserved",
1334 "reserved", "reserved",
1336 "reserved", "reserved",
1337 "reserved", "reserved",
1339 "reserved", "reserved",
1340 "reserved", "reserved",
1342 "g_hclk_vio_bus", "g_aclk_vio",
1343 "reserved", "reserved";
1345 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1350 clk_gates7: gate-clk@00ec {
1351 compatible = "rockchip,rk3188-gate-clk";
1354 <&hclk_peri_pre>, <&dummy>,
1355 <&hclk_peri_pre>, <&hclk_peri_pre>,
1358 <&dummy>, <&pclk_peri_pre>,
1361 <&pclk_peri_pre>, <&dummy>,
1363 <&pclk_peri_pre>, <&dummy>,
1364 <&dummy>, <&pclk_peri_pre>;
1366 clock-output-names =
1367 "g_hclk_emmc", "reserved",
1368 "g_hclk_i2s", "g_hclk_otg1",
1370 "reserved", "reserved",
1371 "reserved", "g_pclk_timer0",
1373 "reserved", "reserved",
1374 "g_pclk_pwm", "reserved",
1376 "g_pclk_spi", "reserved",
1377 "reserved", "g_pclk_wdt";
1379 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1384 clk_gates8: gate-clk@00f0 {
1385 compatible = "rockchip,rk3188-gate-clk";
1388 <&pclk_peri_pre>, <&pclk_peri_pre>,
1389 <&pclk_peri_pre>, <&dummy>,
1391 <&pclk_peri_pre>, <&pclk_peri_pre>,
1392 <&pclk_peri_pre>, <&dummy>,
1394 <&dummy>, <&pclk_peri_pre>,
1395 <&pclk_peri_pre>, <&pclk_peri_pre>,
1400 clock-output-names =
1401 "g_pclk_uart0", "g_pclk_uart1",
1402 "g_pclk_uart2", "reserved",
1404 "g_pclk_i2c0", "g_pclk_i2c1",
1405 "g_pclk_i2c2", "reserved",
1407 "reserved", "g_pclk_gpio0",
1408 "g_pclk_gpio1", "g_pclk_gpio2",
1410 "reserved", "reserved",
1411 "reserved", "reserved";
1413 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1417 clk_gates9: gate-clk@00f4 {
1418 compatible = "rockchip,rk3188-gate-clk";
1424 <&dummy>, <&hclk_vio_pre>,
1425 <&aclk_vio_pre>, <&dummy>,
1430 <&dummy>, <&hclk_peri_pre>,
1431 <&hclk_peri_pre>, <&aclk_peri_pre>;
1433 clock-output-names =
1434 "reserved", "reserved",
1435 "reserved", "reserved",
1437 "reserved", "g_hclk_lcdc",
1438 "g_aclk_lcdc", "reserved",
1440 "reserved", "reserved",
1441 "reserved", "reserved",
1443 "reserved", "g_hclk_usb_peri",
1444 "g_hclk_peri_arbi", "g_aclk_peri_niu";
1446 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1451 clk_gates10: gate-clk@00f8 {
1452 compatible = "rockchip,rk3188-gate-clk";
1455 <&xin24m>, <&xin24m>,
1456 <&xin24m>, <&dummy>,
1458 <&clk_nandc>, <&clk_sfc>,
1459 <&clk_hevc_core>, <&dummy>,
1461 <&clk_dpll>, <&dummy>,
1467 clock-output-names =
1468 "g_clk_pvtm_core", "g_clk_pvtm_gpu",
1469 "g_clk_pvtm_video", "reserved",
1471 "clk_nandc", "clk_sfc",
1472 "clk_hevc_core", "reserved",
1474 "reserved", "reserved",
1475 "reserved", "reserved",
1477 "reserved", "reserved",
1478 "reserved", "reserved";
1480 rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */