arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,gic-400";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         cmt0: timer@ffca0000 {
  54                 compatible = "renesas,cmt-48-gen2";
  55                 reg = <0 0xffca0000 0 0x1004>;
  56                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
  57                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
  58                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
  59                 clock-names = "fck";
  60
  61                 renesas,channels-mask = <0x60>;
  62
  63                 status = "disabled";
  64         };
  65
  66         cmt1: timer@e6130000 {
  67                 compatible = "renesas,cmt-48-gen2";
  68                 reg = <0 0xe6130000 0 0x1004>;
  69                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
  70                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
  71                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
  72                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
  73                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
  74                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
  75                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
  76                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
  78                 clock-names = "fck";
  79
  80                 renesas,channels-mask = <0xff>;
  81
  82                 status = "disabled";
  83         };
  84
  85         timer {
  86                 compatible = "arm,armv7-timer";
  87                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  91         };
  92
  93         irqc0: interrupt-controller@e61c0000 {
  94                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
  95                 #interrupt-cells = <2>;
  96                 interrupt-controller;
  97                 reg = <0 0xe61c0000 0 0x200>;
  98                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
  99                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 100                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 101                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 102                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 103                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 104                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 105                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 106                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 107                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 108                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 109         };
 110
 111         pfc: pin-controller@e6060000 {
 112                 compatible = "renesas,pfc-r8a7794";
 113                 reg = <0 0xe6060000 0 0x11c>;
 114                 #gpio-range-cells = <3>;
 115         };
 116
 117         dmac0: dma-controller@e6700000 {
 118                 compatible = "renesas,rcar-dmac";
 119                 reg = <0 0xe6700000 0 0x20000>;
 120                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 121                               0 200 IRQ_TYPE_LEVEL_HIGH
 122                               0 201 IRQ_TYPE_LEVEL_HIGH
 123                               0 202 IRQ_TYPE_LEVEL_HIGH
 124                               0 203 IRQ_TYPE_LEVEL_HIGH
 125                               0 204 IRQ_TYPE_LEVEL_HIGH
 126                               0 205 IRQ_TYPE_LEVEL_HIGH
 127                               0 206 IRQ_TYPE_LEVEL_HIGH
 128                               0 207 IRQ_TYPE_LEVEL_HIGH
 129                               0 208 IRQ_TYPE_LEVEL_HIGH
 130                               0 209 IRQ_TYPE_LEVEL_HIGH
 131                               0 210 IRQ_TYPE_LEVEL_HIGH
 132                               0 211 IRQ_TYPE_LEVEL_HIGH
 133                               0 212 IRQ_TYPE_LEVEL_HIGH
 134                               0 213 IRQ_TYPE_LEVEL_HIGH
 135                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 136                 interrupt-names = "error",
 137                                 "ch0", "ch1", "ch2", "ch3",
 138                                 "ch4", "ch5", "ch6", "ch7",
 139                                 "ch8", "ch9", "ch10", "ch11",
 140                                 "ch12", "ch13", "ch14";
 141                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 142                 clock-names = "fck";
 143                 #dma-cells = <1>;
 144                 dma-channels = <15>;
 145         };
 146
 147         dmac1: dma-controller@e6720000 {
 148                 compatible = "renesas,rcar-dmac";
 149                 reg = <0 0xe6720000 0 0x20000>;
 150                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 151                               0 216 IRQ_TYPE_LEVEL_HIGH
 152                               0 217 IRQ_TYPE_LEVEL_HIGH
 153                               0 218 IRQ_TYPE_LEVEL_HIGH
 154                               0 219 IRQ_TYPE_LEVEL_HIGH
 155                               0 308 IRQ_TYPE_LEVEL_HIGH
 156                               0 309 IRQ_TYPE_LEVEL_HIGH
 157                               0 310 IRQ_TYPE_LEVEL_HIGH
 158                               0 311 IRQ_TYPE_LEVEL_HIGH
 159                               0 312 IRQ_TYPE_LEVEL_HIGH
 160                               0 313 IRQ_TYPE_LEVEL_HIGH
 161                               0 314 IRQ_TYPE_LEVEL_HIGH
 162                               0 315 IRQ_TYPE_LEVEL_HIGH
 163                               0 316 IRQ_TYPE_LEVEL_HIGH
 164                               0 317 IRQ_TYPE_LEVEL_HIGH
 165                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 166                 interrupt-names = "error",
 167                                 "ch0", "ch1", "ch2", "ch3",
 168                                 "ch4", "ch5", "ch6", "ch7",
 169                                 "ch8", "ch9", "ch10", "ch11",
 170                                 "ch12", "ch13", "ch14";
 171                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 172                 clock-names = "fck";
 173                 #dma-cells = <1>;
 174                 dma-channels = <15>;
 175         };
 176
 177         scifa0: serial@e6c40000 {
 178                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 179                 reg = <0 0xe6c40000 0 64>;
 180                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 182                 clock-names = "sci_ick";
 183                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 184                 dma-names = "tx", "rx";
 185                 status = "disabled";
 186         };
 187
 188         scifa1: serial@e6c50000 {
 189                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 190                 reg = <0 0xe6c50000 0 64>;
 191                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 193                 clock-names = "sci_ick";
 194                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 195                 dma-names = "tx", "rx";
 196                 status = "disabled";
 197         };
 198
 199         scifa2: serial@e6c60000 {
 200                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 201                 reg = <0 0xe6c60000 0 64>;
 202                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 204                 clock-names = "sci_ick";
 205                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 206                 dma-names = "tx", "rx";
 207                 status = "disabled";
 208         };
 209
 210         scifa3: serial@e6c70000 {
 211                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 212                 reg = <0 0xe6c70000 0 64>;
 213                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 215                 clock-names = "sci_ick";
 216                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 217                 dma-names = "tx", "rx";
 218                 status = "disabled";
 219         };
 220
 221         scifa4: serial@e6c78000 {
 222                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 223                 reg = <0 0xe6c78000 0 64>;
 224                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 226                 clock-names = "sci_ick";
 227                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 228                 dma-names = "tx", "rx";
 229                 status = "disabled";
 230         };
 231
 232         scifa5: serial@e6c80000 {
 233                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 234                 reg = <0 0xe6c80000 0 64>;
 235                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 237                 clock-names = "sci_ick";
 238                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 239                 dma-names = "tx", "rx";
 240                 status = "disabled";
 241         };
 242
 243         scifb0: serial@e6c20000 {
 244                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 245                 reg = <0 0xe6c20000 0 64>;
 246                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 248                 clock-names = "sci_ick";
 249                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 250                 dma-names = "tx", "rx";
 251                 status = "disabled";
 252         };
 253
 254         scifb1: serial@e6c30000 {
 255                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 256                 reg = <0 0xe6c30000 0 64>;
 257                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 259                 clock-names = "sci_ick";
 260                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 261                 dma-names = "tx", "rx";
 262                 status = "disabled";
 263         };
 264
 265         scifb2: serial@e6ce0000 {
 266                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 267                 reg = <0 0xe6ce0000 0 64>;
 268                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 270                 clock-names = "sci_ick";
 271                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 272                 dma-names = "tx", "rx";
 273                 status = "disabled";
 274         };
 275
 276         scif0: serial@e6e60000 {
 277                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 278                 reg = <0 0xe6e60000 0 64>;
 279                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
 281                 clock-names = "sci_ick";
 282                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 283                 dma-names = "tx", "rx";
 284                 status = "disabled";
 285         };
 286
 287         scif1: serial@e6e68000 {
 288                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 289                 reg = <0 0xe6e68000 0 64>;
 290                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 291                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
 292                 clock-names = "sci_ick";
 293                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 294                 dma-names = "tx", "rx";
 295                 status = "disabled";
 296         };
 297
 298         scif2: serial@e6e58000 {
 299                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 300                 reg = <0 0xe6e58000 0 64>;
 301                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
 303                 clock-names = "sci_ick";
 304                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 305                 dma-names = "tx", "rx";
 306                 status = "disabled";
 307         };
 308
 309         scif3: serial@e6ea8000 {
 310                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 311                 reg = <0 0xe6ea8000 0 64>;
 312                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
 314                 clock-names = "sci_ick";
 315                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 316                 dma-names = "tx", "rx";
 317                 status = "disabled";
 318         };
 319
 320         scif4: serial@e6ee0000 {
 321                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 322                 reg = <0 0xe6ee0000 0 64>;
 323                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
 325                 clock-names = "sci_ick";
 326                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 327                 dma-names = "tx", "rx";
 328                 status = "disabled";
 329         };
 330
 331         scif5: serial@e6ee8000 {
 332                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 333                 reg = <0 0xe6ee8000 0 64>;
 334                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
 336                 clock-names = "sci_ick";
 337                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 338                 dma-names = "tx", "rx";
 339                 status = "disabled";
 340         };
 341
 342         hscif0: serial@e62c0000 {
 343                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 344                 reg = <0 0xe62c0000 0 96>;
 345                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
 347                 clock-names = "sci_ick";
 348                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 349                 dma-names = "tx", "rx";
 350                 status = "disabled";
 351         };
 352
 353         hscif1: serial@e62c8000 {
 354                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 355                 reg = <0 0xe62c8000 0 96>;
 356                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 357                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
 358                 clock-names = "sci_ick";
 359                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 360                 dma-names = "tx", "rx";
 361                 status = "disabled";
 362         };
 363
 364         hscif2: serial@e62d0000 {
 365                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 366                 reg = <0 0xe62d0000 0 96>;
 367                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
 369                 clock-names = "sci_ick";
 370                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 371                 dma-names = "tx", "rx";
 372                 status = "disabled";
 373         };
 374
 375         ether: ethernet@ee700000 {
 376                 compatible = "renesas,ether-r8a7794";
 377                 reg = <0 0xee700000 0 0x400>;
 378                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 380                 phy-mode = "rmii";
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 status = "disabled";
 384         };
 385
 386         sdhi0: sd@ee100000 {
 387                 compatible = "renesas,sdhi-r8a7794";
 388                 reg = <0 0xee100000 0 0x200>;
 389                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 391                 status = "disabled";
 392         };
 393
 394         sdhi1: sd@ee140000 {
 395                 compatible = "renesas,sdhi-r8a7794";
 396                 reg = <0 0xee140000 0 0x100>;
 397                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 399                 status = "disabled";
 400         };
 401
 402         sdhi2: sd@ee160000 {
 403                 compatible = "renesas,sdhi-r8a7794";
 404                 reg = <0 0xee160000 0 0x100>;
 405                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 407                 status = "disabled";
 408         };
 409
 410         clocks {
 411                 #address-cells = <2>;
 412                 #size-cells = <2>;
 413                 ranges;
 414
 415                 /* External root clock */
 416                 extal_clk: extal_clk {
 417                         compatible = "fixed-clock";
 418                         #clock-cells = <0>;
 419                         /* This value must be overriden by the board. */
 420                         clock-frequency = <0>;
 421                         clock-output-names = "extal";
 422                 };
 423
 424                 /* Special CPG clocks */
 425                 cpg_clocks: cpg_clocks@e6150000 {
 426                         compatible = "renesas,r8a7794-cpg-clocks",
 427                                      "renesas,rcar-gen2-cpg-clocks";
 428                         reg = <0 0xe6150000 0 0x1000>;
 429                         clocks = <&extal_clk>;
 430                         #clock-cells = <1>;
 431                         clock-output-names = "main", "pll0", "pll1", "pll3",
 432                                              "lb", "qspi", "sdh", "sd0", "z";
 433                 };
 434                 /* Variable factor clocks */
 435                 sd2_clk: sd2_clk@e6150078 {
 436                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 437                         reg = <0 0xe6150078 0 4>;
 438                         clocks = <&pll1_div2_clk>;
 439                         #clock-cells = <0>;
 440                         clock-output-names = "sd2";
 441                 };
 442                 sd3_clk: sd3_clk@e615026c {
 443                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 444                         reg = <0 0xe615026c 0 4>;
 445                         clocks = <&pll1_div2_clk>;
 446                         #clock-cells = <0>;
 447                         clock-output-names = "sd3";
 448                 };
 449                 mmc0_clk: mmc0_clk@e6150240 {
 450                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 451                         reg = <0 0xe6150240 0 4>;
 452                         clocks = <&pll1_div2_clk>;
 453                         #clock-cells = <0>;
 454                         clock-output-names = "mmc0";
 455                 };
 456
 457                 /* Fixed factor clocks */
 458                 pll1_div2_clk: pll1_div2_clk {
 459                         compatible = "fixed-factor-clock";
 460                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 461                         #clock-cells = <0>;
 462                         clock-div = <2>;
 463                         clock-mult = <1>;
 464                         clock-output-names = "pll1_div2";
 465                 };
 466                 zg_clk: zg_clk {
 467                         compatible = "fixed-factor-clock";
 468                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 469                         #clock-cells = <0>;
 470                         clock-div = <6>;
 471                         clock-mult = <1>;
 472                         clock-output-names = "zg";
 473                 };
 474                 zx_clk: zx_clk {
 475                         compatible = "fixed-factor-clock";
 476                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 477                         #clock-cells = <0>;
 478                         clock-div = <3>;
 479                         clock-mult = <1>;
 480                         clock-output-names = "zx";
 481                 };
 482                 zs_clk: zs_clk {
 483                         compatible = "fixed-factor-clock";
 484                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 485                         #clock-cells = <0>;
 486                         clock-div = <6>;
 487                         clock-mult = <1>;
 488                         clock-output-names = "zs";
 489                 };
 490                 hp_clk: hp_clk {
 491                         compatible = "fixed-factor-clock";
 492                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 493                         #clock-cells = <0>;
 494                         clock-div = <12>;
 495                         clock-mult = <1>;
 496                         clock-output-names = "hp";
 497                 };
 498                 i_clk: i_clk {
 499                         compatible = "fixed-factor-clock";
 500                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 501                         #clock-cells = <0>;
 502                         clock-div = <2>;
 503                         clock-mult = <1>;
 504                         clock-output-names = "i";
 505                 };
 506                 b_clk: b_clk {
 507                         compatible = "fixed-factor-clock";
 508                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 509                         #clock-cells = <0>;
 510                         clock-div = <12>;
 511                         clock-mult = <1>;
 512                         clock-output-names = "b";
 513                 };
 514                 p_clk: p_clk {
 515                         compatible = "fixed-factor-clock";
 516                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 517                         #clock-cells = <0>;
 518                         clock-div = <24>;
 519                         clock-mult = <1>;
 520                         clock-output-names = "p";
 521                 };
 522                 cl_clk: cl_clk {
 523                         compatible = "fixed-factor-clock";
 524                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 525                         #clock-cells = <0>;
 526                         clock-div = <48>;
 527                         clock-mult = <1>;
 528                         clock-output-names = "cl";
 529                 };
 530                 m2_clk: m2_clk {
 531                         compatible = "fixed-factor-clock";
 532                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 533                         #clock-cells = <0>;
 534                         clock-div = <8>;
 535                         clock-mult = <1>;
 536                         clock-output-names = "m2";
 537                 };
 538                 imp_clk: imp_clk {
 539                         compatible = "fixed-factor-clock";
 540                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 541                         #clock-cells = <0>;
 542                         clock-div = <4>;
 543                         clock-mult = <1>;
 544                         clock-output-names = "imp";
 545                 };
 546                 rclk_clk: rclk_clk {
 547                         compatible = "fixed-factor-clock";
 548                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 549                         #clock-cells = <0>;
 550                         clock-div = <(48 * 1024)>;
 551                         clock-mult = <1>;
 552                         clock-output-names = "rclk";
 553                 };
 554                 oscclk_clk: oscclk_clk {
 555                         compatible = "fixed-factor-clock";
 556                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 557                         #clock-cells = <0>;
 558                         clock-div = <(12 * 1024)>;
 559                         clock-mult = <1>;
 560                         clock-output-names = "oscclk";
 561                 };
 562                 zb3_clk: zb3_clk {
 563                         compatible = "fixed-factor-clock";
 564                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 565                         #clock-cells = <0>;
 566                         clock-div = <4>;
 567                         clock-mult = <1>;
 568                         clock-output-names = "zb3";
 569                 };
 570                 zb3d2_clk: zb3d2_clk {
 571                         compatible = "fixed-factor-clock";
 572                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 573                         #clock-cells = <0>;
 574                         clock-div = <8>;
 575                         clock-mult = <1>;
 576                         clock-output-names = "zb3d2";
 577                 };
 578                 ddr_clk: ddr_clk {
 579                         compatible = "fixed-factor-clock";
 580                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 581                         #clock-cells = <0>;
 582                         clock-div = <8>;
 583                         clock-mult = <1>;
 584                         clock-output-names = "ddr";
 585                 };
 586                 mp_clk: mp_clk {
 587                         compatible = "fixed-factor-clock";
 588                         clocks = <&pll1_div2_clk>;
 589                         #clock-cells = <0>;
 590                         clock-div = <15>;
 591                         clock-mult = <1>;
 592                         clock-output-names = "mp";
 593                 };
 594                 cp_clk: cp_clk {
 595                         compatible = "fixed-factor-clock";
 596                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 597                         #clock-cells = <0>;
 598                         clock-div = <48>;
 599                         clock-mult = <1>;
 600                         clock-output-names = "cp";
 601                 };
 602
 603                 acp_clk: acp_clk {
 604                         compatible = "fixed-factor-clock";
 605                         clocks = <&extal_clk>;
 606                         #clock-cells = <0>;
 607                         clock-div = <2>;
 608                         clock-mult = <1>;
 609                         clock-output-names = "acp";
 610                 };
 611
 612                 /* Gate clocks */
 613                 mstp0_clks: mstp0_clks@e6150130 {
 614                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 615                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 616                         clocks = <&mp_clk>;
 617                         #clock-cells = <1>;
 618                         clock-indices = <R8A7794_CLK_MSIOF0>;
 619                         clock-output-names = "msiof0";
 620                 };
 621                 mstp1_clks: mstp1_clks@e6150134 {
 622                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 623                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 624                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
 625                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 626                                  <&zs_clk>, <&zs_clk>;
 627                         #clock-cells = <1>;
 628                         clock-indices = <
 629                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
 630                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
 631                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
 632                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
 633                         >;
 634                         clock-output-names =
 635                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
 636                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
 637                 };
 638                 mstp2_clks: mstp2_clks@e6150138 {
 639                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 640                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 641                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 642                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
 643                                  <&zs_clk>, <&zs_clk>;
 644                         #clock-cells = <1>;
 645                         clock-indices = <
 646                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
 647                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
 648                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
 649                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
 650                         >;
 651                         clock-output-names =
 652                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 653                                 "scifb1", "msiof1", "scifb2",
 654                                 "sys-dmac1", "sys-dmac0";
 655                 };
 656                 mstp3_clks: mstp3_clks@e615013c {
 657                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 658                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 659                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
 660                                  <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 661                         #clock-cells = <1>;
 662                         clock-indices = <
 663                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
 664                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
 665                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
 666                         >;
 667                         clock-output-names =
 668                                 "sdhi2", "sdhi1", "sdhi0",
 669                                 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
 670                 };
 671                 mstp4_clks: mstp4_clks@e6150140 {
 672                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 673                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 674                         clocks = <&cp_clk>;
 675                         #clock-cells = <1>;
 676                         clock-indices = <R8A7794_CLK_IRQC>;
 677                         clock-output-names = "irqc";
 678                 };
 679                 mstp7_clks: mstp7_clks@e615014c {
 680                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 681                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 682                         clocks = <&mp_clk>, <&mp_clk>,
 683                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 684                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 685                         #clock-cells = <1>;
 686                         clock-indices = <
 687                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
 688                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
 689                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
 690                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
 691                                 R8A7794_CLK_SCIF0
 692                         >;
 693                         clock-output-names =
 694                                 "ehci", "hsusb",
 695                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 696                                 "scif3", "scif2", "scif1", "scif0";
 697                 };
 698                 mstp8_clks: mstp8_clks@e6150990 {
 699                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 700                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 701                         clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
 702                         #clock-cells = <1>;
 703                         clock-indices = <
 704                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
 705                         >;
 706                         clock-output-names =
 707                                 "vin1", "vin0", "ether";
 708                 };
 709                 mstp9_clks: mstp9_clks@e6150994 {
 710                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 711                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 712                         clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
 713                                 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 714                         #clock-cells = <1>;
 715                         clock-indices = <
 716                                 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
 717                                 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
 718                                 R8A7794_CLK_I2C0
 719                         >;
 720                         clock-output-names =
 721                                 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
 722                 };
 723                 mstp11_clks: mstp11_clks@e615099c {
 724                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 725                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 726                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 727                         #clock-cells = <1>;
 728                         clock-indices = <
 729                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
 730                         >;
 731                         clock-output-names = "scifa3", "scifa4", "scifa5";
 732                 };
 733         };
 734
 735         ipmmu_sy0: mmu@e6280000 {
 736                 compatible = "renesas,ipmmu-vmsa";
 737                 reg = <0 0xe6280000 0 0x1000>;
 738                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
 739                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
 740                 #iommu-cells = <1>;
 741                 status = "disabled";
 742         };
 743
 744         ipmmu_sy1: mmu@e6290000 {
 745                 compatible = "renesas,ipmmu-vmsa";
 746                 reg = <0 0xe6290000 0 0x1000>;
 747                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
 748                 #iommu-cells = <1>;
 749                 status = "disabled";
 750         };
 751
 752         ipmmu_ds: mmu@e6740000 {
 753                 compatible = "renesas,ipmmu-vmsa";
 754                 reg = <0 0xe6740000 0 0x1000>;
 755                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 756                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
 757                 #iommu-cells = <1>;
 758         };
 759
 760         ipmmu_mp: mmu@ec680000 {
 761                 compatible = "renesas,ipmmu-vmsa";
 762                 reg = <0 0xec680000 0 0x1000>;
 763                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
 764                 #iommu-cells = <1>;
 765                 status = "disabled";
 766         };
 767
 768         ipmmu_mx: mmu@fe951000 {
 769                 compatible = "renesas,ipmmu-vmsa";
 770                 reg = <0 0xfe951000 0 0x1000>;
 771                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 772                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
 773                 #iommu-cells = <1>;
 774         };
 775
 776         ipmmu_gp: mmu@e62a0000 {
 777                 compatible = "renesas,ipmmu-vmsa";
 778                 reg = <0 0xe62a0000 0 0x1000>;
 779                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
 780                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
 781                 #iommu-cells = <1>;
 782                 status = "disabled";
 783         };
 784 };