2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1500000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1500000000>;
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,cortex-a15-gic";
74 #interrupt-cells = <3>;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
84 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
86 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
96 gpio1: gpio@e6051000 {
97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
98 reg = <0 0xe6051000 0 0x50>;
99 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
102 gpio-ranges = <&pfc 0 32 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
108 gpio2: gpio@e6052000 {
109 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
110 reg = <0 0xe6052000 0 0x50>;
111 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
114 gpio-ranges = <&pfc 0 64 32>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
120 gpio3: gpio@e6053000 {
121 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
122 reg = <0 0xe6053000 0 0x50>;
123 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
132 gpio4: gpio@e6054000 {
133 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
134 reg = <0 0xe6054000 0 0x50>;
135 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
138 gpio-ranges = <&pfc 0 128 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
144 gpio5: gpio@e6055000 {
145 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
146 reg = <0 0xe6055000 0 0x50>;
147 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
150 gpio-ranges = <&pfc 0 160 32>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
156 gpio6: gpio@e6055400 {
157 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
158 reg = <0 0xe6055400 0 0x50>;
159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
162 gpio-ranges = <&pfc 0 192 32>;
163 #interrupt-cells = <2>;
164 interrupt-controller;
165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
168 gpio7: gpio@e6055800 {
169 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
170 reg = <0 0xe6055800 0 0x50>;
171 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
174 gpio-ranges = <&pfc 0 224 26>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
181 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
182 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
183 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
188 compatible = "arm,armv7-timer";
189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
195 cmt0: timer@ffca0000 {
196 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
197 reg = <0 0xffca0000 0 0x1004>;
198 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
199 <0 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
203 renesas,channels-mask = <0x60>;
208 cmt1: timer@e6130000 {
209 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
210 reg = <0 0xe6130000 0 0x1004>;
211 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
212 <0 121 IRQ_TYPE_LEVEL_HIGH>,
213 <0 122 IRQ_TYPE_LEVEL_HIGH>,
214 <0 123 IRQ_TYPE_LEVEL_HIGH>,
215 <0 124 IRQ_TYPE_LEVEL_HIGH>,
216 <0 125 IRQ_TYPE_LEVEL_HIGH>,
217 <0 126 IRQ_TYPE_LEVEL_HIGH>,
218 <0 127 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
222 renesas,channels-mask = <0xff>;
227 irqc0: interrupt-controller@e61c0000 {
228 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
232 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
233 <0 1 IRQ_TYPE_LEVEL_HIGH>,
234 <0 2 IRQ_TYPE_LEVEL_HIGH>,
235 <0 3 IRQ_TYPE_LEVEL_HIGH>,
236 <0 12 IRQ_TYPE_LEVEL_HIGH>,
237 <0 13 IRQ_TYPE_LEVEL_HIGH>,
238 <0 14 IRQ_TYPE_LEVEL_HIGH>,
239 <0 15 IRQ_TYPE_LEVEL_HIGH>,
240 <0 16 IRQ_TYPE_LEVEL_HIGH>,
241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
244 dmac0: dma-controller@e6700000 {
245 compatible = "renesas,rcar-dmac";
246 reg = <0 0xe6700000 0 0x20000>;
247 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
248 0 200 IRQ_TYPE_LEVEL_HIGH
249 0 201 IRQ_TYPE_LEVEL_HIGH
250 0 202 IRQ_TYPE_LEVEL_HIGH
251 0 203 IRQ_TYPE_LEVEL_HIGH
252 0 204 IRQ_TYPE_LEVEL_HIGH
253 0 205 IRQ_TYPE_LEVEL_HIGH
254 0 206 IRQ_TYPE_LEVEL_HIGH
255 0 207 IRQ_TYPE_LEVEL_HIGH
256 0 208 IRQ_TYPE_LEVEL_HIGH
257 0 209 IRQ_TYPE_LEVEL_HIGH
258 0 210 IRQ_TYPE_LEVEL_HIGH
259 0 211 IRQ_TYPE_LEVEL_HIGH
260 0 212 IRQ_TYPE_LEVEL_HIGH
261 0 213 IRQ_TYPE_LEVEL_HIGH
262 0 214 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "error",
264 "ch0", "ch1", "ch2", "ch3",
265 "ch4", "ch5", "ch6", "ch7",
266 "ch8", "ch9", "ch10", "ch11",
267 "ch12", "ch13", "ch14";
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
274 dmac1: dma-controller@e6720000 {
275 compatible = "renesas,rcar-dmac";
276 reg = <0 0xe6720000 0 0x20000>;
277 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
278 0 216 IRQ_TYPE_LEVEL_HIGH
279 0 217 IRQ_TYPE_LEVEL_HIGH
280 0 218 IRQ_TYPE_LEVEL_HIGH
281 0 219 IRQ_TYPE_LEVEL_HIGH
282 0 308 IRQ_TYPE_LEVEL_HIGH
283 0 309 IRQ_TYPE_LEVEL_HIGH
284 0 310 IRQ_TYPE_LEVEL_HIGH
285 0 311 IRQ_TYPE_LEVEL_HIGH
286 0 312 IRQ_TYPE_LEVEL_HIGH
287 0 313 IRQ_TYPE_LEVEL_HIGH
288 0 314 IRQ_TYPE_LEVEL_HIGH
289 0 315 IRQ_TYPE_LEVEL_HIGH
290 0 316 IRQ_TYPE_LEVEL_HIGH
291 0 317 IRQ_TYPE_LEVEL_HIGH
292 0 318 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
304 /* The memory map in the User's Manual maps the cores to bus numbers */
306 #address-cells = <1>;
308 compatible = "renesas,i2c-r8a7791";
309 reg = <0 0xe6508000 0 0x40>;
310 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
316 #address-cells = <1>;
318 compatible = "renesas,i2c-r8a7791";
319 reg = <0 0xe6518000 0 0x40>;
320 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
326 #address-cells = <1>;
328 compatible = "renesas,i2c-r8a7791";
329 reg = <0 0xe6530000 0 0x40>;
330 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
336 #address-cells = <1>;
338 compatible = "renesas,i2c-r8a7791";
339 reg = <0 0xe6540000 0 0x40>;
340 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
346 #address-cells = <1>;
348 compatible = "renesas,i2c-r8a7791";
349 reg = <0 0xe6520000 0 0x40>;
350 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
356 /* doesn't need pinmux */
357 #address-cells = <1>;
359 compatible = "renesas,i2c-r8a7791";
360 reg = <0 0xe6528000 0 0x40>;
361 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
367 /* doesn't need pinmux */
368 #address-cells = <1>;
370 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
371 reg = <0 0xe60b0000 0 0x425>;
372 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
378 #address-cells = <1>;
380 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
381 reg = <0 0xe6500000 0 0x425>;
382 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
388 #address-cells = <1>;
390 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
391 reg = <0 0xe6510000 0 0x425>;
392 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
398 compatible = "renesas,pfc-r8a7791";
399 reg = <0 0xe6060000 0 0x250>;
400 #gpio-range-cells = <3>;
403 mmcif0: mmc@ee200000 {
404 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
405 reg = <0 0xee200000 0 0x80>;
406 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
408 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
409 dma-names = "tx", "rx";
415 compatible = "renesas,sdhi-r8a7791";
416 reg = <0 0xee100000 0 0x200>;
417 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
423 compatible = "renesas,sdhi-r8a7791";
424 reg = <0 0xee140000 0 0x100>;
425 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
431 compatible = "renesas,sdhi-r8a7791";
432 reg = <0 0xee160000 0 0x100>;
433 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
438 scifa0: serial@e6c40000 {
439 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
440 reg = <0 0xe6c40000 0 64>;
441 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
443 clock-names = "sci_ick";
447 scifa1: serial@e6c50000 {
448 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
449 reg = <0 0xe6c50000 0 64>;
450 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
452 clock-names = "sci_ick";
456 scifa2: serial@e6c60000 {
457 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
458 reg = <0 0xe6c60000 0 64>;
459 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
461 clock-names = "sci_ick";
465 scifa3: serial@e6c70000 {
466 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
467 reg = <0 0xe6c70000 0 64>;
468 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
470 clock-names = "sci_ick";
474 scifa4: serial@e6c78000 {
475 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
476 reg = <0 0xe6c78000 0 64>;
477 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
479 clock-names = "sci_ick";
483 scifa5: serial@e6c80000 {
484 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
485 reg = <0 0xe6c80000 0 64>;
486 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
488 clock-names = "sci_ick";
492 scifb0: serial@e6c20000 {
493 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
494 reg = <0 0xe6c20000 0 64>;
495 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
497 clock-names = "sci_ick";
501 scifb1: serial@e6c30000 {
502 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
503 reg = <0 0xe6c30000 0 64>;
504 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
506 clock-names = "sci_ick";
510 scifb2: serial@e6ce0000 {
511 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
512 reg = <0 0xe6ce0000 0 64>;
513 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
515 clock-names = "sci_ick";
519 scif0: serial@e6e60000 {
520 compatible = "renesas,scif-r8a7791", "renesas,scif";
521 reg = <0 0xe6e60000 0 64>;
522 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
524 clock-names = "sci_ick";
528 scif1: serial@e6e68000 {
529 compatible = "renesas,scif-r8a7791", "renesas,scif";
530 reg = <0 0xe6e68000 0 64>;
531 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
533 clock-names = "sci_ick";
537 scif2: serial@e6e58000 {
538 compatible = "renesas,scif-r8a7791", "renesas,scif";
539 reg = <0 0xe6e58000 0 64>;
540 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
542 clock-names = "sci_ick";
546 scif3: serial@e6ea8000 {
547 compatible = "renesas,scif-r8a7791", "renesas,scif";
548 reg = <0 0xe6ea8000 0 64>;
549 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
551 clock-names = "sci_ick";
555 scif4: serial@e6ee0000 {
556 compatible = "renesas,scif-r8a7791", "renesas,scif";
557 reg = <0 0xe6ee0000 0 64>;
558 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
560 clock-names = "sci_ick";
564 scif5: serial@e6ee8000 {
565 compatible = "renesas,scif-r8a7791", "renesas,scif";
566 reg = <0 0xe6ee8000 0 64>;
567 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
569 clock-names = "sci_ick";
573 hscif0: serial@e62c0000 {
574 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
575 reg = <0 0xe62c0000 0 96>;
576 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
578 clock-names = "sci_ick";
582 hscif1: serial@e62c8000 {
583 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
584 reg = <0 0xe62c8000 0 96>;
585 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
587 clock-names = "sci_ick";
591 hscif2: serial@e62d0000 {
592 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
593 reg = <0 0xe62d0000 0 96>;
594 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
596 clock-names = "sci_ick";
600 ether: ethernet@ee700000 {
601 compatible = "renesas,ether-r8a7791";
602 reg = <0 0xee700000 0 0x400>;
603 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
606 #address-cells = <1>;
611 sata0: sata@ee300000 {
612 compatible = "renesas,sata-r8a7791";
613 reg = <0 0xee300000 0 0x2000>;
614 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
619 sata1: sata@ee500000 {
620 compatible = "renesas,sata-r8a7791";
621 reg = <0 0xee500000 0 0x2000>;
622 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
627 hsusb: usb@e6590000 {
628 compatible = "renesas,usbhs-r8a7791";
629 reg = <0 0xe6590000 0 0x100>;
630 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
632 renesas,buswait = <4>;
638 usbphy: usb-phy@e6590100 {
639 compatible = "renesas,usb-phy-r8a7791";
640 reg = <0 0xe6590100 0 0x100>;
641 #address-cells = <1>;
643 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
644 clock-names = "usbhs";
647 usb0: usb-channel@0 {
651 usb2: usb-channel@2 {
657 vin0: video@e6ef0000 {
658 compatible = "renesas,vin-r8a7791";
659 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
660 reg = <0 0xe6ef0000 0 0x1000>;
661 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
665 vin1: video@e6ef1000 {
666 compatible = "renesas,vin-r8a7791";
667 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
668 reg = <0 0xe6ef1000 0 0x1000>;
669 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
673 vin2: video@e6ef2000 {
674 compatible = "renesas,vin-r8a7791";
675 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
676 reg = <0 0xe6ef2000 0 0x1000>;
677 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
682 compatible = "renesas,vsp1";
683 reg = <0 0xfe928000 0 0x8000>;
684 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
695 compatible = "renesas,vsp1";
696 reg = <0 0xfe930000 0 0x8000>;
697 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
708 compatible = "renesas,vsp1";
709 reg = <0 0xfe938000 0 0x8000>;
710 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
720 du: display@feb00000 {
721 compatible = "renesas,du-r8a7791";
722 reg = <0 0xfeb00000 0 0x40000>,
723 <0 0xfeb90000 0 0x1c>;
724 reg-names = "du", "lvds.0";
725 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
726 <0 268 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
728 <&mstp7_clks R8A7791_CLK_DU1>,
729 <&mstp7_clks R8A7791_CLK_LVDS0>;
730 clock-names = "du.0", "du.1", "lvds.0";
734 #address-cells = <1>;
739 du_out_rgb: endpoint {
744 du_out_lvds0: endpoint {
751 #address-cells = <2>;
755 /* External root clock */
756 extal_clk: extal_clk {
757 compatible = "fixed-clock";
759 /* This value must be overriden by the board. */
760 clock-frequency = <0>;
761 clock-output-names = "extal";
765 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
766 * default. Boards that provide audio clocks should override them.
768 audio_clk_a: audio_clk_a {
769 compatible = "fixed-clock";
771 clock-frequency = <0>;
772 clock-output-names = "audio_clk_a";
774 audio_clk_b: audio_clk_b {
775 compatible = "fixed-clock";
777 clock-frequency = <0>;
778 clock-output-names = "audio_clk_b";
780 audio_clk_c: audio_clk_c {
781 compatible = "fixed-clock";
783 clock-frequency = <0>;
784 clock-output-names = "audio_clk_c";
787 /* External PCIe clock - can be overridden by the board */
788 pcie_bus_clk: pcie_bus_clk {
789 compatible = "fixed-clock";
791 clock-frequency = <100000000>;
792 clock-output-names = "pcie_bus";
796 /* Special CPG clocks */
797 cpg_clocks: cpg_clocks@e6150000 {
798 compatible = "renesas,r8a7791-cpg-clocks",
799 "renesas,rcar-gen2-cpg-clocks";
800 reg = <0 0xe6150000 0 0x1000>;
801 clocks = <&extal_clk>;
803 clock-output-names = "main", "pll0", "pll1", "pll3",
804 "lb", "qspi", "sdh", "sd0", "z";
807 /* Variable factor clocks */
808 sd1_clk: sd2_clk@e6150078 {
809 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
810 reg = <0 0xe6150078 0 4>;
811 clocks = <&pll1_div2_clk>;
813 clock-output-names = "sd1";
815 sd2_clk: sd3_clk@e615026c {
816 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
817 reg = <0 0xe615026c 0 4>;
818 clocks = <&pll1_div2_clk>;
820 clock-output-names = "sd2";
822 mmc0_clk: mmc0_clk@e6150240 {
823 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
824 reg = <0 0xe6150240 0 4>;
825 clocks = <&pll1_div2_clk>;
827 clock-output-names = "mmc0";
829 ssp_clk: ssp_clk@e6150248 {
830 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
831 reg = <0 0xe6150248 0 4>;
832 clocks = <&pll1_div2_clk>;
834 clock-output-names = "ssp";
836 ssprs_clk: ssprs_clk@e615024c {
837 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
838 reg = <0 0xe615024c 0 4>;
839 clocks = <&pll1_div2_clk>;
841 clock-output-names = "ssprs";
844 /* Fixed factor clocks */
845 pll1_div2_clk: pll1_div2_clk {
846 compatible = "fixed-factor-clock";
847 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
851 clock-output-names = "pll1_div2";
854 compatible = "fixed-factor-clock";
855 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
859 clock-output-names = "zg";
862 compatible = "fixed-factor-clock";
863 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
867 clock-output-names = "zx";
870 compatible = "fixed-factor-clock";
871 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
875 clock-output-names = "zs";
878 compatible = "fixed-factor-clock";
879 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
883 clock-output-names = "hp";
886 compatible = "fixed-factor-clock";
887 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
891 clock-output-names = "i";
894 compatible = "fixed-factor-clock";
895 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
899 clock-output-names = "b";
902 compatible = "fixed-factor-clock";
903 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
907 clock-output-names = "p";
910 compatible = "fixed-factor-clock";
911 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
915 clock-output-names = "cl";
918 compatible = "fixed-factor-clock";
919 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
923 clock-output-names = "m2";
926 compatible = "fixed-factor-clock";
927 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
931 clock-output-names = "imp";
934 compatible = "fixed-factor-clock";
935 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
937 clock-div = <(48 * 1024)>;
939 clock-output-names = "rclk";
941 oscclk_clk: oscclk_clk {
942 compatible = "fixed-factor-clock";
943 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
945 clock-div = <(12 * 1024)>;
947 clock-output-names = "oscclk";
950 compatible = "fixed-factor-clock";
951 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
955 clock-output-names = "zb3";
957 zb3d2_clk: zb3d2_clk {
958 compatible = "fixed-factor-clock";
959 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
963 clock-output-names = "zb3d2";
966 compatible = "fixed-factor-clock";
967 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
971 clock-output-names = "ddr";
974 compatible = "fixed-factor-clock";
975 clocks = <&pll1_div2_clk>;
979 clock-output-names = "mp";
982 compatible = "fixed-factor-clock";
983 clocks = <&extal_clk>;
987 clock-output-names = "cp";
991 mstp0_clks: mstp0_clks@e6150130 {
992 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
993 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
996 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
997 clock-output-names = "msiof0";
999 mstp1_clks: mstp1_clks@e6150134 {
1000 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1001 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1002 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1003 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1004 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1007 renesas,clock-indices = <
1008 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1009 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1010 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1011 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1012 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1015 clock-output-names =
1016 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1017 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1018 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1020 mstp2_clks: mstp2_clks@e6150138 {
1021 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1022 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1023 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1024 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1025 <&zs_clk>, <&zs_clk>;
1027 renesas,clock-indices = <
1028 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1029 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1030 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1031 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1033 clock-output-names =
1034 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1035 "scifb1", "msiof1", "scifb2",
1036 "sys-dmac1", "sys-dmac0";
1038 mstp3_clks: mstp3_clks@e615013c {
1039 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1040 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1041 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1042 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
1044 renesas,clock-indices = <
1045 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1046 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1047 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1049 clock-output-names =
1050 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1051 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
1053 mstp5_clks: mstp5_clks@e6150144 {
1054 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1055 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1056 clocks = <&extal_clk>, <&p_clk>;
1058 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
1059 clock-output-names = "thermal", "pwm";
1061 mstp7_clks: mstp7_clks@e615014c {
1062 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1063 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1064 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1065 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1066 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1068 renesas,clock-indices = <
1069 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1070 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1071 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1072 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1075 clock-output-names =
1076 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1077 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1079 mstp8_clks: mstp8_clks@e6150990 {
1080 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1081 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1082 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
1085 renesas,clock-indices = <
1086 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1087 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1089 clock-output-names =
1090 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
1092 mstp9_clks: mstp9_clks@e6150994 {
1093 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1094 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1095 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1096 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1097 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1098 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1099 <&hp_clk>, <&hp_clk>;
1101 renesas,clock-indices = <
1102 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1103 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1104 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1105 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1106 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1108 clock-output-names =
1109 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1110 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1113 mstp10_clks: mstp10_clks@e6150998 {
1114 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1115 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1117 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1118 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1120 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1121 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1122 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1123 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1124 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1125 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1130 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1131 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1133 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1134 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1135 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1137 clock-output-names =
1139 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1140 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1142 "scu-dvc1", "scu-dvc0",
1143 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1144 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1146 mstp11_clks: mstp11_clks@e615099c {
1147 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1148 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1149 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1151 renesas,clock-indices = <
1152 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1154 clock-output-names = "scifa3", "scifa4", "scifa5";
1158 qspi: spi@e6b10000 {
1159 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1160 reg = <0 0xe6b10000 0 0x2c>;
1161 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1163 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1164 dma-names = "tx", "rx";
1166 #address-cells = <1>;
1168 status = "disabled";
1171 msiof0: spi@e6e20000 {
1172 compatible = "renesas,msiof-r8a7791";
1173 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1174 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1176 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1177 dma-names = "tx", "rx";
1178 #address-cells = <1>;
1180 status = "disabled";
1183 msiof1: spi@e6e10000 {
1184 compatible = "renesas,msiof-r8a7791";
1185 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1186 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1188 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1189 dma-names = "tx", "rx";
1190 #address-cells = <1>;
1192 status = "disabled";
1195 msiof2: spi@e6e00000 {
1196 compatible = "renesas,msiof-r8a7791";
1197 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1198 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1200 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1201 dma-names = "tx", "rx";
1202 #address-cells = <1>;
1204 status = "disabled";
1207 xhci: usb@ee000000 {
1208 compatible = "renesas,xhci-r8a7791";
1209 reg = <0 0xee000000 0 0xc00>;
1210 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1211 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1214 status = "disabled";
1217 pci0: pci@ee090000 {
1218 compatible = "renesas,pci-r8a7791";
1219 device_type = "pci";
1220 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1221 reg = <0 0xee090000 0 0xc00>,
1222 <0 0xee080000 0 0x1100>;
1223 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1224 status = "disabled";
1227 #address-cells = <3>;
1229 #interrupt-cells = <1>;
1230 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1231 interrupt-map-mask = <0xff00 0 0 0x7>;
1232 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1233 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1234 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1237 reg = <0x800 0 0 0 0>;
1238 device_type = "pci";
1244 reg = <0x1000 0 0 0 0>;
1245 device_type = "pci";
1251 pci1: pci@ee0d0000 {
1252 compatible = "renesas,pci-r8a7791";
1253 device_type = "pci";
1254 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1255 reg = <0 0xee0d0000 0 0xc00>,
1256 <0 0xee0c0000 0 0x1100>;
1257 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1258 status = "disabled";
1261 #address-cells = <3>;
1263 #interrupt-cells = <1>;
1264 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1265 interrupt-map-mask = <0xff00 0 0 0x7>;
1266 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1267 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1268 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1271 reg = <0x800 0 0 0 0>;
1272 device_type = "pci";
1278 reg = <0x1000 0 0 0 0>;
1279 device_type = "pci";
1285 pciec: pcie@fe000000 {
1286 compatible = "renesas,pcie-r8a7791";
1287 reg = <0 0xfe000000 0 0x80000>;
1288 #address-cells = <3>;
1290 bus-range = <0x00 0xff>;
1291 device_type = "pci";
1292 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1293 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1294 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1295 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1296 /* Map all possible DDR as inbound ranges */
1297 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1298 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1299 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1300 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1301 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1302 #interrupt-cells = <1>;
1303 interrupt-map-mask = <0 0 0 0>;
1304 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1306 clock-names = "pcie", "pcie_bus";
1307 status = "disabled";
1310 rcar_sound: rcar_sound@ec500000 {
1311 #sound-dai-cells = <1>;
1312 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1313 reg = <0 0xec500000 0 0x1000>, /* SCU */
1314 <0 0xec5a0000 0 0x100>, /* ADG */
1315 <0 0xec540000 0 0x1000>, /* SSIU */
1316 <0 0xec541000 0 0x1280>; /* SSI */
1317 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1318 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1319 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1320 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1321 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1322 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1323 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1324 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1325 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1326 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1327 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1328 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1329 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1330 clock-names = "ssi-all",
1331 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1332 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1333 "src.9", "src.8", "src.7", "src.6", "src.5",
1334 "src.4", "src.3", "src.2", "src.1", "src.0",
1336 "clk_a", "clk_b", "clk_c", "clk_i";
1338 status = "disabled";
1359 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1360 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1361 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1362 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1363 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1364 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1365 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1366 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1367 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1368 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };