2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1500000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1500000000>;
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,cortex-a15-gic";
74 #interrupt-cells = <3>;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
84 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
86 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
96 gpio1: gpio@e6051000 {
97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
98 reg = <0 0xe6051000 0 0x50>;
99 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
102 gpio-ranges = <&pfc 0 32 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
108 gpio2: gpio@e6052000 {
109 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
110 reg = <0 0xe6052000 0 0x50>;
111 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
114 gpio-ranges = <&pfc 0 64 32>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
120 gpio3: gpio@e6053000 {
121 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
122 reg = <0 0xe6053000 0 0x50>;
123 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
132 gpio4: gpio@e6054000 {
133 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
134 reg = <0 0xe6054000 0 0x50>;
135 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
138 gpio-ranges = <&pfc 0 128 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
144 gpio5: gpio@e6055000 {
145 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
146 reg = <0 0xe6055000 0 0x50>;
147 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
150 gpio-ranges = <&pfc 0 160 32>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
156 gpio6: gpio@e6055400 {
157 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
158 reg = <0 0xe6055400 0 0x50>;
159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
162 gpio-ranges = <&pfc 0 192 32>;
163 #interrupt-cells = <2>;
164 interrupt-controller;
165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
168 gpio7: gpio@e6055800 {
169 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
170 reg = <0 0xe6055800 0 0x50>;
171 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
174 gpio-ranges = <&pfc 0 224 26>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
181 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
182 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
183 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
188 compatible = "arm,armv7-timer";
189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
195 cmt0: timer@ffca0000 {
196 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
197 reg = <0 0xffca0000 0 0x1004>;
198 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
199 <0 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
203 renesas,channels-mask = <0x60>;
208 cmt1: timer@e6130000 {
209 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
210 reg = <0 0xe6130000 0 0x1004>;
211 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
212 <0 121 IRQ_TYPE_LEVEL_HIGH>,
213 <0 122 IRQ_TYPE_LEVEL_HIGH>,
214 <0 123 IRQ_TYPE_LEVEL_HIGH>,
215 <0 124 IRQ_TYPE_LEVEL_HIGH>,
216 <0 125 IRQ_TYPE_LEVEL_HIGH>,
217 <0 126 IRQ_TYPE_LEVEL_HIGH>,
218 <0 127 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
222 renesas,channels-mask = <0xff>;
227 irqc0: interrupt-controller@e61c0000 {
228 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
232 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
233 <0 1 IRQ_TYPE_LEVEL_HIGH>,
234 <0 2 IRQ_TYPE_LEVEL_HIGH>,
235 <0 3 IRQ_TYPE_LEVEL_HIGH>,
236 <0 12 IRQ_TYPE_LEVEL_HIGH>,
237 <0 13 IRQ_TYPE_LEVEL_HIGH>,
238 <0 14 IRQ_TYPE_LEVEL_HIGH>,
239 <0 15 IRQ_TYPE_LEVEL_HIGH>,
240 <0 16 IRQ_TYPE_LEVEL_HIGH>,
241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
244 dmac0: dma-controller@e6700000 {
245 compatible = "renesas,rcar-dmac";
246 reg = <0 0xe6700000 0 0x20000>;
247 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
248 0 200 IRQ_TYPE_LEVEL_HIGH
249 0 201 IRQ_TYPE_LEVEL_HIGH
250 0 202 IRQ_TYPE_LEVEL_HIGH
251 0 203 IRQ_TYPE_LEVEL_HIGH
252 0 204 IRQ_TYPE_LEVEL_HIGH
253 0 205 IRQ_TYPE_LEVEL_HIGH
254 0 206 IRQ_TYPE_LEVEL_HIGH
255 0 207 IRQ_TYPE_LEVEL_HIGH
256 0 208 IRQ_TYPE_LEVEL_HIGH
257 0 209 IRQ_TYPE_LEVEL_HIGH
258 0 210 IRQ_TYPE_LEVEL_HIGH
259 0 211 IRQ_TYPE_LEVEL_HIGH
260 0 212 IRQ_TYPE_LEVEL_HIGH
261 0 213 IRQ_TYPE_LEVEL_HIGH
262 0 214 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "error",
264 "ch0", "ch1", "ch2", "ch3",
265 "ch4", "ch5", "ch6", "ch7",
266 "ch8", "ch9", "ch10", "ch11",
267 "ch12", "ch13", "ch14";
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
274 dmac1: dma-controller@e6720000 {
275 compatible = "renesas,rcar-dmac";
276 reg = <0 0xe6720000 0 0x20000>;
277 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
278 0 216 IRQ_TYPE_LEVEL_HIGH
279 0 217 IRQ_TYPE_LEVEL_HIGH
280 0 218 IRQ_TYPE_LEVEL_HIGH
281 0 219 IRQ_TYPE_LEVEL_HIGH
282 0 308 IRQ_TYPE_LEVEL_HIGH
283 0 309 IRQ_TYPE_LEVEL_HIGH
284 0 310 IRQ_TYPE_LEVEL_HIGH
285 0 311 IRQ_TYPE_LEVEL_HIGH
286 0 312 IRQ_TYPE_LEVEL_HIGH
287 0 313 IRQ_TYPE_LEVEL_HIGH
288 0 314 IRQ_TYPE_LEVEL_HIGH
289 0 315 IRQ_TYPE_LEVEL_HIGH
290 0 316 IRQ_TYPE_LEVEL_HIGH
291 0 317 IRQ_TYPE_LEVEL_HIGH
292 0 318 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
304 /* The memory map in the User's Manual maps the cores to bus numbers */
306 #address-cells = <1>;
308 compatible = "renesas,i2c-r8a7791";
309 reg = <0 0xe6508000 0 0x40>;
310 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
316 #address-cells = <1>;
318 compatible = "renesas,i2c-r8a7791";
319 reg = <0 0xe6518000 0 0x40>;
320 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
326 #address-cells = <1>;
328 compatible = "renesas,i2c-r8a7791";
329 reg = <0 0xe6530000 0 0x40>;
330 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
336 #address-cells = <1>;
338 compatible = "renesas,i2c-r8a7791";
339 reg = <0 0xe6540000 0 0x40>;
340 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
346 #address-cells = <1>;
348 compatible = "renesas,i2c-r8a7791";
349 reg = <0 0xe6520000 0 0x40>;
350 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
356 /* doesn't need pinmux */
357 #address-cells = <1>;
359 compatible = "renesas,i2c-r8a7791";
360 reg = <0 0xe6528000 0 0x40>;
361 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
367 /* doesn't need pinmux */
368 #address-cells = <1>;
370 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
371 reg = <0 0xe60b0000 0 0x425>;
372 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
378 #address-cells = <1>;
380 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
381 reg = <0 0xe6500000 0 0x425>;
382 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
388 #address-cells = <1>;
390 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
391 reg = <0 0xe6510000 0 0x425>;
392 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
398 compatible = "renesas,pfc-r8a7791";
399 reg = <0 0xe6060000 0 0x250>;
400 #gpio-range-cells = <3>;
404 compatible = "renesas,sdhi-r8a7791";
405 reg = <0 0xee100000 0 0x200>;
406 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
412 compatible = "renesas,sdhi-r8a7791";
413 reg = <0 0xee140000 0 0x100>;
414 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
420 compatible = "renesas,sdhi-r8a7791";
421 reg = <0 0xee160000 0 0x100>;
422 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
427 scifa0: serial@e6c40000 {
428 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
429 reg = <0 0xe6c40000 0 64>;
430 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
432 clock-names = "sci_ick";
436 scifa1: serial@e6c50000 {
437 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
438 reg = <0 0xe6c50000 0 64>;
439 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
441 clock-names = "sci_ick";
445 scifa2: serial@e6c60000 {
446 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
447 reg = <0 0xe6c60000 0 64>;
448 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
450 clock-names = "sci_ick";
454 scifa3: serial@e6c70000 {
455 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
456 reg = <0 0xe6c70000 0 64>;
457 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
459 clock-names = "sci_ick";
463 scifa4: serial@e6c78000 {
464 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
465 reg = <0 0xe6c78000 0 64>;
466 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
468 clock-names = "sci_ick";
472 scifa5: serial@e6c80000 {
473 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
474 reg = <0 0xe6c80000 0 64>;
475 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
477 clock-names = "sci_ick";
481 scifb0: serial@e6c20000 {
482 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
483 reg = <0 0xe6c20000 0 64>;
484 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
486 clock-names = "sci_ick";
490 scifb1: serial@e6c30000 {
491 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
492 reg = <0 0xe6c30000 0 64>;
493 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
495 clock-names = "sci_ick";
499 scifb2: serial@e6ce0000 {
500 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
501 reg = <0 0xe6ce0000 0 64>;
502 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
504 clock-names = "sci_ick";
508 scif0: serial@e6e60000 {
509 compatible = "renesas,scif-r8a7791", "renesas,scif";
510 reg = <0 0xe6e60000 0 64>;
511 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
513 clock-names = "sci_ick";
517 scif1: serial@e6e68000 {
518 compatible = "renesas,scif-r8a7791", "renesas,scif";
519 reg = <0 0xe6e68000 0 64>;
520 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
522 clock-names = "sci_ick";
526 scif2: serial@e6e58000 {
527 compatible = "renesas,scif-r8a7791", "renesas,scif";
528 reg = <0 0xe6e58000 0 64>;
529 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
531 clock-names = "sci_ick";
535 scif3: serial@e6ea8000 {
536 compatible = "renesas,scif-r8a7791", "renesas,scif";
537 reg = <0 0xe6ea8000 0 64>;
538 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
540 clock-names = "sci_ick";
544 scif4: serial@e6ee0000 {
545 compatible = "renesas,scif-r8a7791", "renesas,scif";
546 reg = <0 0xe6ee0000 0 64>;
547 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
549 clock-names = "sci_ick";
553 scif5: serial@e6ee8000 {
554 compatible = "renesas,scif-r8a7791", "renesas,scif";
555 reg = <0 0xe6ee8000 0 64>;
556 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
558 clock-names = "sci_ick";
562 hscif0: serial@e62c0000 {
563 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
564 reg = <0 0xe62c0000 0 96>;
565 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
567 clock-names = "sci_ick";
571 hscif1: serial@e62c8000 {
572 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
573 reg = <0 0xe62c8000 0 96>;
574 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
576 clock-names = "sci_ick";
580 hscif2: serial@e62d0000 {
581 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
582 reg = <0 0xe62d0000 0 96>;
583 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
585 clock-names = "sci_ick";
589 ether: ethernet@ee700000 {
590 compatible = "renesas,ether-r8a7791";
591 reg = <0 0xee700000 0 0x400>;
592 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
595 #address-cells = <1>;
600 sata0: sata@ee300000 {
601 compatible = "renesas,sata-r8a7791";
602 reg = <0 0xee300000 0 0x2000>;
603 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
608 sata1: sata@ee500000 {
609 compatible = "renesas,sata-r8a7791";
610 reg = <0 0xee500000 0 0x2000>;
611 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
616 vin0: video@e6ef0000 {
617 compatible = "renesas,vin-r8a7791";
618 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
619 reg = <0 0xe6ef0000 0 0x1000>;
620 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
624 vin1: video@e6ef1000 {
625 compatible = "renesas,vin-r8a7791";
626 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
627 reg = <0 0xe6ef1000 0 0x1000>;
628 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
632 vin2: video@e6ef2000 {
633 compatible = "renesas,vin-r8a7791";
634 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
635 reg = <0 0xe6ef2000 0 0x1000>;
636 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <2>;
645 /* External root clock */
646 extal_clk: extal_clk {
647 compatible = "fixed-clock";
649 /* This value must be overriden by the board. */
650 clock-frequency = <0>;
651 clock-output-names = "extal";
655 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
656 * default. Boards that provide audio clocks should override them.
658 audio_clk_a: audio_clk_a {
659 compatible = "fixed-clock";
661 clock-frequency = <0>;
662 clock-output-names = "audio_clk_a";
664 audio_clk_b: audio_clk_b {
665 compatible = "fixed-clock";
667 clock-frequency = <0>;
668 clock-output-names = "audio_clk_b";
670 audio_clk_c: audio_clk_c {
671 compatible = "fixed-clock";
673 clock-frequency = <0>;
674 clock-output-names = "audio_clk_c";
677 /* External PCIe clock - can be overridden by the board */
678 pcie_bus_clk: pcie_bus_clk {
679 compatible = "fixed-clock";
681 clock-frequency = <100000000>;
682 clock-output-names = "pcie_bus";
686 /* Special CPG clocks */
687 cpg_clocks: cpg_clocks@e6150000 {
688 compatible = "renesas,r8a7791-cpg-clocks",
689 "renesas,rcar-gen2-cpg-clocks";
690 reg = <0 0xe6150000 0 0x1000>;
691 clocks = <&extal_clk>;
693 clock-output-names = "main", "pll0", "pll1", "pll3",
694 "lb", "qspi", "sdh", "sd0", "z";
697 /* Variable factor clocks */
698 sd1_clk: sd2_clk@e6150078 {
699 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
700 reg = <0 0xe6150078 0 4>;
701 clocks = <&pll1_div2_clk>;
703 clock-output-names = "sd1";
705 sd2_clk: sd3_clk@e615026c {
706 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
707 reg = <0 0xe615026c 0 4>;
708 clocks = <&pll1_div2_clk>;
710 clock-output-names = "sd2";
712 mmc0_clk: mmc0_clk@e6150240 {
713 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
714 reg = <0 0xe6150240 0 4>;
715 clocks = <&pll1_div2_clk>;
717 clock-output-names = "mmc0";
719 ssp_clk: ssp_clk@e6150248 {
720 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
721 reg = <0 0xe6150248 0 4>;
722 clocks = <&pll1_div2_clk>;
724 clock-output-names = "ssp";
726 ssprs_clk: ssprs_clk@e615024c {
727 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
728 reg = <0 0xe615024c 0 4>;
729 clocks = <&pll1_div2_clk>;
731 clock-output-names = "ssprs";
734 /* Fixed factor clocks */
735 pll1_div2_clk: pll1_div2_clk {
736 compatible = "fixed-factor-clock";
737 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
741 clock-output-names = "pll1_div2";
744 compatible = "fixed-factor-clock";
745 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
749 clock-output-names = "zg";
752 compatible = "fixed-factor-clock";
753 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
757 clock-output-names = "zx";
760 compatible = "fixed-factor-clock";
761 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
765 clock-output-names = "zs";
768 compatible = "fixed-factor-clock";
769 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
773 clock-output-names = "hp";
776 compatible = "fixed-factor-clock";
777 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
781 clock-output-names = "i";
784 compatible = "fixed-factor-clock";
785 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
789 clock-output-names = "b";
792 compatible = "fixed-factor-clock";
793 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
797 clock-output-names = "p";
800 compatible = "fixed-factor-clock";
801 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
805 clock-output-names = "cl";
808 compatible = "fixed-factor-clock";
809 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
813 clock-output-names = "m2";
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
821 clock-output-names = "imp";
824 compatible = "fixed-factor-clock";
825 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
827 clock-div = <(48 * 1024)>;
829 clock-output-names = "rclk";
831 oscclk_clk: oscclk_clk {
832 compatible = "fixed-factor-clock";
833 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
835 clock-div = <(12 * 1024)>;
837 clock-output-names = "oscclk";
840 compatible = "fixed-factor-clock";
841 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
845 clock-output-names = "zb3";
847 zb3d2_clk: zb3d2_clk {
848 compatible = "fixed-factor-clock";
849 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
853 clock-output-names = "zb3d2";
856 compatible = "fixed-factor-clock";
857 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
861 clock-output-names = "ddr";
864 compatible = "fixed-factor-clock";
865 clocks = <&pll1_div2_clk>;
869 clock-output-names = "mp";
872 compatible = "fixed-factor-clock";
873 clocks = <&extal_clk>;
877 clock-output-names = "cp";
881 mstp0_clks: mstp0_clks@e6150130 {
882 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
883 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
886 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
887 clock-output-names = "msiof0";
889 mstp1_clks: mstp1_clks@e6150134 {
890 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
891 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
892 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
893 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
895 renesas,clock-indices = <
896 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
897 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
898 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
901 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
902 "vsp1-du0", "vsp1-sy";
904 mstp2_clks: mstp2_clks@e6150138 {
905 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
906 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
907 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
908 <&mp_clk>, <&mp_clk>, <&mp_clk>,
909 <&zs_clk>, <&zs_clk>;
911 renesas,clock-indices = <
912 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
913 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
914 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
915 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
918 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
919 "scifb1", "msiof1", "scifb2",
920 "sys-dmac1", "sys-dmac0";
922 mstp3_clks: mstp3_clks@e615013c {
923 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
924 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
925 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
926 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
928 renesas,clock-indices = <
929 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
930 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
931 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
934 "tpu0", "sdhi2", "sdhi1", "sdhi0",
935 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
937 mstp5_clks: mstp5_clks@e6150144 {
938 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
939 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
940 clocks = <&extal_clk>, <&p_clk>;
942 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
943 clock-output-names = "thermal", "pwm";
945 mstp7_clks: mstp7_clks@e615014c {
946 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
947 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
948 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
949 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
950 <&zx_clk>, <&zx_clk>, <&zx_clk>;
952 renesas,clock-indices = <
953 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
954 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
955 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
956 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
960 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
961 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
963 mstp8_clks: mstp8_clks@e6150990 {
964 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
965 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
966 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
969 renesas,clock-indices = <
970 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
971 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
974 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
976 mstp9_clks: mstp9_clks@e6150994 {
977 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
978 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
979 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
980 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
981 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
982 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
983 <&hp_clk>, <&hp_clk>;
985 renesas,clock-indices = <
986 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
987 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
988 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
989 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
990 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
993 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
994 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
997 mstp10_clks: mstp10_clks@e6150998 {
998 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
999 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1001 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1002 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1004 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1005 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1006 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1007 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1008 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1009 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1014 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1015 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1017 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1018 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1019 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1021 clock-output-names =
1023 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1024 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1026 "scu-dvc1", "scu-dvc0",
1027 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1028 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1030 mstp11_clks: mstp11_clks@e615099c {
1031 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1032 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1033 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1035 renesas,clock-indices = <
1036 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1038 clock-output-names = "scifa3", "scifa4", "scifa5";
1042 qspi: spi@e6b10000 {
1043 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1044 reg = <0 0xe6b10000 0 0x2c>;
1045 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1047 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1048 dma-names = "tx", "rx";
1050 #address-cells = <1>;
1052 status = "disabled";
1055 msiof0: spi@e6e20000 {
1056 compatible = "renesas,msiof-r8a7791";
1057 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1058 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1060 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1061 dma-names = "tx", "rx";
1062 #address-cells = <1>;
1064 status = "disabled";
1067 msiof1: spi@e6e10000 {
1068 compatible = "renesas,msiof-r8a7791";
1069 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1070 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1072 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1073 dma-names = "tx", "rx";
1074 #address-cells = <1>;
1076 status = "disabled";
1079 msiof2: spi@e6e00000 {
1080 compatible = "renesas,msiof-r8a7791";
1081 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1082 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1084 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1085 dma-names = "tx", "rx";
1086 #address-cells = <1>;
1088 status = "disabled";
1091 pci0: pci@ee090000 {
1092 compatible = "renesas,pci-r8a7791";
1093 device_type = "pci";
1094 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1095 reg = <0 0xee090000 0 0xc00>,
1096 <0 0xee080000 0 0x1100>;
1097 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1098 status = "disabled";
1101 #address-cells = <3>;
1103 #interrupt-cells = <1>;
1104 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1105 interrupt-map-mask = <0xff00 0 0 0x7>;
1106 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1107 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1108 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1111 pci1: pci@ee0d0000 {
1112 compatible = "renesas,pci-r8a7791";
1113 device_type = "pci";
1114 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1115 reg = <0 0xee0d0000 0 0xc00>,
1116 <0 0xee0c0000 0 0x1100>;
1117 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1118 status = "disabled";
1121 #address-cells = <3>;
1123 #interrupt-cells = <1>;
1124 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1125 interrupt-map-mask = <0xff00 0 0 0x7>;
1126 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1127 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1128 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1131 pciec: pcie@fe000000 {
1132 compatible = "renesas,pcie-r8a7791";
1133 reg = <0 0xfe000000 0 0x80000>;
1134 #address-cells = <3>;
1136 bus-range = <0x00 0xff>;
1137 device_type = "pci";
1138 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1139 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1140 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1141 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1142 /* Map all possible DDR as inbound ranges */
1143 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1144 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1145 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1146 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1147 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1148 #interrupt-cells = <1>;
1149 interrupt-map-mask = <0 0 0 0>;
1150 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1151 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1152 clock-names = "pcie", "pcie_bus";
1153 status = "disabled";
1156 rcar_sound: rcar_sound@0xec500000 {
1157 #sound-dai-cells = <1>;
1158 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1159 reg = <0 0xec500000 0 0x1000>, /* SCU */
1160 <0 0xec5a0000 0 0x100>, /* ADG */
1161 <0 0xec540000 0 0x1000>, /* SSIU */
1162 <0 0xec541000 0 0x1280>; /* SSI */
1163 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1164 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1165 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1166 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1167 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1168 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1169 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1170 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1171 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1172 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1173 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1174 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1175 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1176 clock-names = "ssi-all",
1177 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1178 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1179 "src.9", "src.8", "src.7", "src.6", "src.5",
1180 "src.4", "src.3", "src.2", "src.1", "src.0",
1182 "clk_a", "clk_b", "clk_c", "clk_i";
1184 status = "disabled";
1205 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1206 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1207 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1208 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1209 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1210 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1211 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1212 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1213 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1214 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };