arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0>;
  50                         clock-frequency = <1500000000>;
  51                         voltage-tolerance = <1>; /* 1% */
  52                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  53                         clock-latency = <300000>; /* 300 us */
  54
  55                         /* kHz - uV - OPPs unknown yet */
  56                         operating-points = <1500000 1000000>,
  57                                            <1312500 1000000>,
  58                                            <1125000 1000000>,
  59                                            < 937500 1000000>,
  60                                            < 750000 1000000>,
  61                                            < 375000 1000000>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <1>;
  68                         clock-frequency = <1500000000>;
  69                 };
  70         };
  71
  72         gic: interrupt-controller@f1001000 {
  73                 compatible = "arm,cortex-a15-gic";
  74                 #interrupt-cells = <3>;
  75                 #address-cells = <0>;
  76                 interrupt-controller;
  77                 reg = <0 0xf1001000 0 0x1000>,
  78                         <0 0xf1002000 0 0x1000>,
  79                         <0 0xf1004000 0 0x2000>,
  80                         <0 0xf1006000 0 0x2000>;
  81                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  82         };
  83
  84         gpio0: gpio@e6050000 {
  85                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  86                 reg = <0 0xe6050000 0 0x50>;
  87                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90                 gpio-ranges = <&pfc 0 0 32>;
  91                 #interrupt-cells = <2>;
  92                 interrupt-controller;
  93                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
  94         };
  95
  96         gpio1: gpio@e6051000 {
  97                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  98                 reg = <0 0xe6051000 0 0x50>;
  99                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 32 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 106         };
 107
 108         gpio2: gpio@e6052000 {
 109                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 110                 reg = <0 0xe6052000 0 0x50>;
 111                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 64 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 118         };
 119
 120         gpio3: gpio@e6053000 {
 121                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 122                 reg = <0 0xe6053000 0 0x50>;
 123                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 96 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 142         };
 143
 144         gpio5: gpio@e6055000 {
 145                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055000 0 0x50>;
 147                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 160 32>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 154         };
 155
 156         gpio6: gpio@e6055400 {
 157                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 158                 reg = <0 0xe6055400 0 0x50>;
 159                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 160                 #gpio-cells = <2>;
 161                 gpio-controller;
 162                 gpio-ranges = <&pfc 0 192 32>;
 163                 #interrupt-cells = <2>;
 164                 interrupt-controller;
 165                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 166         };
 167
 168         gpio7: gpio@e6055800 {
 169                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 170                 reg = <0 0xe6055800 0 0x50>;
 171                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 gpio-ranges = <&pfc 0 224 26>;
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 178         };
 179
 180         thermal@e61f0000 {
 181                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 182                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 183                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 185         };
 186
 187         timer {
 188                 compatible = "arm,armv7-timer";
 189                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 190                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 191                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 193         };
 194
 195         cmt0: timer@ffca0000 {
 196                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 197                 reg = <0 0xffca0000 0 0x1004>;
 198                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 201                 clock-names = "fck";
 202
 203                 renesas,channels-mask = <0x60>;
 204
 205                 status = "disabled";
 206         };
 207
 208         cmt1: timer@e6130000 {
 209                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 210                 reg = <0 0xe6130000 0 0x1004>;
 211                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 212                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 214                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 215                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 216                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 217                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 218                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 220                 clock-names = "fck";
 221
 222                 renesas,channels-mask = <0xff>;
 223
 224                 status = "disabled";
 225         };
 226
 227         irqc0: interrupt-controller@e61c0000 {
 228                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 229                 #interrupt-cells = <2>;
 230                 interrupt-controller;
 231                 reg = <0 0xe61c0000 0 0x200>;
 232                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 238                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 239                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 240                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 241                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 242                 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
 243         };
 244
 245         dmac0: dma-controller@e6700000 {
 246                 compatible = "renesas,rcar-dmac";
 247                 reg = <0 0xe6700000 0 0x20000>;
 248                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 249                               0 200 IRQ_TYPE_LEVEL_HIGH
 250                               0 201 IRQ_TYPE_LEVEL_HIGH
 251                               0 202 IRQ_TYPE_LEVEL_HIGH
 252                               0 203 IRQ_TYPE_LEVEL_HIGH
 253                               0 204 IRQ_TYPE_LEVEL_HIGH
 254                               0 205 IRQ_TYPE_LEVEL_HIGH
 255                               0 206 IRQ_TYPE_LEVEL_HIGH
 256                               0 207 IRQ_TYPE_LEVEL_HIGH
 257                               0 208 IRQ_TYPE_LEVEL_HIGH
 258                               0 209 IRQ_TYPE_LEVEL_HIGH
 259                               0 210 IRQ_TYPE_LEVEL_HIGH
 260                               0 211 IRQ_TYPE_LEVEL_HIGH
 261                               0 212 IRQ_TYPE_LEVEL_HIGH
 262                               0 213 IRQ_TYPE_LEVEL_HIGH
 263                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 264                 interrupt-names = "error",
 265                                 "ch0", "ch1", "ch2", "ch3",
 266                                 "ch4", "ch5", "ch6", "ch7",
 267                                 "ch8", "ch9", "ch10", "ch11",
 268                                 "ch12", "ch13", "ch14";
 269                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 270                 clock-names = "fck";
 271                 #dma-cells = <1>;
 272                 dma-channels = <15>;
 273         };
 274
 275         dmac1: dma-controller@e6720000 {
 276                 compatible = "renesas,rcar-dmac";
 277                 reg = <0 0xe6720000 0 0x20000>;
 278                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 279                               0 216 IRQ_TYPE_LEVEL_HIGH
 280                               0 217 IRQ_TYPE_LEVEL_HIGH
 281                               0 218 IRQ_TYPE_LEVEL_HIGH
 282                               0 219 IRQ_TYPE_LEVEL_HIGH
 283                               0 308 IRQ_TYPE_LEVEL_HIGH
 284                               0 309 IRQ_TYPE_LEVEL_HIGH
 285                               0 310 IRQ_TYPE_LEVEL_HIGH
 286                               0 311 IRQ_TYPE_LEVEL_HIGH
 287                               0 312 IRQ_TYPE_LEVEL_HIGH
 288                               0 313 IRQ_TYPE_LEVEL_HIGH
 289                               0 314 IRQ_TYPE_LEVEL_HIGH
 290                               0 315 IRQ_TYPE_LEVEL_HIGH
 291                               0 316 IRQ_TYPE_LEVEL_HIGH
 292                               0 317 IRQ_TYPE_LEVEL_HIGH
 293                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 294                 interrupt-names = "error",
 295                                 "ch0", "ch1", "ch2", "ch3",
 296                                 "ch4", "ch5", "ch6", "ch7",
 297                                 "ch8", "ch9", "ch10", "ch11",
 298                                 "ch12", "ch13", "ch14";
 299                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 300                 clock-names = "fck";
 301                 #dma-cells = <1>;
 302                 dma-channels = <15>;
 303         };
 304
 305         audma0: dma-controller@ec700000 {
 306                 compatible = "renesas,rcar-dmac";
 307                 reg = <0 0xec700000 0 0x10000>;
 308                 interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
 309                                  0 320 IRQ_TYPE_LEVEL_HIGH
 310                                  0 321 IRQ_TYPE_LEVEL_HIGH
 311                                  0 322 IRQ_TYPE_LEVEL_HIGH
 312                                  0 323 IRQ_TYPE_LEVEL_HIGH
 313                                  0 324 IRQ_TYPE_LEVEL_HIGH
 314                                  0 325 IRQ_TYPE_LEVEL_HIGH
 315                                  0 326 IRQ_TYPE_LEVEL_HIGH
 316                                  0 327 IRQ_TYPE_LEVEL_HIGH
 317                                  0 328 IRQ_TYPE_LEVEL_HIGH
 318                                  0 329 IRQ_TYPE_LEVEL_HIGH
 319                                  0 330 IRQ_TYPE_LEVEL_HIGH
 320                                  0 331 IRQ_TYPE_LEVEL_HIGH
 321                                  0 332 IRQ_TYPE_LEVEL_HIGH>;
 322                 interrupt-names = "error",
 323                                 "ch0", "ch1", "ch2", "ch3",
 324                                 "ch4", "ch5", "ch6", "ch7",
 325                                 "ch8", "ch9", "ch10", "ch11",
 326                                 "ch12";
 327                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 328                 clock-names = "fck";
 329                 #dma-cells = <1>;
 330                 dma-channels = <13>;
 331         };
 332
 333         audma1: dma-controller@ec720000 {
 334                 compatible = "renesas,rcar-dmac";
 335                 reg = <0 0xec720000 0 0x10000>;
 336                 interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
 337                                  0 333 IRQ_TYPE_LEVEL_HIGH
 338                                  0 334 IRQ_TYPE_LEVEL_HIGH
 339                                  0 335 IRQ_TYPE_LEVEL_HIGH
 340                                  0 336 IRQ_TYPE_LEVEL_HIGH
 341                                  0 337 IRQ_TYPE_LEVEL_HIGH
 342                                  0 338 IRQ_TYPE_LEVEL_HIGH
 343                                  0 339 IRQ_TYPE_LEVEL_HIGH
 344                                  0 340 IRQ_TYPE_LEVEL_HIGH
 345                                  0 341 IRQ_TYPE_LEVEL_HIGH
 346                                  0 342 IRQ_TYPE_LEVEL_HIGH
 347                                  0 343 IRQ_TYPE_LEVEL_HIGH
 348                                  0 344 IRQ_TYPE_LEVEL_HIGH
 349                                  0 345 IRQ_TYPE_LEVEL_HIGH>;
 350                 interrupt-names = "error",
 351                                 "ch0", "ch1", "ch2", "ch3",
 352                                 "ch4", "ch5", "ch6", "ch7",
 353                                 "ch8", "ch9", "ch10", "ch11",
 354                                 "ch12";
 355                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 356                 clock-names = "fck";
 357                 #dma-cells = <1>;
 358                 dma-channels = <13>;
 359         };
 360
 361         usb_dmac0: dma-controller@e65a0000 {
 362                 compatible = "renesas,usb-dmac";
 363                 reg = <0 0xe65a0000 0 0x100>;
 364                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
 365                               0 109 IRQ_TYPE_LEVEL_HIGH>;
 366                 interrupt-names = "ch0", "ch1";
 367                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
 368                 #dma-cells = <1>;
 369                 dma-channels = <2>;
 370         };
 371
 372         usb_dmac1: dma-controller@e65b0000 {
 373                 compatible = "renesas,usb-dmac";
 374                 reg = <0 0xe65b0000 0 0x100>;
 375                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
 376                               0 110 IRQ_TYPE_LEVEL_HIGH>;
 377                 interrupt-names = "ch0", "ch1";
 378                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
 379                 #dma-cells = <1>;
 380                 dma-channels = <2>;
 381         };
 382
 383         /* The memory map in the User's Manual maps the cores to bus numbers */
 384         i2c0: i2c@e6508000 {
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 compatible = "renesas,i2c-r8a7791";
 388                 reg = <0 0xe6508000 0 0x40>;
 389                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 391                 status = "disabled";
 392         };
 393
 394         i2c1: i2c@e6518000 {
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 compatible = "renesas,i2c-r8a7791";
 398                 reg = <0 0xe6518000 0 0x40>;
 399                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 401                 status = "disabled";
 402         };
 403
 404         i2c2: i2c@e6530000 {
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 compatible = "renesas,i2c-r8a7791";
 408                 reg = <0 0xe6530000 0 0x40>;
 409                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 411                 status = "disabled";
 412         };
 413
 414         i2c3: i2c@e6540000 {
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 compatible = "renesas,i2c-r8a7791";
 418                 reg = <0 0xe6540000 0 0x40>;
 419                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c@e6520000 {
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 compatible = "renesas,i2c-r8a7791";
 428                 reg = <0 0xe6520000 0 0x40>;
 429                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 431                 status = "disabled";
 432         };
 433
 434         i2c5: i2c@e6528000 {
 435                 /* doesn't need pinmux */
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 compatible = "renesas,i2c-r8a7791";
 439                 reg = <0 0xe6528000 0 0x40>;
 440                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 442                 status = "disabled";
 443         };
 444
 445         i2c6: i2c@e60b0000 {
 446                 /* doesn't need pinmux */
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 450                 reg = <0 0xe60b0000 0 0x425>;
 451                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 453                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 454                 dma-names = "tx", "rx";
 455                 status = "disabled";
 456         };
 457
 458         i2c7: i2c@e6500000 {
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 462                 reg = <0 0xe6500000 0 0x425>;
 463                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 465                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 466                 dma-names = "tx", "rx";
 467                 status = "disabled";
 468         };
 469
 470         i2c8: i2c@e6510000 {
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 474                 reg = <0 0xe6510000 0 0x425>;
 475                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 477                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 478                 dma-names = "tx", "rx";
 479                 status = "disabled";
 480         };
 481
 482         pfc: pfc@e6060000 {
 483                 compatible = "renesas,pfc-r8a7791";
 484                 reg = <0 0xe6060000 0 0x250>;
 485                 #gpio-range-cells = <3>;
 486         };
 487
 488         mmcif0: mmc@ee200000 {
 489                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 490                 reg = <0 0xee200000 0 0x80>;
 491                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 492                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 493                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 494                 dma-names = "tx", "rx";
 495                 reg-io-width = <4>;
 496                 status = "disabled";
 497         };
 498
 499         sdhi0: sd@ee100000 {
 500                 compatible = "renesas,sdhi-r8a7791";
 501                 reg = <0 0xee100000 0 0x328>;
 502                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 504                 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 505                 dma-names = "tx", "rx";
 506                 status = "disabled";
 507         };
 508
 509         sdhi1: sd@ee140000 {
 510                 compatible = "renesas,sdhi-r8a7791";
 511                 reg = <0 0xee140000 0 0x100>;
 512                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 513                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 514                 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 515                 dma-names = "tx", "rx";
 516                 status = "disabled";
 517         };
 518
 519         sdhi2: sd@ee160000 {
 520                 compatible = "renesas,sdhi-r8a7791";
 521                 reg = <0 0xee160000 0 0x100>;
 522                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 523                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 524                 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 525                 dma-names = "tx", "rx";
 526                 status = "disabled";
 527         };
 528
 529         scifa0: serial@e6c40000 {
 530                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 531                 reg = <0 0xe6c40000 0 64>;
 532                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 534                 clock-names = "sci_ick";
 535                 status = "disabled";
 536         };
 537
 538         scifa1: serial@e6c50000 {
 539                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 540                 reg = <0 0xe6c50000 0 64>;
 541                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 542                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 543                 clock-names = "sci_ick";
 544                 status = "disabled";
 545         };
 546
 547         scifa2: serial@e6c60000 {
 548                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 549                 reg = <0 0xe6c60000 0 64>;
 550                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 552                 clock-names = "sci_ick";
 553                 status = "disabled";
 554         };
 555
 556         scifa3: serial@e6c70000 {
 557                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 558                 reg = <0 0xe6c70000 0 64>;
 559                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 560                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 561                 clock-names = "sci_ick";
 562                 status = "disabled";
 563         };
 564
 565         scifa4: serial@e6c78000 {
 566                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 567                 reg = <0 0xe6c78000 0 64>;
 568                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 569                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 570                 clock-names = "sci_ick";
 571                 status = "disabled";
 572         };
 573
 574         scifa5: serial@e6c80000 {
 575                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 576                 reg = <0 0xe6c80000 0 64>;
 577                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 579                 clock-names = "sci_ick";
 580                 status = "disabled";
 581         };
 582
 583         scifb0: serial@e6c20000 {
 584                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 585                 reg = <0 0xe6c20000 0 64>;
 586                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 587                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 588                 clock-names = "sci_ick";
 589                 status = "disabled";
 590         };
 591
 592         scifb1: serial@e6c30000 {
 593                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 594                 reg = <0 0xe6c30000 0 64>;
 595                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 597                 clock-names = "sci_ick";
 598                 status = "disabled";
 599         };
 600
 601         scifb2: serial@e6ce0000 {
 602                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 603                 reg = <0 0xe6ce0000 0 64>;
 604                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 606                 clock-names = "sci_ick";
 607                 status = "disabled";
 608         };
 609
 610         scif0: serial@e6e60000 {
 611                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 612                 reg = <0 0xe6e60000 0 64>;
 613                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 615                 clock-names = "sci_ick";
 616                 status = "disabled";
 617         };
 618
 619         scif1: serial@e6e68000 {
 620                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 621                 reg = <0 0xe6e68000 0 64>;
 622                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 624                 clock-names = "sci_ick";
 625                 status = "disabled";
 626         };
 627
 628         scif2: serial@e6e58000 {
 629                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 630                 reg = <0 0xe6e58000 0 64>;
 631                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 633                 clock-names = "sci_ick";
 634                 status = "disabled";
 635         };
 636
 637         scif3: serial@e6ea8000 {
 638                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 639                 reg = <0 0xe6ea8000 0 64>;
 640                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 642                 clock-names = "sci_ick";
 643                 status = "disabled";
 644         };
 645
 646         scif4: serial@e6ee0000 {
 647                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 648                 reg = <0 0xe6ee0000 0 64>;
 649                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 650                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 651                 clock-names = "sci_ick";
 652                 status = "disabled";
 653         };
 654
 655         scif5: serial@e6ee8000 {
 656                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 657                 reg = <0 0xe6ee8000 0 64>;
 658                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 659                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 660                 clock-names = "sci_ick";
 661                 status = "disabled";
 662         };
 663
 664         hscif0: serial@e62c0000 {
 665                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 666                 reg = <0 0xe62c0000 0 96>;
 667                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 669                 clock-names = "sci_ick";
 670                 status = "disabled";
 671         };
 672
 673         hscif1: serial@e62c8000 {
 674                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 675                 reg = <0 0xe62c8000 0 96>;
 676                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 678                 clock-names = "sci_ick";
 679                 status = "disabled";
 680         };
 681
 682         hscif2: serial@e62d0000 {
 683                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 684                 reg = <0 0xe62d0000 0 96>;
 685                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 686                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 687                 clock-names = "sci_ick";
 688                 status = "disabled";
 689         };
 690
 691         ether: ethernet@ee700000 {
 692                 compatible = "renesas,ether-r8a7791";
 693                 reg = <0 0xee700000 0 0x400>;
 694                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 696                 phy-mode = "rmii";
 697                 #address-cells = <1>;
 698                 #size-cells = <0>;
 699                 status = "disabled";
 700         };
 701
 702         sata0: sata@ee300000 {
 703                 compatible = "renesas,sata-r8a7791";
 704                 reg = <0 0xee300000 0 0x2000>;
 705                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 706                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 707                 status = "disabled";
 708         };
 709
 710         sata1: sata@ee500000 {
 711                 compatible = "renesas,sata-r8a7791";
 712                 reg = <0 0xee500000 0 0x2000>;
 713                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 715                 status = "disabled";
 716         };
 717
 718         hsusb: usb@e6590000 {
 719                 compatible = "renesas,usbhs-r8a7791";
 720                 reg = <0 0xe6590000 0 0x100>;
 721                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 722                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 723                 renesas,buswait = <4>;
 724                 phys = <&usb0 1>;
 725                 phy-names = "usb";
 726                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 727                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 728                 dma-names = "ch0", "ch1", "ch2", "ch3";
 729                 status = "disabled";
 730         };
 731
 732         usbphy: usb-phy@e6590100 {
 733                 compatible = "renesas,usb-phy-r8a7791";
 734                 reg = <0 0xe6590100 0 0x100>;
 735                 #address-cells = <1>;
 736                 #size-cells = <0>;
 737                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 738                 clock-names = "usbhs";
 739                 status = "disabled";
 740
 741                 usb0: usb-channel@0 {
 742                         reg = <0>;
 743                         #phy-cells = <1>;
 744                 };
 745                 usb2: usb-channel@2 {
 746                         reg = <2>;
 747                         #phy-cells = <1>;
 748                 };
 749         };
 750
 751         vin0: video@e6ef0000 {
 752                 compatible = "renesas,vin-r8a7791";
 753                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 754                 reg = <0 0xe6ef0000 0 0x1000>;
 755                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 756                 status = "disabled";
 757         };
 758
 759         vin1: video@e6ef1000 {
 760                 compatible = "renesas,vin-r8a7791";
 761                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 762                 reg = <0 0xe6ef1000 0 0x1000>;
 763                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 764                 status = "disabled";
 765         };
 766
 767         vin2: video@e6ef2000 {
 768                 compatible = "renesas,vin-r8a7791";
 769                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 770                 reg = <0 0xe6ef2000 0 0x1000>;
 771                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 772                 status = "disabled";
 773         };
 774
 775         vsp1@fe928000 {
 776                 compatible = "renesas,vsp1";
 777                 reg = <0 0xfe928000 0 0x8000>;
 778                 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 779                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
 780
 781                 renesas,has-lut;
 782                 renesas,has-sru;
 783                 renesas,#rpf = <5>;
 784                 renesas,#uds = <3>;
 785                 renesas,#wpf = <4>;
 786         };
 787
 788         vsp1@fe930000 {
 789                 compatible = "renesas,vsp1";
 790                 reg = <0 0xfe930000 0 0x8000>;
 791                 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 792                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
 793
 794                 renesas,has-lif;
 795                 renesas,has-lut;
 796                 renesas,#rpf = <4>;
 797                 renesas,#uds = <1>;
 798                 renesas,#wpf = <4>;
 799         };
 800
 801         vsp1@fe938000 {
 802                 compatible = "renesas,vsp1";
 803                 reg = <0 0xfe938000 0 0x8000>;
 804                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 805                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
 806
 807                 renesas,has-lif;
 808                 renesas,has-lut;
 809                 renesas,#rpf = <4>;
 810                 renesas,#uds = <1>;
 811                 renesas,#wpf = <4>;
 812         };
 813
 814         du: display@feb00000 {
 815                 compatible = "renesas,du-r8a7791";
 816                 reg = <0 0xfeb00000 0 0x40000>,
 817                       <0 0xfeb90000 0 0x1c>;
 818                 reg-names = "du", "lvds.0";
 819                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 820                              <0 268 IRQ_TYPE_LEVEL_HIGH>;
 821                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
 822                          <&mstp7_clks R8A7791_CLK_DU1>,
 823                          <&mstp7_clks R8A7791_CLK_LVDS0>;
 824                 clock-names = "du.0", "du.1", "lvds.0";
 825                 status = "disabled";
 826
 827                 ports {
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830
 831                         port@0 {
 832                                 reg = <0>;
 833                                 du_out_rgb: endpoint {
 834                                 };
 835                         };
 836                         port@1 {
 837                                 reg = <1>;
 838                                 du_out_lvds0: endpoint {
 839                                 };
 840                         };
 841                 };
 842         };
 843
 844         can0: can@e6e80000 {
 845                 compatible = "renesas,can-r8a7791";
 846                 reg = <0 0xe6e80000 0 0x1000>;
 847                 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
 848                 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
 849                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 850                 clock-names = "clkp1", "clkp2", "can_clk";
 851                 status = "disabled";
 852         };
 853
 854         can1: can@e6e88000 {
 855                 compatible = "renesas,can-r8a7791";
 856                 reg = <0 0xe6e88000 0 0x1000>;
 857                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
 859                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 860                 clock-names = "clkp1", "clkp2", "can_clk";
 861                 status = "disabled";
 862         };
 863
 864         clocks {
 865                 #address-cells = <2>;
 866                 #size-cells = <2>;
 867                 ranges;
 868
 869                 /* External root clock */
 870                 extal_clk: extal_clk {
 871                         compatible = "fixed-clock";
 872                         #clock-cells = <0>;
 873                         /* This value must be overriden by the board. */
 874                         clock-frequency = <0>;
 875                         clock-output-names = "extal";
 876                 };
 877
 878                 /*
 879                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 880                  * default. Boards that provide audio clocks should override them.
 881                  */
 882                 audio_clk_a: audio_clk_a {
 883                         compatible = "fixed-clock";
 884                         #clock-cells = <0>;
 885                         clock-frequency = <0>;
 886                         clock-output-names = "audio_clk_a";
 887                 };
 888                 audio_clk_b: audio_clk_b {
 889                         compatible = "fixed-clock";
 890                         #clock-cells = <0>;
 891                         clock-frequency = <0>;
 892                         clock-output-names = "audio_clk_b";
 893                 };
 894                 audio_clk_c: audio_clk_c {
 895                         compatible = "fixed-clock";
 896                         #clock-cells = <0>;
 897                         clock-frequency = <0>;
 898                         clock-output-names = "audio_clk_c";
 899                 };
 900
 901                 /* External PCIe clock - can be overridden by the board */
 902                 pcie_bus_clk: pcie_bus_clk {
 903                         compatible = "fixed-clock";
 904                         #clock-cells = <0>;
 905                         clock-frequency = <100000000>;
 906                         clock-output-names = "pcie_bus";
 907                         status = "disabled";
 908                 };
 909
 910                 /* External USB clock - can be overridden by the board */
 911                 usb_extal_clk: usb_extal_clk {
 912                         compatible = "fixed-clock";
 913                         #clock-cells = <0>;
 914                         clock-frequency = <48000000>;
 915                         clock-output-names = "usb_extal";
 916                 };
 917
 918                 /* External CAN clock */
 919                 can_clk: can_clk {
 920                         compatible = "fixed-clock";
 921                         #clock-cells = <0>;
 922                         /* This value must be overridden by the board. */
 923                         clock-frequency = <0>;
 924                         clock-output-names = "can_clk";
 925                         status = "disabled";
 926                 };
 927
 928                 /* Special CPG clocks */
 929                 cpg_clocks: cpg_clocks@e6150000 {
 930                         compatible = "renesas,r8a7791-cpg-clocks",
 931                                      "renesas,rcar-gen2-cpg-clocks";
 932                         reg = <0 0xe6150000 0 0x1000>;
 933                         clocks = <&extal_clk &usb_extal_clk>;
 934                         #clock-cells = <1>;
 935                         clock-output-names = "main", "pll0", "pll1", "pll3",
 936                                              "lb", "qspi", "sdh", "sd0", "z",
 937                                              "rcan", "adsp";
 938                 };
 939
 940                 /* Variable factor clocks */
 941                 sd2_clk: sd2_clk@e6150078 {
 942                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 943                         reg = <0 0xe6150078 0 4>;
 944                         clocks = <&pll1_div2_clk>;
 945                         #clock-cells = <0>;
 946                         clock-output-names = "sd2";
 947                 };
 948                 sd3_clk: sd3_clk@e615026c {
 949                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 950                         reg = <0 0xe615026c 0 4>;
 951                         clocks = <&pll1_div2_clk>;
 952                         #clock-cells = <0>;
 953                         clock-output-names = "sd3";
 954                 };
 955                 mmc0_clk: mmc0_clk@e6150240 {
 956                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 957                         reg = <0 0xe6150240 0 4>;
 958                         clocks = <&pll1_div2_clk>;
 959                         #clock-cells = <0>;
 960                         clock-output-names = "mmc0";
 961                 };
 962                 ssp_clk: ssp_clk@e6150248 {
 963                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 964                         reg = <0 0xe6150248 0 4>;
 965                         clocks = <&pll1_div2_clk>;
 966                         #clock-cells = <0>;
 967                         clock-output-names = "ssp";
 968                 };
 969                 ssprs_clk: ssprs_clk@e615024c {
 970                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 971                         reg = <0 0xe615024c 0 4>;
 972                         clocks = <&pll1_div2_clk>;
 973                         #clock-cells = <0>;
 974                         clock-output-names = "ssprs";
 975                 };
 976
 977                 /* Fixed factor clocks */
 978                 pll1_div2_clk: pll1_div2_clk {
 979                         compatible = "fixed-factor-clock";
 980                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 981                         #clock-cells = <0>;
 982                         clock-div = <2>;
 983                         clock-mult = <1>;
 984                         clock-output-names = "pll1_div2";
 985                 };
 986                 zg_clk: zg_clk {
 987                         compatible = "fixed-factor-clock";
 988                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 989                         #clock-cells = <0>;
 990                         clock-div = <3>;
 991                         clock-mult = <1>;
 992                         clock-output-names = "zg";
 993                 };
 994                 zx_clk: zx_clk {
 995                         compatible = "fixed-factor-clock";
 996                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 997                         #clock-cells = <0>;
 998                         clock-div = <3>;
 999                         clock-mult = <1>;
1000                         clock-output-names = "zx";
1001                 };
1002                 zs_clk: zs_clk {
1003                         compatible = "fixed-factor-clock";
1004                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1005                         #clock-cells = <0>;
1006                         clock-div = <6>;
1007                         clock-mult = <1>;
1008                         clock-output-names = "zs";
1009                 };
1010                 hp_clk: hp_clk {
1011                         compatible = "fixed-factor-clock";
1012                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1013                         #clock-cells = <0>;
1014                         clock-div = <12>;
1015                         clock-mult = <1>;
1016                         clock-output-names = "hp";
1017                 };
1018                 i_clk: i_clk {
1019                         compatible = "fixed-factor-clock";
1020                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1021                         #clock-cells = <0>;
1022                         clock-div = <2>;
1023                         clock-mult = <1>;
1024                         clock-output-names = "i";
1025                 };
1026                 b_clk: b_clk {
1027                         compatible = "fixed-factor-clock";
1028                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1029                         #clock-cells = <0>;
1030                         clock-div = <12>;
1031                         clock-mult = <1>;
1032                         clock-output-names = "b";
1033                 };
1034                 p_clk: p_clk {
1035                         compatible = "fixed-factor-clock";
1036                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1037                         #clock-cells = <0>;
1038                         clock-div = <24>;
1039                         clock-mult = <1>;
1040                         clock-output-names = "p";
1041                 };
1042                 cl_clk: cl_clk {
1043                         compatible = "fixed-factor-clock";
1044                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1045                         #clock-cells = <0>;
1046                         clock-div = <48>;
1047                         clock-mult = <1>;
1048                         clock-output-names = "cl";
1049                 };
1050                 m2_clk: m2_clk {
1051                         compatible = "fixed-factor-clock";
1052                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1053                         #clock-cells = <0>;
1054                         clock-div = <8>;
1055                         clock-mult = <1>;
1056                         clock-output-names = "m2";
1057                 };
1058                 imp_clk: imp_clk {
1059                         compatible = "fixed-factor-clock";
1060                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1061                         #clock-cells = <0>;
1062                         clock-div = <4>;
1063                         clock-mult = <1>;
1064                         clock-output-names = "imp";
1065                 };
1066                 rclk_clk: rclk_clk {
1067                         compatible = "fixed-factor-clock";
1068                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1069                         #clock-cells = <0>;
1070                         clock-div = <(48 * 1024)>;
1071                         clock-mult = <1>;
1072                         clock-output-names = "rclk";
1073                 };
1074                 oscclk_clk: oscclk_clk {
1075                         compatible = "fixed-factor-clock";
1076                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1077                         #clock-cells = <0>;
1078                         clock-div = <(12 * 1024)>;
1079                         clock-mult = <1>;
1080                         clock-output-names = "oscclk";
1081                 };
1082                 zb3_clk: zb3_clk {
1083                         compatible = "fixed-factor-clock";
1084                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1085                         #clock-cells = <0>;
1086                         clock-div = <4>;
1087                         clock-mult = <1>;
1088                         clock-output-names = "zb3";
1089                 };
1090                 zb3d2_clk: zb3d2_clk {
1091                         compatible = "fixed-factor-clock";
1092                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1093                         #clock-cells = <0>;
1094                         clock-div = <8>;
1095                         clock-mult = <1>;
1096                         clock-output-names = "zb3d2";
1097                 };
1098                 ddr_clk: ddr_clk {
1099                         compatible = "fixed-factor-clock";
1100                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1101                         #clock-cells = <0>;
1102                         clock-div = <8>;
1103                         clock-mult = <1>;
1104                         clock-output-names = "ddr";
1105                 };
1106                 mp_clk: mp_clk {
1107                         compatible = "fixed-factor-clock";
1108                         clocks = <&pll1_div2_clk>;
1109                         #clock-cells = <0>;
1110                         clock-div = <15>;
1111                         clock-mult = <1>;
1112                         clock-output-names = "mp";
1113                 };
1114                 cp_clk: cp_clk {
1115                         compatible = "fixed-factor-clock";
1116                         clocks = <&extal_clk>;
1117                         #clock-cells = <0>;
1118                         clock-div = <2>;
1119                         clock-mult = <1>;
1120                         clock-output-names = "cp";
1121                 };
1122
1123                 /* Gate clocks */
1124                 mstp0_clks: mstp0_clks@e6150130 {
1125                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1126                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1127                         clocks = <&mp_clk>;
1128                         #clock-cells = <1>;
1129                         clock-indices = <R8A7791_CLK_MSIOF0>;
1130                         clock-output-names = "msiof0";
1131                 };
1132                 mstp1_clks: mstp1_clks@e6150134 {
1133                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1134                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1135                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1136                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1137                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1138                                  <&zs_clk>;
1139                         #clock-cells = <1>;
1140                         clock-indices = <
1141                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1142                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1143                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1144                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1145                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1146                                 R8A7791_CLK_VSP1_S
1147                         >;
1148                         clock-output-names =
1149                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1150                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1151                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1152                 };
1153                 mstp2_clks: mstp2_clks@e6150138 {
1154                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1155                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1156                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1157                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1158                                  <&zs_clk>, <&zs_clk>;
1159                         #clock-cells = <1>;
1160                         clock-indices = <
1161                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1162                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1163                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1164                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1165                         >;
1166                         clock-output-names =
1167                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1168                                 "scifb1", "msiof1", "scifb2",
1169                                 "sys-dmac1", "sys-dmac0";
1170                 };
1171                 mstp3_clks: mstp3_clks@e615013c {
1172                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1173                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1174                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1175                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1176                                  <&hp_clk>, <&hp_clk>;
1177                         #clock-cells = <1>;
1178                         clock-indices = <
1179                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1180                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1181                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1182                                 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1183                         >;
1184                         clock-output-names =
1185                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1186                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1187                                 "usbdmac0", "usbdmac1";
1188                 };
1189                 mstp4_clks: mstp4_clks@e6150140 {
1190                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1191                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1192                         clocks = <&cp_clk>;
1193                         #clock-cells = <1>;
1194                         clock-indices = <R8A7791_CLK_IRQC>;
1195                         clock-output-names = "irqc";
1196                 };
1197                 mstp5_clks: mstp5_clks@e6150144 {
1198                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1199                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1200                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1201                                  <&extal_clk>, <&p_clk>;
1202                         #clock-cells = <1>;
1203                         clock-indices = <
1204                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1205                                 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1206                                 R8A7791_CLK_PWM
1207                         >;
1208                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1209                                              "thermal", "pwm";
1210                 };
1211                 mstp7_clks: mstp7_clks@e615014c {
1212                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1213                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1214                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1215                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1216                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1217                         #clock-cells = <1>;
1218                         clock-indices = <
1219                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1220                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1221                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1222                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1223                                 R8A7791_CLK_LVDS0
1224                         >;
1225                         clock-output-names =
1226                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1227                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1228                 };
1229                 mstp8_clks: mstp8_clks@e6150990 {
1230                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1231                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1232                         clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1233                                  <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1234                         #clock-cells = <1>;
1235                         clock-indices = <
1236                                 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1237                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1238                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1239                         >;
1240                         clock-output-names =
1241                                 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1242                                 "sata1", "sata0";
1243                 };
1244                 mstp9_clks: mstp9_clks@e6150994 {
1245                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1246                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1247                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1248                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1249                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1250                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1251                                  <&hp_clk>, <&hp_clk>;
1252                         #clock-cells = <1>;
1253                         clock-indices = <
1254                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1255                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1256                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1257                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1258                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1259                         >;
1260                         clock-output-names =
1261                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1262                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1263                                 "i2c1", "i2c0";
1264                 };
1265                 mstp10_clks: mstp10_clks@e6150998 {
1266                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1267                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1268                         clocks = <&p_clk>,
1269                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1270                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1271                                 <&p_clk>,
1272                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1273                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1274                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1275                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1276                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1277                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1278
1279                         #clock-cells = <1>;
1280                         clock-indices = <
1281                                 R8A7791_CLK_SSI_ALL
1282                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1283                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1284                                 R8A7791_CLK_SCU_ALL
1285                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1286                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1287                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1288                         >;
1289                         clock-output-names =
1290                                 "ssi-all",
1291                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1292                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1293                                 "scu-all",
1294                                 "scu-dvc1", "scu-dvc0",
1295                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1296                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1297                 };
1298                 mstp11_clks: mstp11_clks@e615099c {
1299                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1300                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1301                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1302                         #clock-cells = <1>;
1303                         clock-indices = <
1304                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1305                         >;
1306                         clock-output-names = "scifa3", "scifa4", "scifa5";
1307                 };
1308         };
1309
1310         qspi: spi@e6b10000 {
1311                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1312                 reg = <0 0xe6b10000 0 0x2c>;
1313                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1314                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1315                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1316                 dma-names = "tx", "rx";
1317                 num-cs = <1>;
1318                 #address-cells = <1>;
1319                 #size-cells = <0>;
1320                 status = "disabled";
1321         };
1322
1323         msiof0: spi@e6e20000 {
1324                 compatible = "renesas,msiof-r8a7791";
1325                 reg = <0 0xe6e20000 0 0x0064>;
1326                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1327                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1328                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1329                 dma-names = "tx", "rx";
1330                 #address-cells = <1>;
1331                 #size-cells = <0>;
1332                 status = "disabled";
1333         };
1334
1335         msiof1: spi@e6e10000 {
1336                 compatible = "renesas,msiof-r8a7791";
1337                 reg = <0 0xe6e10000 0 0x0064>;
1338                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1339                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1340                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1341                 dma-names = "tx", "rx";
1342                 #address-cells = <1>;
1343                 #size-cells = <0>;
1344                 status = "disabled";
1345         };
1346
1347         msiof2: spi@e6e00000 {
1348                 compatible = "renesas,msiof-r8a7791";
1349                 reg = <0 0xe6e00000 0 0x0064>;
1350                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1351                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1352                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1353                 dma-names = "tx", "rx";
1354                 #address-cells = <1>;
1355                 #size-cells = <0>;
1356                 status = "disabled";
1357         };
1358
1359         xhci: usb@ee000000 {
1360                 compatible = "renesas,xhci-r8a7791";
1361                 reg = <0 0xee000000 0 0xc00>;
1362                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1363                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1364                 phys = <&usb2 1>;
1365                 phy-names = "usb";
1366                 status = "disabled";
1367         };
1368
1369         pci0: pci@ee090000 {
1370                 compatible = "renesas,pci-r8a7791";
1371                 device_type = "pci";
1372                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1373                 reg = <0 0xee090000 0 0xc00>,
1374                       <0 0xee080000 0 0x1100>;
1375                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1376                 status = "disabled";
1377
1378                 bus-range = <0 0>;
1379                 #address-cells = <3>;
1380                 #size-cells = <2>;
1381                 #interrupt-cells = <1>;
1382                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1383                 interrupt-map-mask = <0xff00 0 0 0x7>;
1384                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1385                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1386                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1387
1388                 usb@0,1 {
1389                         reg = <0x800 0 0 0 0>;
1390                         device_type = "pci";
1391                         phys = <&usb0 0>;
1392                         phy-names = "usb";
1393                 };
1394
1395                 usb@0,2 {
1396                         reg = <0x1000 0 0 0 0>;
1397                         device_type = "pci";
1398                         phys = <&usb0 0>;
1399                         phy-names = "usb";
1400                 };
1401         };
1402
1403         pci1: pci@ee0d0000 {
1404                 compatible = "renesas,pci-r8a7791";
1405                 device_type = "pci";
1406                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1407                 reg = <0 0xee0d0000 0 0xc00>,
1408                       <0 0xee0c0000 0 0x1100>;
1409                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1410                 status = "disabled";
1411
1412                 bus-range = <1 1>;
1413                 #address-cells = <3>;
1414                 #size-cells = <2>;
1415                 #interrupt-cells = <1>;
1416                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1417                 interrupt-map-mask = <0xff00 0 0 0x7>;
1418                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1419                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1420                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1421
1422                 usb@0,1 {
1423                         reg = <0x800 0 0 0 0>;
1424                         device_type = "pci";
1425                         phys = <&usb2 0>;
1426                         phy-names = "usb";
1427                 };
1428
1429                 usb@0,2 {
1430                         reg = <0x1000 0 0 0 0>;
1431                         device_type = "pci";
1432                         phys = <&usb2 0>;
1433                         phy-names = "usb";
1434                 };
1435         };
1436
1437         pciec: pcie@fe000000 {
1438                 compatible = "renesas,pcie-r8a7791";
1439                 reg = <0 0xfe000000 0 0x80000>;
1440                 #address-cells = <3>;
1441                 #size-cells = <2>;
1442                 bus-range = <0x00 0xff>;
1443                 device_type = "pci";
1444                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1445                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1446                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1447                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1448                 /* Map all possible DDR as inbound ranges */
1449                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1450                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1451                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1452                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1453                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1454                 #interrupt-cells = <1>;
1455                 interrupt-map-mask = <0 0 0 0>;
1456                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1457                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1458                 clock-names = "pcie", "pcie_bus";
1459                 status = "disabled";
1460         };
1461
1462         ipmmu_sy0: mmu@e6280000 {
1463                 compatible = "renesas,ipmmu-vmsa";
1464                 reg = <0 0xe6280000 0 0x1000>;
1465                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1466                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
1467                 #iommu-cells = <1>;
1468                 status = "disabled";
1469         };
1470
1471         ipmmu_sy1: mmu@e6290000 {
1472                 compatible = "renesas,ipmmu-vmsa";
1473                 reg = <0 0xe6290000 0 0x1000>;
1474                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1475                 #iommu-cells = <1>;
1476                 status = "disabled";
1477         };
1478
1479         ipmmu_ds: mmu@e6740000 {
1480                 compatible = "renesas,ipmmu-vmsa";
1481                 reg = <0 0xe6740000 0 0x1000>;
1482                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1483                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
1484                 #iommu-cells = <1>;
1485                 status = "disabled";
1486         };
1487
1488         ipmmu_mp: mmu@ec680000 {
1489                 compatible = "renesas,ipmmu-vmsa";
1490                 reg = <0 0xec680000 0 0x1000>;
1491                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1492                 #iommu-cells = <1>;
1493                 status = "disabled";
1494         };
1495
1496         ipmmu_mx: mmu@fe951000 {
1497                 compatible = "renesas,ipmmu-vmsa";
1498                 reg = <0 0xfe951000 0 0x1000>;
1499                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1500                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
1501                 #iommu-cells = <1>;
1502                 status = "disabled";
1503         };
1504
1505         ipmmu_rt: mmu@ffc80000 {
1506                 compatible = "renesas,ipmmu-vmsa";
1507                 reg = <0 0xffc80000 0 0x1000>;
1508                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1509                 #iommu-cells = <1>;
1510                 status = "disabled";
1511         };
1512
1513         ipmmu_gp: mmu@e62a0000 {
1514                 compatible = "renesas,ipmmu-vmsa";
1515                 reg = <0 0xe62a0000 0 0x1000>;
1516                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1517                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
1518                 #iommu-cells = <1>;
1519                 status = "disabled";
1520         };
1521
1522         rcar_sound: sound@ec500000 {
1523                 /*
1524                  * #sound-dai-cells is required
1525                  *
1526                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1527                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1528                  */
1529                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1530                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1531                         <0 0xec5a0000 0 0x100>,  /* ADG */
1532                         <0 0xec540000 0 0x1000>, /* SSIU */
1533                         <0 0xec541000 0 0x1280>, /* SSI */
1534                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1535                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1536
1537                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1538                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1539                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1540                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1541                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1542                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1543                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1544                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1545                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1546                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1547                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1548                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1549                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1550                 clock-names = "ssi-all",
1551                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1552                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1553                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1554                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1555                                 "dvc.0", "dvc.1",
1556                                 "clk_a", "clk_b", "clk_c", "clk_i";
1557
1558                 status = "disabled";
1559
1560                 rcar_sound,dvc {
1561                         dvc0: dvc@0 {
1562                                 dmas = <&audma0 0xbc>;
1563                                 dma-names = "tx";
1564                         };
1565                         dvc1: dvc@1 {
1566                                 dmas = <&audma0 0xbe>;
1567                                 dma-names = "tx";
1568                         };
1569                 };
1570
1571                 rcar_sound,src {
1572                         src0: src@0 {
1573                                 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1574                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1575                                 dma-names = "rx", "tx";
1576                         };
1577                         src1: src@1 {
1578                                 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1579                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1580                                 dma-names = "rx", "tx";
1581                         };
1582                         src2: src@2 {
1583                                 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1584                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1585                                 dma-names = "rx", "tx";
1586                         };
1587                         src3: src@3 {
1588                                 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1589                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1590                                 dma-names = "rx", "tx";
1591                         };
1592                         src4: src@4 {
1593                                 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1594                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1595                                 dma-names = "rx", "tx";
1596                         };
1597                         src5: src@5 {
1598                                 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1599                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1600                                 dma-names = "rx", "tx";
1601                         };
1602                         src6: src@6 {
1603                                 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1604                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1605                                 dma-names = "rx", "tx";
1606                         };
1607                         src7: src@7 {
1608                                 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1609                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1610                                 dma-names = "rx", "tx";
1611                         };
1612                         src8: src@8 {
1613                                 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1614                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1615                                 dma-names = "rx", "tx";
1616                         };
1617                         src9: src@9 {
1618                                 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1619                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1620                                 dma-names = "rx", "tx";
1621                         };
1622                 };
1623
1624                 rcar_sound,ssi {
1625                         ssi0: ssi@0 {
1626                                 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1627                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1628                                 dma-names = "rx", "tx", "rxu", "txu";
1629                         };
1630                         ssi1: ssi@1 {
1631                                  interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1632                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1633                                 dma-names = "rx", "tx", "rxu", "txu";
1634                         };
1635                         ssi2: ssi@2 {
1636                                 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1637                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1638                                 dma-names = "rx", "tx", "rxu", "txu";
1639                         };
1640                         ssi3: ssi@3 {
1641                                 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1642                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1643                                 dma-names = "rx", "tx", "rxu", "txu";
1644                         };
1645                         ssi4: ssi@4 {
1646                                 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1647                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1648                                 dma-names = "rx", "tx", "rxu", "txu";
1649                         };
1650                         ssi5: ssi@5 {
1651                                 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1652                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1653                                 dma-names = "rx", "tx", "rxu", "txu";
1654                         };
1655                         ssi6: ssi@6 {
1656                                 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1657                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1658                                 dma-names = "rx", "tx", "rxu", "txu";
1659                         };
1660                         ssi7: ssi@7 {
1661                                 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1662                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1663                                 dma-names = "rx", "tx", "rxu", "txu";
1664                         };
1665                         ssi8: ssi@8 {
1666                                 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1667                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1668                                 dma-names = "rx", "tx", "rxu", "txu";
1669                         };
1670                         ssi9: ssi@9 {
1671                                 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1672                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1673                                 dma-names = "rx", "tx", "rxu", "txu";
1674                         };
1675                 };
1676         };
1677 };