arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /include/ "skeleton.dtsi"
  18
  19 #include <dt-bindings/clock/r8a7778-clock.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "renesas,r8a7778";
  24         interrupt-parent = <&gic>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                         clock-frequency = <800000000>;
  35                 };
  36         };
  37
  38         aliases {
  39                 spi0 = &hspi0;
  40                 spi1 = &hspi1;
  41                 spi2 = &hspi2;
  42         };
  43
  44         gic: interrupt-controller@fe438000 {
  45                 compatible = "arm,cortex-a9-gic";
  46                 #interrupt-cells = <3>;
  47                 interrupt-controller;
  48                 reg = <0xfe438000 0x1000>,
  49                       <0xfe430000 0x100>;
  50         };
  51
  52         /* irqpin: IRQ0 - IRQ3 */
  53         irqpin: irqpin@fe78001c {
  54                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  55                 #interrupt-cells = <2>;
  56                 interrupt-controller;
  57                 status = "disabled"; /* default off */
  58                 reg =   <0xfe78001c 4>,
  59                         <0xfe780010 4>,
  60                         <0xfe780024 4>,
  61                         <0xfe780044 4>,
  62                         <0xfe780064 4>;
  63                 interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
  64                                 0 28 IRQ_TYPE_LEVEL_HIGH
  65                                 0 29 IRQ_TYPE_LEVEL_HIGH
  66                                 0 30 IRQ_TYPE_LEVEL_HIGH>;
  67                 sense-bitfield-width = <2>;
  68         };
  69
  70         gpio0: gpio@ffc40000 {
  71                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  72                 reg = <0xffc40000 0x2c>;
  73                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  74                 #gpio-cells = <2>;
  75                 gpio-controller;
  76                 gpio-ranges = <&pfc 0 0 32>;
  77                 #interrupt-cells = <2>;
  78                 interrupt-controller;
  79         };
  80
  81         gpio1: gpio@ffc41000 {
  82                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  83                 reg = <0xffc41000 0x2c>;
  84                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 32 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90         };
  91
  92         gpio2: gpio@ffc42000 {
  93                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  94                 reg = <0xffc42000 0x2c>;
  95                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 64 32>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         gpio3: gpio@ffc43000 {
 104                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 105                 reg = <0xffc43000 0x2c>;
 106                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 107                 #gpio-cells = <2>;
 108                 gpio-controller;
 109                 gpio-ranges = <&pfc 0 96 32>;
 110                 #interrupt-cells = <2>;
 111                 interrupt-controller;
 112         };
 113
 114         gpio4: gpio@ffc44000 {
 115                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 116                 reg = <0xffc44000 0x2c>;
 117                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 128 27>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         pfc: pfc@fffc0000 {
 126                 compatible = "renesas,pfc-r8a7778";
 127                 reg = <0xfffc0000 0x118>;
 128         };
 129
 130         i2c0: i2c@ffc70000 {
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 compatible = "renesas,i2c-r8a7778";
 134                 reg = <0xffc70000 0x1000>;
 135                 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 136                 status = "disabled";
 137         };
 138
 139         i2c1: i2c@ffc71000 {
 140                 #address-cells = <1>;
 141                 #size-cells = <0>;
 142                 compatible = "renesas,i2c-r8a7778";
 143                 reg = <0xffc71000 0x1000>;
 144                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 145                 status = "disabled";
 146         };
 147
 148         i2c2: i2c@ffc72000 {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 compatible = "renesas,i2c-r8a7778";
 152                 reg = <0xffc72000 0x1000>;
 153                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
 154                 status = "disabled";
 155         };
 156
 157         i2c3: i2c@ffc73000 {
 158                 #address-cells = <1>;
 159                 #size-cells = <0>;
 160                 compatible = "renesas,i2c-r8a7778";
 161                 reg = <0xffc73000 0x1000>;
 162                 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
 163                 status = "disabled";
 164         };
 165
 166         tmu0: timer@ffd80000 {
 167                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 168                 reg = <0xffd80000 0x30>;
 169                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 170                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 171                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 172
 173                 #renesas,channels = <3>;
 174
 175                 status = "disabled";
 176         };
 177
 178         tmu1: timer@ffd81000 {
 179                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 180                 reg = <0xffd81000 0x30>;
 181                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 182                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 183                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                 #renesas,channels = <3>;
 186
 187                 status = "disabled";
 188         };
 189
 190         tmu2: timer@ffd82000 {
 191                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 192                 reg = <0xffd82000 0x30>;
 193                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 194                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 195                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 196
 197                 #renesas,channels = <3>;
 198
 199                 status = "disabled";
 200         };
 201
 202         scif0: serial@ffe40000 {
 203                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 204                 reg = <0xffe40000 0x100>;
 205                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
 206                 status = "disabled";
 207         };
 208
 209         scif1: serial@ffe41000 {
 210                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 211                 reg = <0xffe41000 0x100>;
 212                 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
 213                 status = "disabled";
 214         };
 215
 216         scif2: serial@ffe42000 {
 217                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 218                 reg = <0xffe42000 0x100>;
 219                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 220                 status = "disabled";
 221         };
 222
 223         scif3: serial@ffe43000 {
 224                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 225                 reg = <0xffe43000 0x100>;
 226                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 227                 status = "disabled";
 228         };
 229
 230         scif4: serial@ffe44000 {
 231                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 232                 reg = <0xffe44000 0x100>;
 233                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 234                 status = "disabled";
 235         };
 236
 237         scif5: serial@ffe45000 {
 238                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 239                 reg = <0xffe45000 0x100>;
 240                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 241                 status = "disabled";
 242         };
 243
 244         mmcif: mmc@ffe4e000 {
 245                 compatible = "renesas,sh-mmcif";
 246                 reg = <0xffe4e000 0x100>;
 247                 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 248                 status = "disabled";
 249         };
 250
 251         sdhi0: sd@ffe4c000 {
 252                 compatible = "renesas,sdhi-r8a7778";
 253                 reg = <0xffe4c000 0x100>;
 254                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
 255                 status = "disabled";
 256         };
 257
 258         sdhi1: sd@ffe4d000 {
 259                 compatible = "renesas,sdhi-r8a7778";
 260                 reg = <0xffe4d000 0x100>;
 261                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 262                 status = "disabled";
 263         };
 264
 265         sdhi2: sd@ffe4f000 {
 266                 compatible = "renesas,sdhi-r8a7778";
 267                 reg = <0xffe4f000 0x100>;
 268                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 269                 status = "disabled";
 270         };
 271
 272         hspi0: spi@fffc7000 {
 273                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 274                 reg = <0xfffc7000 0x18>;
 275                 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 status = "disabled";
 279         };
 280
 281         hspi1: spi@fffc8000 {
 282                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 283                 reg = <0xfffc8000 0x18>;
 284                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 status = "disabled";
 288         };
 289
 290         hspi2: spi@fffc6000 {
 291                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 292                 reg = <0xfffc6000 0x18>;
 293                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 status = "disabled";
 297         };
 298
 299         clocks {
 300                 #address-cells = <1>;
 301                 #size-cells = <1>;
 302                 ranges;
 303
 304                 /* External input clock */
 305                 extal_clk: extal_clk {
 306                         compatible = "fixed-clock";
 307                         #clock-cells = <0>;
 308                         clock-frequency = <0>;
 309                         clock-output-names = "extal";
 310                 };
 311
 312                 /* Special CPG clocks */
 313                 cpg_clocks: cpg_clocks@ffc80000 {
 314                         compatible = "renesas,r8a7778-cpg-clocks";
 315                         reg = <0xffc80000 0x80>;
 316                         #clock-cells = <1>;
 317                         clocks = <&extal_clk>;
 318                         clock-output-names = "plla", "pllb", "b",
 319                                              "out", "p", "s", "s1";
 320                 };
 321
 322                 /* Audio clocks; frequencies are set by boards if applicable. */
 323                 audio_clk_a: audio_clk_a {
 324                         compatible = "fixed-clock";
 325                         #clock-cells = <0>;
 326                         clock-output-names = "audio_clk_a";
 327                 };
 328                 audio_clk_b: audio_clk_b {
 329                         compatible = "fixed-clock";
 330                         #clock-cells = <0>;
 331                         clock-output-names = "audio_clk_b";
 332                 };
 333                 audio_clk_c: audio_clk_c {
 334                         compatible = "fixed-clock";
 335                         #clock-cells = <0>;
 336                         clock-output-names = "audio_clk_c";
 337                 };
 338
 339                 /* Fixed ratio clocks */
 340                 g_clk: g_clk {
 341                         compatible = "fixed-factor-clock";
 342                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 343                         #clock-cells = <0>;
 344                         clock-div = <12>;
 345                         clock-mult = <1>;
 346                         clock-output-names = "g";
 347                 };
 348                 i_clk: i_clk {
 349                         compatible = "fixed-factor-clock";
 350                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 351                         #clock-cells = <0>;
 352                         clock-div = <1>;
 353                         clock-mult = <1>;
 354                         clock-output-names = "i";
 355                 };
 356                 s3_clk: s3_clk {
 357                         compatible = "fixed-factor-clock";
 358                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 359                         #clock-cells = <0>;
 360                         clock-div = <4>;
 361                         clock-mult = <1>;
 362                         clock-output-names = "s3";
 363                 };
 364                 s4_clk: s4_clk {
 365                         compatible = "fixed-factor-clock";
 366                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 367                         #clock-cells = <0>;
 368                         clock-div = <8>;
 369                         clock-mult = <1>;
 370                         clock-output-names = "s4";
 371                 };
 372                 z_clk: z_clk {
 373                         compatible = "fixed-factor-clock";
 374                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 375                         #clock-cells = <0>;
 376                         clock-div = <1>;
 377                         clock-mult = <1>;
 378                         clock-output-names = "z";
 379                 };
 380
 381                 /* Gate clocks */
 382                 mstp0_clks: mstp0_clks@ffc80030 {
 383                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 384                         reg = <0xffc80030 4>;
 385                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 386                                  <&cpg_clocks R8A7778_CLK_P>,
 387                                  <&cpg_clocks R8A7778_CLK_P>,
 388                                  <&cpg_clocks R8A7778_CLK_P>,
 389                                  <&cpg_clocks R8A7778_CLK_P>,
 390                                  <&cpg_clocks R8A7778_CLK_P>,
 391                                  <&cpg_clocks R8A7778_CLK_P>,
 392                                  <&cpg_clocks R8A7778_CLK_P>,
 393                                  <&cpg_clocks R8A7778_CLK_P>,
 394                                  <&cpg_clocks R8A7778_CLK_P>,
 395                                  <&cpg_clocks R8A7778_CLK_P>,
 396                                  <&cpg_clocks R8A7778_CLK_P>,
 397                                  <&cpg_clocks R8A7778_CLK_P>,
 398                                  <&cpg_clocks R8A7778_CLK_P>,
 399                                  <&cpg_clocks R8A7778_CLK_P>,
 400                                  <&cpg_clocks R8A7778_CLK_P>,
 401                                  <&cpg_clocks R8A7778_CLK_P>,
 402                                  <&cpg_clocks R8A7778_CLK_P>,
 403                                  <&cpg_clocks R8A7778_CLK_S>;
 404                         #clock-cells = <1>;
 405                         clock-indices = <
 406                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 407                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 408                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 409                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 410                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 411                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 412                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 413                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 414                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 415                                 R8A7778_CLK_HSPI
 416                         >;
 417                         clock-output-names =
 418                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 419                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 420                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 421                                 "ssi2", "ssi3", "sru", "hspi";
 422                 };
 423                 mstp1_clks: mstp1_clks@ffc80034 {
 424                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 425                         reg = <0xffc80034 4>, <0xffc80044 4>;
 426                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 427                                  <&cpg_clocks R8A7778_CLK_S>,
 428                                  <&cpg_clocks R8A7778_CLK_S>,
 429                                  <&cpg_clocks R8A7778_CLK_P>;
 430                         #clock-cells = <1>;
 431                         clock-indices = <
 432                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 433                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 434                         >;
 435                         clock-output-names =
 436                                 "ether", "vin0", "vin1", "usb";
 437                 };
 438                 mstp3_clks: mstp3_clks@ffc8003c {
 439                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 440                         reg = <0xffc8003c 4>;
 441                         clocks = <&s4_clk>,
 442                                  <&cpg_clocks R8A7778_CLK_P>,
 443                                  <&cpg_clocks R8A7778_CLK_P>,
 444                                  <&cpg_clocks R8A7778_CLK_P>,
 445                                  <&cpg_clocks R8A7778_CLK_P>,
 446                                  <&cpg_clocks R8A7778_CLK_P>,
 447                                  <&cpg_clocks R8A7778_CLK_P>,
 448                                  <&cpg_clocks R8A7778_CLK_P>,
 449                                  <&cpg_clocks R8A7778_CLK_P>;
 450                         #clock-cells = <1>;
 451                         clock-indices = <
 452                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 453                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 454                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 455                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 456                                 R8A7778_CLK_SSI8
 457                         >;
 458                         clock-output-names =
 459                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 460                                 "ssi5", "ssi6", "ssi7", "ssi8";
 461                 };
 462                 mstp5_clks: mstp5_clks@ffc80054 {
 463                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 464                         reg = <0xffc80054 4>;
 465                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 466                                  <&cpg_clocks R8A7778_CLK_P>,
 467                                  <&cpg_clocks R8A7778_CLK_P>,
 468                                  <&cpg_clocks R8A7778_CLK_P>,
 469                                  <&cpg_clocks R8A7778_CLK_P>,
 470                                  <&cpg_clocks R8A7778_CLK_P>,
 471                                  <&cpg_clocks R8A7778_CLK_P>,
 472                                  <&cpg_clocks R8A7778_CLK_P>,
 473                                  <&cpg_clocks R8A7778_CLK_P>;
 474                         #clock-cells = <1>;
 475                         clock-indices = <
 476                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 477                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 478                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 479                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 480                                 R8A7778_CLK_SRU_SRC8
 481                         >;
 482                         clock-output-names =
 483                                 "sru-src0", "sru-src1", "sru-src2",
 484                                 "sru-src3", "sru-src4", "sru-src5",
 485                                 "sru-src6", "sru-src7", "sru-src8";
 486                 };
 487         };
 488 };