arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /include/ "skeleton.dtsi"
  18
  19 #include <dt-bindings/clock/r8a7778-clock.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "renesas,r8a7778";
  24         interrupt-parent = <&gic>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                         clock-frequency = <800000000>;
  35                 };
  36         };
  37
  38         aliases {
  39                 spi0 = &hspi0;
  40                 spi1 = &hspi1;
  41                 spi2 = &hspi2;
  42         };
  43
  44         ether: ethernet@fde00000 {
  45                 compatible = "renesas,ether-r8a7778";
  46                 reg = <0xfde00000 0x400>;
  47                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
  48                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  49                 phy-mode = "rmii";
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52                 status = "disabled";
  53         };
  54
  55         gic: interrupt-controller@fe438000 {
  56                 compatible = "arm,cortex-a9-gic";
  57                 #interrupt-cells = <3>;
  58                 interrupt-controller;
  59                 reg = <0xfe438000 0x1000>,
  60                       <0xfe430000 0x100>;
  61         };
  62
  63         /* irqpin: IRQ0 - IRQ3 */
  64         irqpin: irqpin@fe78001c {
  65                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  66                 #interrupt-cells = <2>;
  67                 interrupt-controller;
  68                 status = "disabled"; /* default off */
  69                 reg =   <0xfe78001c 4>,
  70                         <0xfe780010 4>,
  71                         <0xfe780024 4>,
  72                         <0xfe780044 4>,
  73                         <0xfe780064 4>;
  74                 interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
  75                                 0 28 IRQ_TYPE_LEVEL_HIGH
  76                                 0 29 IRQ_TYPE_LEVEL_HIGH
  77                                 0 30 IRQ_TYPE_LEVEL_HIGH>;
  78                 sense-bitfield-width = <2>;
  79         };
  80
  81         gpio0: gpio@ffc40000 {
  82                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  83                 reg = <0xffc40000 0x2c>;
  84                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 0 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90         };
  91
  92         gpio1: gpio@ffc41000 {
  93                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  94                 reg = <0xffc41000 0x2c>;
  95                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 32 32>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         gpio2: gpio@ffc42000 {
 104                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 105                 reg = <0xffc42000 0x2c>;
 106                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 107                 #gpio-cells = <2>;
 108                 gpio-controller;
 109                 gpio-ranges = <&pfc 0 64 32>;
 110                 #interrupt-cells = <2>;
 111                 interrupt-controller;
 112         };
 113
 114         gpio3: gpio@ffc43000 {
 115                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 116                 reg = <0xffc43000 0x2c>;
 117                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 96 32>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         gpio4: gpio@ffc44000 {
 126                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 127                 reg = <0xffc44000 0x2c>;
 128                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 128 27>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134         };
 135
 136         pfc: pfc@fffc0000 {
 137                 compatible = "renesas,pfc-r8a7778";
 138                 reg = <0xfffc0000 0x118>;
 139         };
 140
 141         i2c0: i2c@ffc70000 {
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144                 compatible = "renesas,i2c-r8a7778";
 145                 reg = <0xffc70000 0x1000>;
 146                 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 147                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 148                 status = "disabled";
 149         };
 150
 151         i2c1: i2c@ffc71000 {
 152                 #address-cells = <1>;
 153                 #size-cells = <0>;
 154                 compatible = "renesas,i2c-r8a7778";
 155                 reg = <0xffc71000 0x1000>;
 156                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 157                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 158                 status = "disabled";
 159         };
 160
 161         i2c2: i2c@ffc72000 {
 162                 #address-cells = <1>;
 163                 #size-cells = <0>;
 164                 compatible = "renesas,i2c-r8a7778";
 165                 reg = <0xffc72000 0x1000>;
 166                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
 167                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 168                 status = "disabled";
 169         };
 170
 171         i2c3: i2c@ffc73000 {
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 compatible = "renesas,i2c-r8a7778";
 175                 reg = <0xffc73000 0x1000>;
 176                 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 178                 status = "disabled";
 179         };
 180
 181         tmu0: timer@ffd80000 {
 182                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 183                 reg = <0xffd80000 0x30>;
 184                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 185                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 186                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 188                 clock-names = "fck";
 189
 190                 #renesas,channels = <3>;
 191
 192                 status = "disabled";
 193         };
 194
 195         tmu1: timer@ffd81000 {
 196                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 197                 reg = <0xffd81000 0x30>;
 198                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 200                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 202                 clock-names = "fck";
 203
 204                 #renesas,channels = <3>;
 205
 206                 status = "disabled";
 207         };
 208
 209         tmu2: timer@ffd82000 {
 210                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 211                 reg = <0xffd82000 0x30>;
 212                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 214                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 216                 clock-names = "fck";
 217
 218                 #renesas,channels = <3>;
 219
 220                 status = "disabled";
 221         };
 222
 223         scif0: serial@ffe40000 {
 224                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 225                 reg = <0xffe40000 0x100>;
 226                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
 228                 clock-names = "sci_ick";
 229                 status = "disabled";
 230         };
 231
 232         scif1: serial@ffe41000 {
 233                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 234                 reg = <0xffe41000 0x100>;
 235                 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
 237                 clock-names = "sci_ick";
 238                 status = "disabled";
 239         };
 240
 241         scif2: serial@ffe42000 {
 242                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 243                 reg = <0xffe42000 0x100>;
 244                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
 246                 clock-names = "sci_ick";
 247                 status = "disabled";
 248         };
 249
 250         scif3: serial@ffe43000 {
 251                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 252                 reg = <0xffe43000 0x100>;
 253                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
 255                 clock-names = "sci_ick";
 256                 status = "disabled";
 257         };
 258
 259         scif4: serial@ffe44000 {
 260                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 261                 reg = <0xffe44000 0x100>;
 262                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 263                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
 264                 clock-names = "sci_ick";
 265                 status = "disabled";
 266         };
 267
 268         scif5: serial@ffe45000 {
 269                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 270                 reg = <0xffe45000 0x100>;
 271                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 272                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
 273                 clock-names = "sci_ick";
 274                 status = "disabled";
 275         };
 276
 277         mmcif: mmc@ffe4e000 {
 278                 compatible = "renesas,sh-mmcif";
 279                 reg = <0xffe4e000 0x100>;
 280                 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 282                 status = "disabled";
 283         };
 284
 285         sdhi0: sd@ffe4c000 {
 286                 compatible = "renesas,sdhi-r8a7778";
 287                 reg = <0xffe4c000 0x100>;
 288                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 290                 status = "disabled";
 291         };
 292
 293         sdhi1: sd@ffe4d000 {
 294                 compatible = "renesas,sdhi-r8a7778";
 295                 reg = <0xffe4d000 0x100>;
 296                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 298                 status = "disabled";
 299         };
 300
 301         sdhi2: sd@ffe4f000 {
 302                 compatible = "renesas,sdhi-r8a7778";
 303                 reg = <0xffe4f000 0x100>;
 304                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 305                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 306                 status = "disabled";
 307         };
 308
 309         hspi0: spi@fffc7000 {
 310                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 311                 reg = <0xfffc7000 0x18>;
 312                 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 status = "disabled";
 317         };
 318
 319         hspi1: spi@fffc8000 {
 320                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 321                 reg = <0xfffc8000 0x18>;
 322                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 status = "disabled";
 327         };
 328
 329         hspi2: spi@fffc6000 {
 330                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 331                 reg = <0xfffc6000 0x18>;
 332                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 status = "disabled";
 337         };
 338
 339         clocks {
 340                 #address-cells = <1>;
 341                 #size-cells = <1>;
 342                 ranges;
 343
 344                 /* External input clock */
 345                 extal_clk: extal_clk {
 346                         compatible = "fixed-clock";
 347                         #clock-cells = <0>;
 348                         clock-frequency = <0>;
 349                         clock-output-names = "extal";
 350                 };
 351
 352                 /* Special CPG clocks */
 353                 cpg_clocks: cpg_clocks@ffc80000 {
 354                         compatible = "renesas,r8a7778-cpg-clocks";
 355                         reg = <0xffc80000 0x80>;
 356                         #clock-cells = <1>;
 357                         clocks = <&extal_clk>;
 358                         clock-output-names = "plla", "pllb", "b",
 359                                              "out", "p", "s", "s1";
 360                 };
 361
 362                 /* Audio clocks; frequencies are set by boards if applicable. */
 363                 audio_clk_a: audio_clk_a {
 364                         compatible = "fixed-clock";
 365                         #clock-cells = <0>;
 366                         clock-output-names = "audio_clk_a";
 367                 };
 368                 audio_clk_b: audio_clk_b {
 369                         compatible = "fixed-clock";
 370                         #clock-cells = <0>;
 371                         clock-output-names = "audio_clk_b";
 372                 };
 373                 audio_clk_c: audio_clk_c {
 374                         compatible = "fixed-clock";
 375                         #clock-cells = <0>;
 376                         clock-output-names = "audio_clk_c";
 377                 };
 378
 379                 /* Fixed ratio clocks */
 380                 g_clk: g_clk {
 381                         compatible = "fixed-factor-clock";
 382                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 383                         #clock-cells = <0>;
 384                         clock-div = <12>;
 385                         clock-mult = <1>;
 386                         clock-output-names = "g";
 387                 };
 388                 i_clk: i_clk {
 389                         compatible = "fixed-factor-clock";
 390                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 391                         #clock-cells = <0>;
 392                         clock-div = <1>;
 393                         clock-mult = <1>;
 394                         clock-output-names = "i";
 395                 };
 396                 s3_clk: s3_clk {
 397                         compatible = "fixed-factor-clock";
 398                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 399                         #clock-cells = <0>;
 400                         clock-div = <4>;
 401                         clock-mult = <1>;
 402                         clock-output-names = "s3";
 403                 };
 404                 s4_clk: s4_clk {
 405                         compatible = "fixed-factor-clock";
 406                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 407                         #clock-cells = <0>;
 408                         clock-div = <8>;
 409                         clock-mult = <1>;
 410                         clock-output-names = "s4";
 411                 };
 412                 z_clk: z_clk {
 413                         compatible = "fixed-factor-clock";
 414                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 415                         #clock-cells = <0>;
 416                         clock-div = <1>;
 417                         clock-mult = <1>;
 418                         clock-output-names = "z";
 419                 };
 420
 421                 /* Gate clocks */
 422                 mstp0_clks: mstp0_clks@ffc80030 {
 423                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 424                         reg = <0xffc80030 4>;
 425                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 426                                  <&cpg_clocks R8A7778_CLK_P>,
 427                                  <&cpg_clocks R8A7778_CLK_P>,
 428                                  <&cpg_clocks R8A7778_CLK_P>,
 429                                  <&cpg_clocks R8A7778_CLK_P>,
 430                                  <&cpg_clocks R8A7778_CLK_P>,
 431                                  <&cpg_clocks R8A7778_CLK_P>,
 432                                  <&cpg_clocks R8A7778_CLK_P>,
 433                                  <&cpg_clocks R8A7778_CLK_P>,
 434                                  <&cpg_clocks R8A7778_CLK_P>,
 435                                  <&cpg_clocks R8A7778_CLK_P>,
 436                                  <&cpg_clocks R8A7778_CLK_P>,
 437                                  <&cpg_clocks R8A7778_CLK_P>,
 438                                  <&cpg_clocks R8A7778_CLK_P>,
 439                                  <&cpg_clocks R8A7778_CLK_P>,
 440                                  <&cpg_clocks R8A7778_CLK_P>,
 441                                  <&cpg_clocks R8A7778_CLK_P>,
 442                                  <&cpg_clocks R8A7778_CLK_P>,
 443                                  <&cpg_clocks R8A7778_CLK_S>;
 444                         #clock-cells = <1>;
 445                         clock-indices = <
 446                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 447                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 448                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 449                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 450                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 451                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 452                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 453                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 454                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 455                                 R8A7778_CLK_HSPI
 456                         >;
 457                         clock-output-names =
 458                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 459                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 460                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 461                                 "ssi2", "ssi3", "sru", "hspi";
 462                 };
 463                 mstp1_clks: mstp1_clks@ffc80034 {
 464                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 465                         reg = <0xffc80034 4>, <0xffc80044 4>;
 466                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 467                                  <&cpg_clocks R8A7778_CLK_S>,
 468                                  <&cpg_clocks R8A7778_CLK_S>,
 469                                  <&cpg_clocks R8A7778_CLK_P>;
 470                         #clock-cells = <1>;
 471                         clock-indices = <
 472                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 473                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 474                         >;
 475                         clock-output-names =
 476                                 "ether", "vin0", "vin1", "usb";
 477                 };
 478                 mstp3_clks: mstp3_clks@ffc8003c {
 479                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 480                         reg = <0xffc8003c 4>;
 481                         clocks = <&s4_clk>,
 482                                  <&cpg_clocks R8A7778_CLK_P>,
 483                                  <&cpg_clocks R8A7778_CLK_P>,
 484                                  <&cpg_clocks R8A7778_CLK_P>,
 485                                  <&cpg_clocks R8A7778_CLK_P>,
 486                                  <&cpg_clocks R8A7778_CLK_P>,
 487                                  <&cpg_clocks R8A7778_CLK_P>,
 488                                  <&cpg_clocks R8A7778_CLK_P>,
 489                                  <&cpg_clocks R8A7778_CLK_P>;
 490                         #clock-cells = <1>;
 491                         clock-indices = <
 492                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 493                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 494                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 495                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 496                                 R8A7778_CLK_SSI8
 497                         >;
 498                         clock-output-names =
 499                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 500                                 "ssi5", "ssi6", "ssi7", "ssi8";
 501                 };
 502                 mstp5_clks: mstp5_clks@ffc80054 {
 503                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 504                         reg = <0xffc80054 4>;
 505                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 506                                  <&cpg_clocks R8A7778_CLK_P>,
 507                                  <&cpg_clocks R8A7778_CLK_P>,
 508                                  <&cpg_clocks R8A7778_CLK_P>,
 509                                  <&cpg_clocks R8A7778_CLK_P>,
 510                                  <&cpg_clocks R8A7778_CLK_P>,
 511                                  <&cpg_clocks R8A7778_CLK_P>,
 512                                  <&cpg_clocks R8A7778_CLK_P>,
 513                                  <&cpg_clocks R8A7778_CLK_P>;
 514                         #clock-cells = <1>;
 515                         clock-indices = <
 516                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 517                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 518                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 519                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 520                                 R8A7778_CLK_SRU_SRC8
 521                         >;
 522                         clock-output-names =
 523                                 "sru-src0", "sru-src1", "sru-src2",
 524                                 "sru-src3", "sru-src4", "sru-src5",
 525                                 "sru-src6", "sru-src7", "sru-src8";
 526                 };
 527         };
 528 };