2 * Device Tree Source for Renesas r8a7778
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 * Copyright (C) 2013 Renesas Solutions Corp.
10 * Copyright (C) 2013 Simon Horman
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
17 /include/ "skeleton.dtsi"
19 #include <dt-bindings/clock/r8a7778-clock.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
23 compatible = "renesas,r8a7778";
24 interrupt-parent = <&gic>;
32 compatible = "arm,cortex-a9";
34 clock-frequency = <800000000>;
45 compatible = "simple-bus";
48 ranges = <0 0 0x1c000000>;
51 ether: ethernet@fde00000 {
52 compatible = "renesas,ether-r8a7778";
53 reg = <0xfde00000 0x400>;
54 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
62 gic: interrupt-controller@fe438000 {
63 compatible = "arm,cortex-a9-gic";
64 #interrupt-cells = <3>;
66 reg = <0xfe438000 0x1000>,
70 /* irqpin: IRQ0 - IRQ3 */
71 irqpin: irqpin@fe78001c {
72 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
73 #interrupt-cells = <2>;
75 status = "disabled"; /* default off */
81 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
82 0 28 IRQ_TYPE_LEVEL_HIGH
83 0 29 IRQ_TYPE_LEVEL_HIGH
84 0 30 IRQ_TYPE_LEVEL_HIGH>;
85 sense-bitfield-width = <2>;
88 gpio0: gpio@ffc40000 {
89 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
90 reg = <0xffc40000 0x2c>;
91 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
94 gpio-ranges = <&pfc 0 0 32>;
95 #interrupt-cells = <2>;
99 gpio1: gpio@ffc41000 {
100 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
101 reg = <0xffc41000 0x2c>;
102 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
105 gpio-ranges = <&pfc 0 32 32>;
106 #interrupt-cells = <2>;
107 interrupt-controller;
110 gpio2: gpio@ffc42000 {
111 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
112 reg = <0xffc42000 0x2c>;
113 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
116 gpio-ranges = <&pfc 0 64 32>;
117 #interrupt-cells = <2>;
118 interrupt-controller;
121 gpio3: gpio@ffc43000 {
122 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
123 reg = <0xffc43000 0x2c>;
124 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
127 gpio-ranges = <&pfc 0 96 32>;
128 #interrupt-cells = <2>;
129 interrupt-controller;
132 gpio4: gpio@ffc44000 {
133 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
134 reg = <0xffc44000 0x2c>;
135 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
138 gpio-ranges = <&pfc 0 128 27>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
144 compatible = "renesas,pfc-r8a7778";
145 reg = <0xfffc0000 0x118>;
149 #address-cells = <1>;
151 compatible = "renesas,i2c-r8a7778";
152 reg = <0xffc70000 0x1000>;
153 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
159 #address-cells = <1>;
161 compatible = "renesas,i2c-r8a7778";
162 reg = <0xffc71000 0x1000>;
163 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
169 #address-cells = <1>;
171 compatible = "renesas,i2c-r8a7778";
172 reg = <0xffc72000 0x1000>;
173 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
179 #address-cells = <1>;
181 compatible = "renesas,i2c-r8a7778";
182 reg = <0xffc73000 0x1000>;
183 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
188 tmu0: timer@ffd80000 {
189 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
190 reg = <0xffd80000 0x30>;
191 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
192 <0 33 IRQ_TYPE_LEVEL_HIGH>,
193 <0 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
197 #renesas,channels = <3>;
202 tmu1: timer@ffd81000 {
203 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
204 reg = <0xffd81000 0x30>;
205 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
206 <0 37 IRQ_TYPE_LEVEL_HIGH>,
207 <0 38 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
211 #renesas,channels = <3>;
216 tmu2: timer@ffd82000 {
217 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
218 reg = <0xffd82000 0x30>;
219 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
220 <0 41 IRQ_TYPE_LEVEL_HIGH>,
221 <0 42 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
225 #renesas,channels = <3>;
230 scif0: serial@ffe40000 {
231 compatible = "renesas,scif-r8a7778", "renesas,scif";
232 reg = <0xffe40000 0x100>;
233 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
235 clock-names = "sci_ick";
239 scif1: serial@ffe41000 {
240 compatible = "renesas,scif-r8a7778", "renesas,scif";
241 reg = <0xffe41000 0x100>;
242 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
244 clock-names = "sci_ick";
248 scif2: serial@ffe42000 {
249 compatible = "renesas,scif-r8a7778", "renesas,scif";
250 reg = <0xffe42000 0x100>;
251 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
253 clock-names = "sci_ick";
257 scif3: serial@ffe43000 {
258 compatible = "renesas,scif-r8a7778", "renesas,scif";
259 reg = <0xffe43000 0x100>;
260 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
262 clock-names = "sci_ick";
266 scif4: serial@ffe44000 {
267 compatible = "renesas,scif-r8a7778", "renesas,scif";
268 reg = <0xffe44000 0x100>;
269 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
271 clock-names = "sci_ick";
275 scif5: serial@ffe45000 {
276 compatible = "renesas,scif-r8a7778", "renesas,scif";
277 reg = <0xffe45000 0x100>;
278 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
280 clock-names = "sci_ick";
284 mmcif: mmc@ffe4e000 {
285 compatible = "renesas,sh-mmcif";
286 reg = <0xffe4e000 0x100>;
287 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
293 compatible = "renesas,sdhi-r8a7778";
294 reg = <0xffe4c000 0x100>;
295 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
301 compatible = "renesas,sdhi-r8a7778";
302 reg = <0xffe4d000 0x100>;
303 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
309 compatible = "renesas,sdhi-r8a7778";
310 reg = <0xffe4f000 0x100>;
311 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
316 hspi0: spi@fffc7000 {
317 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
318 reg = <0xfffc7000 0x18>;
319 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
321 #address-cells = <1>;
326 hspi1: spi@fffc8000 {
327 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
328 reg = <0xfffc8000 0x18>;
329 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
331 #address-cells = <1>;
336 hspi2: spi@fffc6000 {
337 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
338 reg = <0xfffc6000 0x18>;
339 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
341 #address-cells = <1>;
347 #address-cells = <1>;
351 /* External input clock */
352 extal_clk: extal_clk {
353 compatible = "fixed-clock";
355 clock-frequency = <0>;
356 clock-output-names = "extal";
359 /* Special CPG clocks */
360 cpg_clocks: cpg_clocks@ffc80000 {
361 compatible = "renesas,r8a7778-cpg-clocks";
362 reg = <0xffc80000 0x80>;
364 clocks = <&extal_clk>;
365 clock-output-names = "plla", "pllb", "b",
366 "out", "p", "s", "s1";
369 /* Audio clocks; frequencies are set by boards if applicable. */
370 audio_clk_a: audio_clk_a {
371 compatible = "fixed-clock";
373 clock-output-names = "audio_clk_a";
375 audio_clk_b: audio_clk_b {
376 compatible = "fixed-clock";
378 clock-output-names = "audio_clk_b";
380 audio_clk_c: audio_clk_c {
381 compatible = "fixed-clock";
383 clock-output-names = "audio_clk_c";
386 /* Fixed ratio clocks */
388 compatible = "fixed-factor-clock";
389 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
393 clock-output-names = "g";
396 compatible = "fixed-factor-clock";
397 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
401 clock-output-names = "i";
404 compatible = "fixed-factor-clock";
405 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
409 clock-output-names = "s3";
412 compatible = "fixed-factor-clock";
413 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
417 clock-output-names = "s4";
420 compatible = "fixed-factor-clock";
421 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
425 clock-output-names = "z";
429 mstp0_clks: mstp0_clks@ffc80030 {
430 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
431 reg = <0xffc80030 4>;
432 clocks = <&cpg_clocks R8A7778_CLK_P>,
433 <&cpg_clocks R8A7778_CLK_P>,
434 <&cpg_clocks R8A7778_CLK_P>,
435 <&cpg_clocks R8A7778_CLK_P>,
436 <&cpg_clocks R8A7778_CLK_P>,
437 <&cpg_clocks R8A7778_CLK_P>,
438 <&cpg_clocks R8A7778_CLK_P>,
439 <&cpg_clocks R8A7778_CLK_P>,
440 <&cpg_clocks R8A7778_CLK_P>,
441 <&cpg_clocks R8A7778_CLK_P>,
442 <&cpg_clocks R8A7778_CLK_P>,
443 <&cpg_clocks R8A7778_CLK_P>,
444 <&cpg_clocks R8A7778_CLK_P>,
445 <&cpg_clocks R8A7778_CLK_P>,
446 <&cpg_clocks R8A7778_CLK_P>,
447 <&cpg_clocks R8A7778_CLK_P>,
448 <&cpg_clocks R8A7778_CLK_P>,
449 <&cpg_clocks R8A7778_CLK_P>,
450 <&cpg_clocks R8A7778_CLK_S>;
453 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
454 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
455 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
456 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
457 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
458 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
459 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
460 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
461 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
465 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
466 "scif1", "scif2", "scif3", "scif4", "scif5",
467 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
468 "ssi2", "ssi3", "sru", "hspi";
470 mstp1_clks: mstp1_clks@ffc80034 {
471 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
472 reg = <0xffc80034 4>, <0xffc80044 4>;
473 clocks = <&cpg_clocks R8A7778_CLK_P>,
474 <&cpg_clocks R8A7778_CLK_S>,
475 <&cpg_clocks R8A7778_CLK_S>,
476 <&cpg_clocks R8A7778_CLK_P>;
479 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
480 R8A7778_CLK_VIN1 R8A7778_CLK_USB
483 "ether", "vin0", "vin1", "usb";
485 mstp3_clks: mstp3_clks@ffc8003c {
486 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
487 reg = <0xffc8003c 4>;
489 <&cpg_clocks R8A7778_CLK_P>,
490 <&cpg_clocks R8A7778_CLK_P>,
491 <&cpg_clocks R8A7778_CLK_P>,
492 <&cpg_clocks R8A7778_CLK_P>,
493 <&cpg_clocks R8A7778_CLK_P>,
494 <&cpg_clocks R8A7778_CLK_P>,
495 <&cpg_clocks R8A7778_CLK_P>,
496 <&cpg_clocks R8A7778_CLK_P>;
499 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
500 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
501 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
502 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
506 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
507 "ssi5", "ssi6", "ssi7", "ssi8";
509 mstp5_clks: mstp5_clks@ffc80054 {
510 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
511 reg = <0xffc80054 4>;
512 clocks = <&cpg_clocks R8A7778_CLK_P>,
513 <&cpg_clocks R8A7778_CLK_P>,
514 <&cpg_clocks R8A7778_CLK_P>,
515 <&cpg_clocks R8A7778_CLK_P>,
516 <&cpg_clocks R8A7778_CLK_P>,
517 <&cpg_clocks R8A7778_CLK_P>,
518 <&cpg_clocks R8A7778_CLK_P>,
519 <&cpg_clocks R8A7778_CLK_P>,
520 <&cpg_clocks R8A7778_CLK_P>;
523 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
524 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
525 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
526 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
530 "sru-src0", "sru-src1", "sru-src2",
531 "sru-src3", "sru-src4", "sru-src5",
532 "sru-src6", "sru-src7", "sru-src8";