arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /include/ "skeleton.dtsi"
  18
  19 #include <dt-bindings/clock/r8a7778-clock.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "renesas,r8a7778";
  24         interrupt-parent = <&gic>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                         clock-frequency = <800000000>;
  35                 };
  36         };
  37
  38         aliases {
  39                 spi0 = &hspi0;
  40                 spi1 = &hspi1;
  41                 spi2 = &hspi2;
  42         };
  43
  44         bsc: bus@1c000000 {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0 0 0x1c000000>;
  49         };
  50
  51         ether: ethernet@fde00000 {
  52                 compatible = "renesas,ether-r8a7778";
  53                 reg = <0xfde00000 0x400>;
  54                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  56                 phy-mode = "rmii";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 status = "disabled";
  60         };
  61
  62         gic: interrupt-controller@fe438000 {
  63                 compatible = "arm,cortex-a9-gic";
  64                 #interrupt-cells = <3>;
  65                 interrupt-controller;
  66                 reg = <0xfe438000 0x1000>,
  67                       <0xfe430000 0x100>;
  68         };
  69
  70         /* irqpin: IRQ0 - IRQ3 */
  71         irqpin: irqpin@fe78001c {
  72                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  73                 #interrupt-cells = <2>;
  74                 interrupt-controller;
  75                 status = "disabled"; /* default off */
  76                 reg =   <0xfe78001c 4>,
  77                         <0xfe780010 4>,
  78                         <0xfe780024 4>,
  79                         <0xfe780044 4>,
  80                         <0xfe780064 4>;
  81                 interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
  82                                 0 28 IRQ_TYPE_LEVEL_HIGH
  83                                 0 29 IRQ_TYPE_LEVEL_HIGH
  84                                 0 30 IRQ_TYPE_LEVEL_HIGH>;
  85                 sense-bitfield-width = <2>;
  86         };
  87
  88         gpio0: gpio@ffc40000 {
  89                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  90                 reg = <0xffc40000 0x2c>;
  91                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  92                 #gpio-cells = <2>;
  93                 gpio-controller;
  94                 gpio-ranges = <&pfc 0 0 32>;
  95                 #interrupt-cells = <2>;
  96                 interrupt-controller;
  97         };
  98
  99         gpio1: gpio@ffc41000 {
 100                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 101                 reg = <0xffc41000 0x2c>;
 102                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 103                 #gpio-cells = <2>;
 104                 gpio-controller;
 105                 gpio-ranges = <&pfc 0 32 32>;
 106                 #interrupt-cells = <2>;
 107                 interrupt-controller;
 108         };
 109
 110         gpio2: gpio@ffc42000 {
 111                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 112                 reg = <0xffc42000 0x2c>;
 113                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 114                 #gpio-cells = <2>;
 115                 gpio-controller;
 116                 gpio-ranges = <&pfc 0 64 32>;
 117                 #interrupt-cells = <2>;
 118                 interrupt-controller;
 119         };
 120
 121         gpio3: gpio@ffc43000 {
 122                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 123                 reg = <0xffc43000 0x2c>;
 124                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 125                 #gpio-cells = <2>;
 126                 gpio-controller;
 127                 gpio-ranges = <&pfc 0 96 32>;
 128                 #interrupt-cells = <2>;
 129                 interrupt-controller;
 130         };
 131
 132         gpio4: gpio@ffc44000 {
 133                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 134                 reg = <0xffc44000 0x2c>;
 135                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 27>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141         };
 142
 143         pfc: pfc@fffc0000 {
 144                 compatible = "renesas,pfc-r8a7778";
 145                 reg = <0xfffc0000 0x118>;
 146         };
 147
 148         i2c0: i2c@ffc70000 {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 compatible = "renesas,i2c-r8a7778";
 152                 reg = <0xffc70000 0x1000>;
 153                 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 155                 status = "disabled";
 156         };
 157
 158         i2c1: i2c@ffc71000 {
 159                 #address-cells = <1>;
 160                 #size-cells = <0>;
 161                 compatible = "renesas,i2c-r8a7778";
 162                 reg = <0xffc71000 0x1000>;
 163                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 164                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 165                 status = "disabled";
 166         };
 167
 168         i2c2: i2c@ffc72000 {
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 compatible = "renesas,i2c-r8a7778";
 172                 reg = <0xffc72000 0x1000>;
 173                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
 174                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 175                 status = "disabled";
 176         };
 177
 178         i2c3: i2c@ffc73000 {
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 compatible = "renesas,i2c-r8a7778";
 182                 reg = <0xffc73000 0x1000>;
 183                 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 185                 status = "disabled";
 186         };
 187
 188         tmu0: timer@ffd80000 {
 189                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 190                 reg = <0xffd80000 0x30>;
 191                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 192                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 193                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 195                 clock-names = "fck";
 196
 197                 #renesas,channels = <3>;
 198
 199                 status = "disabled";
 200         };
 201
 202         tmu1: timer@ffd81000 {
 203                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 204                 reg = <0xffd81000 0x30>;
 205                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 206                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 207                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 208                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 209                 clock-names = "fck";
 210
 211                 #renesas,channels = <3>;
 212
 213                 status = "disabled";
 214         };
 215
 216         tmu2: timer@ffd82000 {
 217                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 218                 reg = <0xffd82000 0x30>;
 219                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 220                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 221                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 223                 clock-names = "fck";
 224
 225                 #renesas,channels = <3>;
 226
 227                 status = "disabled";
 228         };
 229
 230         scif0: serial@ffe40000 {
 231                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 232                 reg = <0xffe40000 0x100>;
 233                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
 235                 clock-names = "sci_ick";
 236                 status = "disabled";
 237         };
 238
 239         scif1: serial@ffe41000 {
 240                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 241                 reg = <0xffe41000 0x100>;
 242                 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
 244                 clock-names = "sci_ick";
 245                 status = "disabled";
 246         };
 247
 248         scif2: serial@ffe42000 {
 249                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 250                 reg = <0xffe42000 0x100>;
 251                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 252                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
 253                 clock-names = "sci_ick";
 254                 status = "disabled";
 255         };
 256
 257         scif3: serial@ffe43000 {
 258                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 259                 reg = <0xffe43000 0x100>;
 260                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
 262                 clock-names = "sci_ick";
 263                 status = "disabled";
 264         };
 265
 266         scif4: serial@ffe44000 {
 267                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 268                 reg = <0xffe44000 0x100>;
 269                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
 271                 clock-names = "sci_ick";
 272                 status = "disabled";
 273         };
 274
 275         scif5: serial@ffe45000 {
 276                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 277                 reg = <0xffe45000 0x100>;
 278                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
 280                 clock-names = "sci_ick";
 281                 status = "disabled";
 282         };
 283
 284         mmcif: mmc@ffe4e000 {
 285                 compatible = "renesas,sh-mmcif";
 286                 reg = <0xffe4e000 0x100>;
 287                 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 289                 status = "disabled";
 290         };
 291
 292         sdhi0: sd@ffe4c000 {
 293                 compatible = "renesas,sdhi-r8a7778";
 294                 reg = <0xffe4c000 0x100>;
 295                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 297                 status = "disabled";
 298         };
 299
 300         sdhi1: sd@ffe4d000 {
 301                 compatible = "renesas,sdhi-r8a7778";
 302                 reg = <0xffe4d000 0x100>;
 303                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 305                 status = "disabled";
 306         };
 307
 308         sdhi2: sd@ffe4f000 {
 309                 compatible = "renesas,sdhi-r8a7778";
 310                 reg = <0xffe4f000 0x100>;
 311                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 313                 status = "disabled";
 314         };
 315
 316         hspi0: spi@fffc7000 {
 317                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 318                 reg = <0xfffc7000 0x18>;
 319                 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 status = "disabled";
 324         };
 325
 326         hspi1: spi@fffc8000 {
 327                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 328                 reg = <0xfffc8000 0x18>;
 329                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         hspi2: spi@fffc6000 {
 337                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 338                 reg = <0xfffc6000 0x18>;
 339                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 status = "disabled";
 344         };
 345
 346         clocks {
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349                 ranges;
 350
 351                 /* External input clock */
 352                 extal_clk: extal_clk {
 353                         compatible = "fixed-clock";
 354                         #clock-cells = <0>;
 355                         clock-frequency = <0>;
 356                         clock-output-names = "extal";
 357                 };
 358
 359                 /* Special CPG clocks */
 360                 cpg_clocks: cpg_clocks@ffc80000 {
 361                         compatible = "renesas,r8a7778-cpg-clocks";
 362                         reg = <0xffc80000 0x80>;
 363                         #clock-cells = <1>;
 364                         clocks = <&extal_clk>;
 365                         clock-output-names = "plla", "pllb", "b",
 366                                              "out", "p", "s", "s1";
 367                 };
 368
 369                 /* Audio clocks; frequencies are set by boards if applicable. */
 370                 audio_clk_a: audio_clk_a {
 371                         compatible = "fixed-clock";
 372                         #clock-cells = <0>;
 373                         clock-output-names = "audio_clk_a";
 374                 };
 375                 audio_clk_b: audio_clk_b {
 376                         compatible = "fixed-clock";
 377                         #clock-cells = <0>;
 378                         clock-output-names = "audio_clk_b";
 379                 };
 380                 audio_clk_c: audio_clk_c {
 381                         compatible = "fixed-clock";
 382                         #clock-cells = <0>;
 383                         clock-output-names = "audio_clk_c";
 384                 };
 385
 386                 /* Fixed ratio clocks */
 387                 g_clk: g_clk {
 388                         compatible = "fixed-factor-clock";
 389                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 390                         #clock-cells = <0>;
 391                         clock-div = <12>;
 392                         clock-mult = <1>;
 393                         clock-output-names = "g";
 394                 };
 395                 i_clk: i_clk {
 396                         compatible = "fixed-factor-clock";
 397                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 398                         #clock-cells = <0>;
 399                         clock-div = <1>;
 400                         clock-mult = <1>;
 401                         clock-output-names = "i";
 402                 };
 403                 s3_clk: s3_clk {
 404                         compatible = "fixed-factor-clock";
 405                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 406                         #clock-cells = <0>;
 407                         clock-div = <4>;
 408                         clock-mult = <1>;
 409                         clock-output-names = "s3";
 410                 };
 411                 s4_clk: s4_clk {
 412                         compatible = "fixed-factor-clock";
 413                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 414                         #clock-cells = <0>;
 415                         clock-div = <8>;
 416                         clock-mult = <1>;
 417                         clock-output-names = "s4";
 418                 };
 419                 z_clk: z_clk {
 420                         compatible = "fixed-factor-clock";
 421                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 422                         #clock-cells = <0>;
 423                         clock-div = <1>;
 424                         clock-mult = <1>;
 425                         clock-output-names = "z";
 426                 };
 427
 428                 /* Gate clocks */
 429                 mstp0_clks: mstp0_clks@ffc80030 {
 430                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 431                         reg = <0xffc80030 4>;
 432                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 433                                  <&cpg_clocks R8A7778_CLK_P>,
 434                                  <&cpg_clocks R8A7778_CLK_P>,
 435                                  <&cpg_clocks R8A7778_CLK_P>,
 436                                  <&cpg_clocks R8A7778_CLK_P>,
 437                                  <&cpg_clocks R8A7778_CLK_P>,
 438                                  <&cpg_clocks R8A7778_CLK_P>,
 439                                  <&cpg_clocks R8A7778_CLK_P>,
 440                                  <&cpg_clocks R8A7778_CLK_P>,
 441                                  <&cpg_clocks R8A7778_CLK_P>,
 442                                  <&cpg_clocks R8A7778_CLK_P>,
 443                                  <&cpg_clocks R8A7778_CLK_P>,
 444                                  <&cpg_clocks R8A7778_CLK_P>,
 445                                  <&cpg_clocks R8A7778_CLK_P>,
 446                                  <&cpg_clocks R8A7778_CLK_P>,
 447                                  <&cpg_clocks R8A7778_CLK_P>,
 448                                  <&cpg_clocks R8A7778_CLK_P>,
 449                                  <&cpg_clocks R8A7778_CLK_P>,
 450                                  <&cpg_clocks R8A7778_CLK_S>;
 451                         #clock-cells = <1>;
 452                         clock-indices = <
 453                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 454                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 455                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 456                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 457                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 458                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 459                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 460                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 461                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 462                                 R8A7778_CLK_HSPI
 463                         >;
 464                         clock-output-names =
 465                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 466                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 467                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 468                                 "ssi2", "ssi3", "sru", "hspi";
 469                 };
 470                 mstp1_clks: mstp1_clks@ffc80034 {
 471                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 472                         reg = <0xffc80034 4>, <0xffc80044 4>;
 473                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 474                                  <&cpg_clocks R8A7778_CLK_S>,
 475                                  <&cpg_clocks R8A7778_CLK_S>,
 476                                  <&cpg_clocks R8A7778_CLK_P>;
 477                         #clock-cells = <1>;
 478                         clock-indices = <
 479                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 480                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 481                         >;
 482                         clock-output-names =
 483                                 "ether", "vin0", "vin1", "usb";
 484                 };
 485                 mstp3_clks: mstp3_clks@ffc8003c {
 486                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 487                         reg = <0xffc8003c 4>;
 488                         clocks = <&s4_clk>,
 489                                  <&cpg_clocks R8A7778_CLK_P>,
 490                                  <&cpg_clocks R8A7778_CLK_P>,
 491                                  <&cpg_clocks R8A7778_CLK_P>,
 492                                  <&cpg_clocks R8A7778_CLK_P>,
 493                                  <&cpg_clocks R8A7778_CLK_P>,
 494                                  <&cpg_clocks R8A7778_CLK_P>,
 495                                  <&cpg_clocks R8A7778_CLK_P>,
 496                                  <&cpg_clocks R8A7778_CLK_P>;
 497                         #clock-cells = <1>;
 498                         clock-indices = <
 499                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 500                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 501                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 502                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 503                                 R8A7778_CLK_SSI8
 504                         >;
 505                         clock-output-names =
 506                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 507                                 "ssi5", "ssi6", "ssi7", "ssi8";
 508                 };
 509                 mstp5_clks: mstp5_clks@ffc80054 {
 510                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 511                         reg = <0xffc80054 4>;
 512                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 513                                  <&cpg_clocks R8A7778_CLK_P>,
 514                                  <&cpg_clocks R8A7778_CLK_P>,
 515                                  <&cpg_clocks R8A7778_CLK_P>,
 516                                  <&cpg_clocks R8A7778_CLK_P>,
 517                                  <&cpg_clocks R8A7778_CLK_P>,
 518                                  <&cpg_clocks R8A7778_CLK_P>,
 519                                  <&cpg_clocks R8A7778_CLK_P>,
 520                                  <&cpg_clocks R8A7778_CLK_P>;
 521                         #clock-cells = <1>;
 522                         clock-indices = <
 523                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 524                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 525                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 526                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 527                                 R8A7778_CLK_SRU_SRC8
 528                         >;
 529                         clock-output-names =
 530                                 "sru-src0", "sru-src1", "sru-src2",
 531                                 "sru-src3", "sru-src4", "sru-src5",
 532                                 "sru-src6", "sru-src7", "sru-src8";
 533                 };
 534         };
 535 };