arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /include/ "skeleton.dtsi"
  18
  19 #include <dt-bindings/clock/r8a7778-clock.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "renesas,r8a7778";
  24         interrupt-parent = <&gic>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                         clock-frequency = <800000000>;
  35                 };
  36         };
  37
  38         aliases {
  39                 spi0 = &hspi0;
  40                 spi1 = &hspi1;
  41                 spi2 = &hspi2;
  42         };
  43
  44         gic: interrupt-controller@fe438000 {
  45                 compatible = "arm,cortex-a9-gic";
  46                 #interrupt-cells = <3>;
  47                 interrupt-controller;
  48                 reg = <0xfe438000 0x1000>,
  49                       <0xfe430000 0x100>;
  50         };
  51
  52         /* irqpin: IRQ0 - IRQ3 */
  53         irqpin: irqpin@fe78001c {
  54                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  55                 #interrupt-cells = <2>;
  56                 interrupt-controller;
  57                 status = "disabled"; /* default off */
  58                 reg =   <0xfe78001c 4>,
  59                         <0xfe780010 4>,
  60                         <0xfe780024 4>,
  61                         <0xfe780044 4>,
  62                         <0xfe780064 4>;
  63                 interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
  64                                 0 28 IRQ_TYPE_LEVEL_HIGH
  65                                 0 29 IRQ_TYPE_LEVEL_HIGH
  66                                 0 30 IRQ_TYPE_LEVEL_HIGH>;
  67                 sense-bitfield-width = <2>;
  68         };
  69
  70         gpio0: gpio@ffc40000 {
  71                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  72                 reg = <0xffc40000 0x2c>;
  73                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  74                 #gpio-cells = <2>;
  75                 gpio-controller;
  76                 gpio-ranges = <&pfc 0 0 32>;
  77                 #interrupt-cells = <2>;
  78                 interrupt-controller;
  79         };
  80
  81         gpio1: gpio@ffc41000 {
  82                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  83                 reg = <0xffc41000 0x2c>;
  84                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 32 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90         };
  91
  92         gpio2: gpio@ffc42000 {
  93                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  94                 reg = <0xffc42000 0x2c>;
  95                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 64 32>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         gpio3: gpio@ffc43000 {
 104                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 105                 reg = <0xffc43000 0x2c>;
 106                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 107                 #gpio-cells = <2>;
 108                 gpio-controller;
 109                 gpio-ranges = <&pfc 0 96 32>;
 110                 #interrupt-cells = <2>;
 111                 interrupt-controller;
 112         };
 113
 114         gpio4: gpio@ffc44000 {
 115                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 116                 reg = <0xffc44000 0x2c>;
 117                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 128 27>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         pfc: pfc@fffc0000 {
 126                 compatible = "renesas,pfc-r8a7778";
 127                 reg = <0xfffc0000 0x118>;
 128         };
 129
 130         i2c0: i2c@ffc70000 {
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 compatible = "renesas,i2c-r8a7778";
 134                 reg = <0xffc70000 0x1000>;
 135                 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 136                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 137                 status = "disabled";
 138         };
 139
 140         i2c1: i2c@ffc71000 {
 141                 #address-cells = <1>;
 142                 #size-cells = <0>;
 143                 compatible = "renesas,i2c-r8a7778";
 144                 reg = <0xffc71000 0x1000>;
 145                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 146                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 147                 status = "disabled";
 148         };
 149
 150         i2c2: i2c@ffc72000 {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153                 compatible = "renesas,i2c-r8a7778";
 154                 reg = <0xffc72000 0x1000>;
 155                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 157                 status = "disabled";
 158         };
 159
 160         i2c3: i2c@ffc73000 {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 compatible = "renesas,i2c-r8a7778";
 164                 reg = <0xffc73000 0x1000>;
 165                 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 167                 status = "disabled";
 168         };
 169
 170         tmu0: timer@ffd80000 {
 171                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 172                 reg = <0xffd80000 0x30>;
 173                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 174                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 175                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 177                 clock-names = "fck";
 178
 179                 #renesas,channels = <3>;
 180
 181                 status = "disabled";
 182         };
 183
 184         tmu1: timer@ffd81000 {
 185                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 186                 reg = <0xffd81000 0x30>;
 187                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 188                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 189                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 190                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 191                 clock-names = "fck";
 192
 193                 #renesas,channels = <3>;
 194
 195                 status = "disabled";
 196         };
 197
 198         tmu2: timer@ffd82000 {
 199                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 200                 reg = <0xffd82000 0x30>;
 201                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 202                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 203                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 205                 clock-names = "fck";
 206
 207                 #renesas,channels = <3>;
 208
 209                 status = "disabled";
 210         };
 211
 212         scif0: serial@ffe40000 {
 213                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 214                 reg = <0xffe40000 0x100>;
 215                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
 217                 clock-names = "sci_ick";
 218                 status = "disabled";
 219         };
 220
 221         scif1: serial@ffe41000 {
 222                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 223                 reg = <0xffe41000 0x100>;
 224                 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
 226                 clock-names = "sci_ick";
 227                 status = "disabled";
 228         };
 229
 230         scif2: serial@ffe42000 {
 231                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 232                 reg = <0xffe42000 0x100>;
 233                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
 235                 clock-names = "sci_ick";
 236                 status = "disabled";
 237         };
 238
 239         scif3: serial@ffe43000 {
 240                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 241                 reg = <0xffe43000 0x100>;
 242                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
 244                 clock-names = "sci_ick";
 245                 status = "disabled";
 246         };
 247
 248         scif4: serial@ffe44000 {
 249                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 250                 reg = <0xffe44000 0x100>;
 251                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 252                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
 253                 clock-names = "sci_ick";
 254                 status = "disabled";
 255         };
 256
 257         scif5: serial@ffe45000 {
 258                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 259                 reg = <0xffe45000 0x100>;
 260                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
 262                 clock-names = "sci_ick";
 263                 status = "disabled";
 264         };
 265
 266         mmcif: mmc@ffe4e000 {
 267                 compatible = "renesas,sh-mmcif";
 268                 reg = <0xffe4e000 0x100>;
 269                 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 271                 status = "disabled";
 272         };
 273
 274         sdhi0: sd@ffe4c000 {
 275                 compatible = "renesas,sdhi-r8a7778";
 276                 reg = <0xffe4c000 0x100>;
 277                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 279                 status = "disabled";
 280         };
 281
 282         sdhi1: sd@ffe4d000 {
 283                 compatible = "renesas,sdhi-r8a7778";
 284                 reg = <0xffe4d000 0x100>;
 285                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 287                 status = "disabled";
 288         };
 289
 290         sdhi2: sd@ffe4f000 {
 291                 compatible = "renesas,sdhi-r8a7778";
 292                 reg = <0xffe4f000 0x100>;
 293                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 295                 status = "disabled";
 296         };
 297
 298         hspi0: spi@fffc7000 {
 299                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 300                 reg = <0xfffc7000 0x18>;
 301                 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 status = "disabled";
 306         };
 307
 308         hspi1: spi@fffc8000 {
 309                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 310                 reg = <0xfffc8000 0x18>;
 311                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 status = "disabled";
 316         };
 317
 318         hspi2: spi@fffc6000 {
 319                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 320                 reg = <0xfffc6000 0x18>;
 321                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 322                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         clocks {
 329                 #address-cells = <1>;
 330                 #size-cells = <1>;
 331                 ranges;
 332
 333                 /* External input clock */
 334                 extal_clk: extal_clk {
 335                         compatible = "fixed-clock";
 336                         #clock-cells = <0>;
 337                         clock-frequency = <0>;
 338                         clock-output-names = "extal";
 339                 };
 340
 341                 /* Special CPG clocks */
 342                 cpg_clocks: cpg_clocks@ffc80000 {
 343                         compatible = "renesas,r8a7778-cpg-clocks";
 344                         reg = <0xffc80000 0x80>;
 345                         #clock-cells = <1>;
 346                         clocks = <&extal_clk>;
 347                         clock-output-names = "plla", "pllb", "b",
 348                                              "out", "p", "s", "s1";
 349                 };
 350
 351                 /* Audio clocks; frequencies are set by boards if applicable. */
 352                 audio_clk_a: audio_clk_a {
 353                         compatible = "fixed-clock";
 354                         #clock-cells = <0>;
 355                         clock-output-names = "audio_clk_a";
 356                 };
 357                 audio_clk_b: audio_clk_b {
 358                         compatible = "fixed-clock";
 359                         #clock-cells = <0>;
 360                         clock-output-names = "audio_clk_b";
 361                 };
 362                 audio_clk_c: audio_clk_c {
 363                         compatible = "fixed-clock";
 364                         #clock-cells = <0>;
 365                         clock-output-names = "audio_clk_c";
 366                 };
 367
 368                 /* Fixed ratio clocks */
 369                 g_clk: g_clk {
 370                         compatible = "fixed-factor-clock";
 371                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 372                         #clock-cells = <0>;
 373                         clock-div = <12>;
 374                         clock-mult = <1>;
 375                         clock-output-names = "g";
 376                 };
 377                 i_clk: i_clk {
 378                         compatible = "fixed-factor-clock";
 379                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 380                         #clock-cells = <0>;
 381                         clock-div = <1>;
 382                         clock-mult = <1>;
 383                         clock-output-names = "i";
 384                 };
 385                 s3_clk: s3_clk {
 386                         compatible = "fixed-factor-clock";
 387                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 388                         #clock-cells = <0>;
 389                         clock-div = <4>;
 390                         clock-mult = <1>;
 391                         clock-output-names = "s3";
 392                 };
 393                 s4_clk: s4_clk {
 394                         compatible = "fixed-factor-clock";
 395                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 396                         #clock-cells = <0>;
 397                         clock-div = <8>;
 398                         clock-mult = <1>;
 399                         clock-output-names = "s4";
 400                 };
 401                 z_clk: z_clk {
 402                         compatible = "fixed-factor-clock";
 403                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 404                         #clock-cells = <0>;
 405                         clock-div = <1>;
 406                         clock-mult = <1>;
 407                         clock-output-names = "z";
 408                 };
 409
 410                 /* Gate clocks */
 411                 mstp0_clks: mstp0_clks@ffc80030 {
 412                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 413                         reg = <0xffc80030 4>;
 414                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 415                                  <&cpg_clocks R8A7778_CLK_P>,
 416                                  <&cpg_clocks R8A7778_CLK_P>,
 417                                  <&cpg_clocks R8A7778_CLK_P>,
 418                                  <&cpg_clocks R8A7778_CLK_P>,
 419                                  <&cpg_clocks R8A7778_CLK_P>,
 420                                  <&cpg_clocks R8A7778_CLK_P>,
 421                                  <&cpg_clocks R8A7778_CLK_P>,
 422                                  <&cpg_clocks R8A7778_CLK_P>,
 423                                  <&cpg_clocks R8A7778_CLK_P>,
 424                                  <&cpg_clocks R8A7778_CLK_P>,
 425                                  <&cpg_clocks R8A7778_CLK_P>,
 426                                  <&cpg_clocks R8A7778_CLK_P>,
 427                                  <&cpg_clocks R8A7778_CLK_P>,
 428                                  <&cpg_clocks R8A7778_CLK_P>,
 429                                  <&cpg_clocks R8A7778_CLK_P>,
 430                                  <&cpg_clocks R8A7778_CLK_P>,
 431                                  <&cpg_clocks R8A7778_CLK_P>,
 432                                  <&cpg_clocks R8A7778_CLK_S>;
 433                         #clock-cells = <1>;
 434                         clock-indices = <
 435                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 436                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 437                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 438                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 439                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 440                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 441                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 442                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 443                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 444                                 R8A7778_CLK_HSPI
 445                         >;
 446                         clock-output-names =
 447                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 448                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 449                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 450                                 "ssi2", "ssi3", "sru", "hspi";
 451                 };
 452                 mstp1_clks: mstp1_clks@ffc80034 {
 453                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 454                         reg = <0xffc80034 4>, <0xffc80044 4>;
 455                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 456                                  <&cpg_clocks R8A7778_CLK_S>,
 457                                  <&cpg_clocks R8A7778_CLK_S>,
 458                                  <&cpg_clocks R8A7778_CLK_P>;
 459                         #clock-cells = <1>;
 460                         clock-indices = <
 461                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 462                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 463                         >;
 464                         clock-output-names =
 465                                 "ether", "vin0", "vin1", "usb";
 466                 };
 467                 mstp3_clks: mstp3_clks@ffc8003c {
 468                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 469                         reg = <0xffc8003c 4>;
 470                         clocks = <&s4_clk>,
 471                                  <&cpg_clocks R8A7778_CLK_P>,
 472                                  <&cpg_clocks R8A7778_CLK_P>,
 473                                  <&cpg_clocks R8A7778_CLK_P>,
 474                                  <&cpg_clocks R8A7778_CLK_P>,
 475                                  <&cpg_clocks R8A7778_CLK_P>,
 476                                  <&cpg_clocks R8A7778_CLK_P>,
 477                                  <&cpg_clocks R8A7778_CLK_P>,
 478                                  <&cpg_clocks R8A7778_CLK_P>;
 479                         #clock-cells = <1>;
 480                         clock-indices = <
 481                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 482                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 483                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 484                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 485                                 R8A7778_CLK_SSI8
 486                         >;
 487                         clock-output-names =
 488                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 489                                 "ssi5", "ssi6", "ssi7", "ssi8";
 490                 };
 491                 mstp5_clks: mstp5_clks@ffc80054 {
 492                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 493                         reg = <0xffc80054 4>;
 494                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 495                                  <&cpg_clocks R8A7778_CLK_P>,
 496                                  <&cpg_clocks R8A7778_CLK_P>,
 497                                  <&cpg_clocks R8A7778_CLK_P>,
 498                                  <&cpg_clocks R8A7778_CLK_P>,
 499                                  <&cpg_clocks R8A7778_CLK_P>,
 500                                  <&cpg_clocks R8A7778_CLK_P>,
 501                                  <&cpg_clocks R8A7778_CLK_P>,
 502                                  <&cpg_clocks R8A7778_CLK_P>;
 503                         #clock-cells = <1>;
 504                         clock-indices = <
 505                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 506                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 507                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 508                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 509                                 R8A7778_CLK_SRU_SRC8
 510                         >;
 511                         clock-output-names =
 512                                 "sru-src0", "sru-src1", "sru-src2",
 513                                 "sru-src3", "sru-src4", "sru-src5",
 514                                 "sru-src6", "sru-src7", "sru-src8";
 515                 };
 516         };
 517 };