3 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
15 interrupts = <1 9 0xf04>;
18 compatible = "qcom,krait";
19 enable-method = "qcom,kpss-acc-v2";
22 next-level-cache = <&L2>;
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v2";
31 next-level-cache = <&L2>;
36 compatible = "qcom,krait";
37 enable-method = "qcom,kpss-acc-v2";
40 next-level-cache = <&L2>;
45 compatible = "qcom,krait";
46 enable-method = "qcom,kpss-acc-v2";
49 next-level-cache = <&L2>;
61 compatible = "qcom,krait-pmu";
62 interrupts = <1 7 0xf04>;
66 compatible = "arm,armv7-timer";
67 interrupts = <1 2 0xf08>,
71 clock-frequency = <19200000>;
78 compatible = "simple-bus";
80 intc: interrupt-controller@f9000000 {
81 compatible = "qcom,msm-qgic2";
83 #interrupt-cells = <3>;
84 reg = <0xf9000000 0x1000>,
92 compatible = "arm,armv7-timer-mem";
93 reg = <0xf9020000 0x1000>;
94 clock-frequency = <19200000>;
98 interrupts = <0 8 0x4>,
100 reg = <0xf9021000 0x1000>,
106 interrupts = <0 9 0x4>;
107 reg = <0xf9023000 0x1000>;
113 interrupts = <0 10 0x4>;
114 reg = <0xf9024000 0x1000>;
120 interrupts = <0 11 0x4>;
121 reg = <0xf9025000 0x1000>;
127 interrupts = <0 12 0x4>;
128 reg = <0xf9026000 0x1000>;
134 interrupts = <0 13 0x4>;
135 reg = <0xf9027000 0x1000>;
141 interrupts = <0 14 0x4>;
142 reg = <0xf9028000 0x1000>;
147 saw_l2: regulator@f9012000 {
148 compatible = "qcom,saw2";
149 reg = <0xf9012000 0x1000>;
153 acc0: clock-controller@f9088000 {
154 compatible = "qcom,kpss-acc-v2";
155 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
158 acc1: clock-controller@f9098000 {
159 compatible = "qcom,kpss-acc-v2";
160 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
163 acc2: clock-controller@f90a8000 {
164 compatible = "qcom,kpss-acc-v2";
165 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
168 acc3: clock-controller@f90b8000 {
169 compatible = "qcom,kpss-acc-v2";
170 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
174 compatible = "qcom,pshold";
175 reg = <0xfc4ab000 0x4>;
178 gcc: clock-controller@fc400000 {
179 compatible = "qcom,gcc-msm8974";
182 reg = <0xfc400000 0x4000>;
185 mmcc: clock-controller@fd8c0000 {
186 compatible = "qcom,mmcc-msm8974";
189 reg = <0xfd8c0000 0x6000>;
193 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
194 reg = <0xf991e000 0x1000>;
195 interrupts = <0 108 0x0>;
196 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
197 clock-names = "core", "iface";
202 compatible = "qcom,sdhci-msm-v4";
203 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
204 reg-names = "hc_mem", "core_mem";
205 interrupts = <0 123 0>, <0 138 0>;
206 interrupt-names = "hc_irq", "pwr_irq";
207 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
208 clock-names = "core", "iface";
213 compatible = "qcom,sdhci-msm-v4";
214 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
215 reg-names = "hc_mem", "core_mem";
216 interrupts = <0 125 0>, <0 221 0>;
217 interrupt-names = "hc_irq", "pwr_irq";
218 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
219 clock-names = "core", "iface";
224 compatible = "qcom,prng";
225 reg = <0xf9bff000 0x200>;
226 clocks = <&gcc GCC_PRNG_AHB_CLK>;
227 clock-names = "core";
230 msmgpio: pinctrl@fd510000 {
231 compatible = "qcom,msm8974-pinctrl";
232 reg = <0xfd510000 0x4000>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 interrupts = <0 208 0>;