3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include "skeleton.dtsi"
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
15 interrupts = <1 9 0xf04>;
18 compatible = "qcom,krait";
19 enable-method = "qcom,kpss-acc-v2";
22 next-level-cache = <&L2>;
25 cpu-idle-states = <&CPU_SPC>;
29 compatible = "qcom,krait";
30 enable-method = "qcom,kpss-acc-v2";
33 next-level-cache = <&L2>;
36 cpu-idle-states = <&CPU_SPC>;
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v2";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v2";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
69 compatible = "qcom,idle-state-spc",
71 entry-latency-us = <150>;
72 exit-latency-us = <200>;
73 min-residency-us = <2000>;
79 compatible = "qcom,krait-pmu";
80 interrupts = <1 7 0xf04>;
84 compatible = "arm,armv7-timer";
85 interrupts = <1 2 0xf08>,
89 clock-frequency = <19200000>;
96 compatible = "simple-bus";
98 intc: interrupt-controller@f9000000 {
99 compatible = "qcom,msm-qgic2";
100 interrupt-controller;
101 #interrupt-cells = <3>;
102 reg = <0xf9000000 0x1000>,
107 #address-cells = <1>;
110 compatible = "arm,armv7-timer-mem";
111 reg = <0xf9020000 0x1000>;
112 clock-frequency = <19200000>;
116 interrupts = <0 8 0x4>,
118 reg = <0xf9021000 0x1000>,
124 interrupts = <0 9 0x4>;
125 reg = <0xf9023000 0x1000>;
131 interrupts = <0 10 0x4>;
132 reg = <0xf9024000 0x1000>;
138 interrupts = <0 11 0x4>;
139 reg = <0xf9025000 0x1000>;
145 interrupts = <0 12 0x4>;
146 reg = <0xf9026000 0x1000>;
152 interrupts = <0 13 0x4>;
153 reg = <0xf9027000 0x1000>;
159 interrupts = <0 14 0x4>;
160 reg = <0xf9028000 0x1000>;
165 saw0: power-controller@f9089000 {
166 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
167 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
170 saw1: power-controller@f9099000 {
171 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
172 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
175 saw2: power-controller@f90a9000 {
176 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
177 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
180 saw3: power-controller@f90b9000 {
181 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
182 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
185 saw_l2: power-controller@f9012000 {
186 compatible = "qcom,saw2";
187 reg = <0xf9012000 0x1000>;
191 acc0: clock-controller@f9088000 {
192 compatible = "qcom,kpss-acc-v2";
193 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
196 acc1: clock-controller@f9098000 {
197 compatible = "qcom,kpss-acc-v2";
198 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
201 acc2: clock-controller@f90a8000 {
202 compatible = "qcom,kpss-acc-v2";
203 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
206 acc3: clock-controller@f90b8000 {
207 compatible = "qcom,kpss-acc-v2";
208 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
212 compatible = "qcom,pshold";
213 reg = <0xfc4ab000 0x4>;
216 gcc: clock-controller@fc400000 {
217 compatible = "qcom,gcc-msm8974";
220 reg = <0xfc400000 0x4000>;
223 mmcc: clock-controller@fd8c0000 {
224 compatible = "qcom,mmcc-msm8974";
227 reg = <0xfd8c0000 0x6000>;
231 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
232 reg = <0xf991e000 0x1000>;
233 interrupts = <0 108 0x0>;
234 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
235 clock-names = "core", "iface";
240 compatible = "qcom,sdhci-msm-v4";
241 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
242 reg-names = "hc_mem", "core_mem";
243 interrupts = <0 123 0>, <0 138 0>;
244 interrupt-names = "hc_irq", "pwr_irq";
245 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
246 clock-names = "core", "iface";
251 compatible = "qcom,sdhci-msm-v4";
252 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
253 reg-names = "hc_mem", "core_mem";
254 interrupts = <0 125 0>, <0 221 0>;
255 interrupt-names = "hc_irq", "pwr_irq";
256 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
257 clock-names = "core", "iface";
262 compatible = "qcom,prng";
263 reg = <0xf9bff000 0x200>;
264 clocks = <&gcc GCC_PRNG_AHB_CLK>;
265 clock-names = "core";
268 msmgpio: pinctrl@fd510000 {
269 compatible = "qcom,msm8974-pinctrl";
270 reg = <0xfd510000 0x4000>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 interrupts = <0 208 0>;
278 blsp_i2c11: i2c@f9967000 {
280 compatible = "qcom,i2c-qup-v2.1.1";
281 reg = <0xf9967000 0x1000>;
282 interrupts = <0 105 IRQ_TYPE_NONE>;
283 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
284 clock-names = "core", "iface";
285 #address-cells = <1>;
289 spmi_bus: spmi@fc4cf000 {
290 compatible = "qcom,spmi-pmic-arb";
291 reg-names = "core", "intr", "cnfg";
292 reg = <0xfc4cf000 0x1000>,
295 interrupt-names = "periph_irq";
296 interrupts = <0 190 0>;
299 #address-cells = <2>;
301 interrupt-controller;
302 #interrupt-cells = <4>;