3 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
15 interrupts = <1 9 0xf04>;
16 compatible = "qcom,krait";
17 enable-method = "qcom,kpss-acc-v2";
22 next-level-cache = <&L2>;
29 next-level-cache = <&L2>;
36 next-level-cache = <&L2>;
43 next-level-cache = <&L2>;
50 interrupts = <0 2 0x4>;
56 compatible = "qcom,krait-pmu";
57 interrupts = <1 7 0xf04>;
64 compatible = "simple-bus";
66 intc: interrupt-controller@f9000000 {
67 compatible = "qcom,msm-qgic2";
69 #interrupt-cells = <3>;
70 reg = <0xf9000000 0x1000>,
75 compatible = "arm,armv7-timer";
76 interrupts = <1 2 0xf08>,
80 clock-frequency = <19200000>;
87 compatible = "arm,armv7-timer-mem";
88 reg = <0xf9020000 0x1000>;
89 clock-frequency = <19200000>;
93 interrupts = <0 8 0x4>,
95 reg = <0xf9021000 0x1000>,
101 interrupts = <0 9 0x4>;
102 reg = <0xf9023000 0x1000>;
108 interrupts = <0 10 0x4>;
109 reg = <0xf9024000 0x1000>;
115 interrupts = <0 11 0x4>;
116 reg = <0xf9025000 0x1000>;
122 interrupts = <0 12 0x4>;
123 reg = <0xf9026000 0x1000>;
129 interrupts = <0 13 0x4>;
130 reg = <0xf9027000 0x1000>;
136 interrupts = <0 14 0x4>;
137 reg = <0xf9028000 0x1000>;
142 saw_l2: regulator@f9012000 {
143 compatible = "qcom,saw2";
144 reg = <0xf9012000 0x1000>;
148 acc0: clock-controller@f9088000 {
149 compatible = "qcom,kpss-acc-v2";
150 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
153 acc1: clock-controller@f9098000 {
154 compatible = "qcom,kpss-acc-v2";
155 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
158 acc2: clock-controller@f90a8000 {
159 compatible = "qcom,kpss-acc-v2";
160 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
163 acc3: clock-controller@f90b8000 {
164 compatible = "qcom,kpss-acc-v2";
165 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
169 compatible = "qcom,pshold";
170 reg = <0xfc4ab000 0x4>;
173 gcc: clock-controller@fc400000 {
174 compatible = "qcom,gcc-msm8974";
177 reg = <0xfc400000 0x4000>;
180 mmcc: clock-controller@fd8c0000 {
181 compatible = "qcom,mmcc-msm8974";
184 reg = <0xfd8c0000 0x6000>;
188 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
189 reg = <0xf991e000 0x1000>;
190 interrupts = <0 108 0x0>;
191 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
192 clock-names = "core", "iface";
196 compatible = "qcom,prng";
197 reg = <0xf9bff000 0x200>;
198 clocks = <&gcc GCC_PRNG_AHB_CLK>;
199 clock-names = "core";