arch/arm/boot/dts/qcom-msm8960-cdp.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6
   7 / {
   8         model = "Qualcomm MSM8960 CDP";
   9         compatible = "qcom,msm8960-cdp", "qcom,msm8960";
  10         interrupt-parent = <&intc>;
  11
  12         intc: interrupt-controller@2000000 {
  13                 compatible = "qcom,msm-qgic2";
  14                 interrupt-controller;
  15                 #interrupt-cells = <3>;
  16                 reg = < 0x02000000 0x1000 >,
  17                       < 0x02002000 0x1000 >;
  18         };
  19
  20         timer@200a000 {
  21                 compatible = "qcom,kpss-timer", "qcom,msm-timer";
  22                 interrupts = <1 1 0x301>,
  23                              <1 2 0x301>,
  24                              <1 3 0x301>;
  25                 reg = <0x0200a000 0x100>;
  26                 clock-frequency = <27000000>,
  27                                   <32768>;
  28                 cpu-offset = <0x80000>;
  29         };
  30
  31         msmgpio: gpio@800000 {
  32                 compatible = "qcom,msm-gpio";
  33                 gpio-controller;
  34                 #gpio-cells = <2>;
  35                 ngpio = <150>;
  36                 interrupts = <0 16 0x4>;
  37                 interrupt-controller;
  38                 #interrupt-cells = <2>;
  39                 reg = <0x800000 0x4000>;
  40         };
  41
  42         gcc: clock-controller@900000 {
  43                 compatible = "qcom,gcc-msm8960";
  44                 #clock-cells = <1>;
  45                 #reset-cells = <1>;
  46                 reg = <0x900000 0x4000>;
  47         };
  48
  49         clock-controller@4000000 {
  50                 compatible = "qcom,mmcc-msm8960";
  51                 reg = <0x4000000 0x1000>;
  52                 #clock-cells = <1>;
  53                 #reset-cells = <1>;
  54         };
  55
  56         serial@16440000 {
  57                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  58                 reg = <0x16440000 0x1000>,
  59                       <0x16400000 0x1000>;
  60                 interrupts = <0 154 0x0>;
  61                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
  62                 clock-names = "core", "iface";
  63         };
  64
  65         qcom,ssbi@500000 {
  66                 compatible = "qcom,ssbi";
  67                 reg = <0x500000 0x1000>;
  68                 qcom,controller-type = "pmic-arbiter";
  69         };
  70 };