3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
6 #include <dt-bindings/soc/qcom,gsbi.h>
9 model = "Qualcomm MSM8660";
10 compatible = "qcom,msm8660";
11 interrupt-parent = <&intc>;
18 compatible = "qcom,scorpion";
19 enable-method = "qcom,gcc-msm8660";
22 next-level-cache = <&L2>;
26 compatible = "qcom,scorpion";
27 enable-method = "qcom,gcc-msm8660";
30 next-level-cache = <&L2>;
43 compatible = "simple-bus";
45 intc: interrupt-controller@2080000 {
46 compatible = "qcom,msm-8660-qgic";
48 #interrupt-cells = <3>;
49 reg = < 0x02080000 0x1000 >,
50 < 0x02081000 0x1000 >;
54 compatible = "qcom,scss-timer", "qcom,msm-timer";
55 interrupts = <1 0 0x301>,
58 reg = <0x02000000 0x100>;
59 clock-frequency = <27000000>,
61 cpu-offset = <0x40000>;
64 msmgpio: gpio@800000 {
65 compatible = "qcom,msm-gpio";
66 reg = <0x00800000 0x4000>;
70 interrupts = <0 16 0x4>;
72 #interrupt-cells = <2>;
75 gcc: clock-controller@900000 {
76 compatible = "qcom,gcc-msm8660";
79 reg = <0x900000 0x4000>;
82 gsbi12: gsbi@19c00000 {
83 compatible = "qcom,gsbi-v1.0.0";
84 reg = <0x19c00000 0x100>;
85 clocks = <&gcc GSBI12_H_CLK>;
86 clock-names = "iface";
92 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
93 reg = <0x19c40000 0x1000>,
95 interrupts = <0 195 0x0>;
96 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
97 clock-names = "core", "iface";
103 compatible = "qcom,ssbi";
104 reg = <0x500000 0x1000>;
105 qcom,controller-type = "pmic-arbiter";