arch/arm/boot/dts/qcom-apq8084.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4
   5 / {
   6         model = "Qualcomm APQ 8084";
   7         compatible = "qcom,apq8084";
   8         interrupt-parent = <&intc>;
   9
  10         cpus {
  11                 #address-cells = <1>;
  12                 #size-cells = <0>;
  13
  14                 cpu@0 {
  15                         device_type = "cpu";
  16                         compatible = "qcom,krait";
  17                         reg = <0>;
  18                         enable-method = "qcom,kpss-acc-v2";
  19                         next-level-cache = <&L2>;
  20                         qcom,acc = <&acc0>;
  21                 };
  22
  23                 cpu@1 {
  24                         device_type = "cpu";
  25                         compatible = "qcom,krait";
  26                         reg = <1>;
  27                         enable-method = "qcom,kpss-acc-v2";
  28                         next-level-cache = <&L2>;
  29                         qcom,acc = <&acc1>;
  30                 };
  31
  32                 cpu@2 {
  33                         device_type = "cpu";
  34                         compatible = "qcom,krait";
  35                         reg = <2>;
  36                         enable-method = "qcom,kpss-acc-v2";
  37                         next-level-cache = <&L2>;
  38                         qcom,acc = <&acc2>;
  39                 };
  40
  41                 cpu@3 {
  42                         device_type = "cpu";
  43                         compatible = "qcom,krait";
  44                         reg = <3>;
  45                         enable-method = "qcom,kpss-acc-v2";
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc3>;
  48                 };
  49
  50                 L2: l2-cache {
  51                         compatible = "qcom,arch-cache";
  52                         cache-level = <2>;
  53                         qcom,saw = <&saw_l2>;
  54                 };
  55         };
  56
  57         cpu-pmu {
  58                 compatible = "qcom,krait-pmu";
  59                 interrupts = <1 7 0xf04>;
  60         };
  61
  62         timer {
  63                 compatible = "arm,armv7-timer";
  64                 interrupts = <1 2 0xf08>,
  65                              <1 3 0xf08>,
  66                              <1 4 0xf08>,
  67                              <1 1 0xf08>;
  68                 clock-frequency = <19200000>;
  69         };
  70
  71         soc: soc {
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 ranges;
  75                 compatible = "simple-bus";
  76
  77                 intc: interrupt-controller@f9000000 {
  78                         compatible = "qcom,msm-qgic2";
  79                         interrupt-controller;
  80                         #interrupt-cells = <3>;
  81                         reg = <0xf9000000 0x1000>,
  82                               <0xf9002000 0x1000>;
  83                 };
  84
  85                 timer@f9020000 {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         compatible = "arm,armv7-timer-mem";
  90                         reg = <0xf9020000 0x1000>;
  91                         clock-frequency = <19200000>;
  92
  93                         frame@f9021000 {
  94                                 frame-number = <0>;
  95                                 interrupts = <0 8 0x4>,
  96                                              <0 7 0x4>;
  97                                 reg = <0xf9021000 0x1000>,
  98                                       <0xf9022000 0x1000>;
  99                         };
 100
 101                         frame@f9023000 {
 102                                 frame-number = <1>;
 103                                 interrupts = <0 9 0x4>;
 104                                 reg = <0xf9023000 0x1000>;
 105                                 status = "disabled";
 106                         };
 107
 108                         frame@f9024000 {
 109                                 frame-number = <2>;
 110                                 interrupts = <0 10 0x4>;
 111                                 reg = <0xf9024000 0x1000>;
 112                                 status = "disabled";
 113                         };
 114
 115                         frame@f9025000 {
 116                                 frame-number = <3>;
 117                                 interrupts = <0 11 0x4>;
 118                                 reg = <0xf9025000 0x1000>;
 119                                 status = "disabled";
 120                         };
 121
 122                         frame@f9026000 {
 123                                 frame-number = <4>;
 124                                 interrupts = <0 12 0x4>;
 125                                 reg = <0xf9026000 0x1000>;
 126                                 status = "disabled";
 127                         };
 128
 129                         frame@f9027000 {
 130                                 frame-number = <5>;
 131                                 interrupts = <0 13 0x4>;
 132                                 reg = <0xf9027000 0x1000>;
 133                                 status = "disabled";
 134                         };
 135
 136                         frame@f9028000 {
 137                                 frame-number = <6>;
 138                                 interrupts = <0 14 0x4>;
 139                                 reg = <0xf9028000 0x1000>;
 140                                 status = "disabled";
 141                         };
 142                 };
 143
 144                 saw_l2: regulator@f9012000 {
 145                         compatible = "qcom,saw2";
 146                         reg = <0xf9012000 0x1000>;
 147                         regulator;
 148                 };
 149
 150                 acc0: clock-controller@f9088000 {
 151                         compatible = "qcom,kpss-acc-v2";
 152                         reg = <0xf9088000 0x1000>,
 153                               <0xf9008000 0x1000>;
 154                 };
 155
 156                 acc1: clock-controller@f9098000 {
 157                         compatible = "qcom,kpss-acc-v2";
 158                         reg = <0xf9098000 0x1000>,
 159                               <0xf9008000 0x1000>;
 160                 };
 161
 162                 acc2: clock-controller@f90a8000 {
 163                         compatible = "qcom,kpss-acc-v2";
 164                         reg = <0xf90a8000 0x1000>,
 165                               <0xf9008000 0x1000>;
 166                 };
 167
 168                 acc3: clock-controller@f90b8000 {
 169                         compatible = "qcom,kpss-acc-v2";
 170                         reg = <0xf90b8000 0x1000>,
 171                               <0xf9008000 0x1000>;
 172                 };
 173
 174                 restart@fc4ab000 {
 175                         compatible = "qcom,pshold";
 176                         reg = <0xfc4ab000 0x4>;
 177                 };
 178         };
 179 };