3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
23 next-level-cache = <&L2>;
26 cpu-idle-states = <&CPU_SPC>;
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
37 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
45 next-level-cache = <&L2>;
48 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
56 next-level-cache = <&L2>;
59 cpu-idle-states = <&CPU_SPC>;
69 compatible = "qcom,idle-state-spc",
71 entry-latency-us = <400>;
72 exit-latency-us = <900>;
73 min-residency-us = <3000>;
79 compatible = "qcom,krait-pmu";
80 interrupts = <1 10 0x304>;
87 compatible = "simple-bus";
89 tlmm_pinmux: pinctrl@800000 {
90 compatible = "qcom,apq8064-pinctrl";
91 reg = <0x800000 0x4000>;
96 #interrupt-cells = <2>;
97 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&ps_hold>;
102 sdc4_gpios: sdc4-gpios {
104 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
112 function = "ps_hold";
118 pins = "gpio20", "gpio21";
125 pins = "gpio8", "gpio9";
130 uart_pins: uart_pins {
132 pins = "gpio14", "gpio15", "gpio16", "gpio17";
138 intc: interrupt-controller@2000000 {
139 compatible = "qcom,msm-qgic2";
140 interrupt-controller;
141 #interrupt-cells = <3>;
142 reg = <0x02000000 0x1000>,
147 compatible = "qcom,kpss-timer", "qcom,msm-timer";
148 interrupts = <1 1 0x301>,
151 reg = <0x0200a000 0x100>;
152 clock-frequency = <27000000>,
154 cpu-offset = <0x80000>;
157 acc0: clock-controller@2088000 {
158 compatible = "qcom,kpss-acc-v1";
159 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
162 acc1: clock-controller@2098000 {
163 compatible = "qcom,kpss-acc-v1";
164 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
167 acc2: clock-controller@20a8000 {
168 compatible = "qcom,kpss-acc-v1";
169 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
172 acc3: clock-controller@20b8000 {
173 compatible = "qcom,kpss-acc-v1";
174 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
177 saw0: power-controller@2089000 {
178 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
179 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
183 saw1: power-controller@2099000 {
184 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
185 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
189 saw2: power-controller@20a9000 {
190 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
191 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
195 saw3: power-controller@20b9000 {
196 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
197 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
201 gsbi1: gsbi@12440000 {
203 compatible = "qcom,gsbi-v1.0.0";
205 reg = <0x12440000 0x100>;
206 clocks = <&gcc GSBI1_H_CLK>;
207 clock-names = "iface";
208 #address-cells = <1>;
212 syscon-tcsr = <&tcsr>;
215 compatible = "qcom,i2c-qup-v1.1.1";
216 pinctrl-0 = <&i2c1_pins>;
217 pinctrl-names = "default";
218 reg = <0x12460000 0x1000>;
219 interrupts = <0 194 IRQ_TYPE_NONE>;
220 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
221 clock-names = "core", "iface";
222 #address-cells = <1>;
227 gsbi2: gsbi@12480000 {
229 compatible = "qcom,gsbi-v1.0.0";
231 reg = <0x12480000 0x100>;
232 clocks = <&gcc GSBI2_H_CLK>;
233 clock-names = "iface";
234 #address-cells = <1>;
238 syscon-tcsr = <&tcsr>;
241 compatible = "qcom,i2c-qup-v1.1.1";
242 reg = <0x124a0000 0x1000>;
243 interrupts = <0 196 IRQ_TYPE_NONE>;
244 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
245 clock-names = "core", "iface";
246 #address-cells = <1>;
251 gsbi3: gsbi@16200000 {
253 compatible = "qcom,gsbi-v1.0.0";
255 reg = <0x16200000 0x100>;
256 clocks = <&gcc GSBI3_H_CLK>;
257 clock-names = "iface";
258 #address-cells = <1>;
262 compatible = "qcom,i2c-qup-v1.1.1";
263 pinctrl-0 = <&i2c3_pins>;
264 pinctrl-names = "default";
265 reg = <0x16280000 0x1000>;
266 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
267 clocks = <&gcc GSBI3_QUP_CLK>,
269 clock-names = "core", "iface";
273 gsbi6: gsbi@16500000 {
275 compatible = "qcom,gsbi-v1.0.0";
277 reg = <0x16500000 0x03>;
278 clocks = <&gcc GSBI6_H_CLK>;
279 clock-names = "iface";
280 #address-cells = <1>;
284 gsbi6_serial: serial@16540000 {
285 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
286 reg = <0x16540000 0x100>,
288 interrupts = <0 156 0x0>;
289 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
290 clock-names = "core", "iface";
295 gsbi7: gsbi@16600000 {
297 compatible = "qcom,gsbi-v1.0.0";
299 reg = <0x16600000 0x100>;
300 clocks = <&gcc GSBI7_H_CLK>;
301 clock-names = "iface";
302 #address-cells = <1>;
305 syscon-tcsr = <&tcsr>;
307 gsbi7_serial: serial@16640000 {
308 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
309 reg = <0x16640000 0x1000>,
311 interrupts = <0 158 0x0>;
312 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
313 clock-names = "core", "iface";
319 compatible = "qcom,ssbi";
320 reg = <0x00500000 0x1000>;
321 qcom,controller-type = "pmic-arbiter";
324 compatible = "qcom,pm8921";
325 interrupt-parent = <&tlmm_pinmux>;
327 #interrupt-cells = <2>;
328 interrupt-controller;
329 #address-cells = <1>;
332 pm8921_gpio: gpio@150 {
334 compatible = "qcom,pm8921-gpio";
336 interrupts = <192 1>, <193 1>, <194 1>,
337 <195 1>, <196 1>, <197 1>,
338 <198 1>, <199 1>, <200 1>,
339 <201 1>, <202 1>, <203 1>,
340 <204 1>, <205 1>, <206 1>,
341 <207 1>, <208 1>, <209 1>,
342 <210 1>, <211 1>, <212 1>,
343 <213 1>, <214 1>, <215 1>,
344 <216 1>, <217 1>, <218 1>,
345 <219 1>, <220 1>, <221 1>,
346 <222 1>, <223 1>, <224 1>,
347 <225 1>, <226 1>, <227 1>,
348 <228 1>, <229 1>, <230 1>,
349 <231 1>, <232 1>, <233 1>,
357 pm8921_mpps: mpps@50 {
358 compatible = "qcom,pm8921-mpp";
363 <128 1>, <129 1>, <130 1>, <131 1>,
364 <132 1>, <133 1>, <134 1>, <135 1>,
365 <136 1>, <137 1>, <138 1>, <139 1>;
369 compatible = "qcom,pm8921-rtc";
370 interrupt-parent = <&pmicintc>;
379 gcc: clock-controller@900000 {
380 compatible = "qcom,gcc-apq8064";
381 reg = <0x00900000 0x4000>;
386 lcc: clock-controller@28000000 {
387 compatible = "qcom,lcc-apq8064";
388 reg = <0x28000000 0x1000>;
393 mmcc: clock-controller@4000000 {
394 compatible = "qcom,mmcc-apq8064";
395 reg = <0x4000000 0x1000>;
400 l2cc: clock-controller@2011000 {
401 compatible = "syscon";
402 reg = <0x2011000 0x1000>;
406 compatible = "qcom,rpm-apq8064";
407 reg = <0x108000 0x1000>;
408 qcom,ipc = <&l2cc 0x8 2>;
410 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
411 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
412 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
413 interrupt-names = "ack", "err", "wakeup";
416 compatible = "qcom,rpm-pm8921-regulators";
418 pm8921_hdmi_switch: hdmi-switch {
424 usb1_phy: phy@12500000 {
425 compatible = "qcom,usb-otg-ci";
426 reg = <0x12500000 0x400>;
427 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
431 clocks = <&gcc USB_HS1_XCVR_CLK>,
432 <&gcc USB_HS1_H_CLK>;
433 clock-names = "core", "iface";
435 resets = <&gcc USB_HS1_RESET>;
436 reset-names = "link";
439 usb3_phy: phy@12520000 {
440 compatible = "qcom,usb-otg-ci";
441 reg = <0x12520000 0x400>;
442 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
446 clocks = <&gcc USB_HS3_XCVR_CLK>,
447 <&gcc USB_HS3_H_CLK>;
448 clock-names = "core", "iface";
450 resets = <&gcc USB_HS3_RESET>;
451 reset-names = "link";
454 usb4_phy: phy@12530000 {
455 compatible = "qcom,usb-otg-ci";
456 reg = <0x12530000 0x400>;
457 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
461 clocks = <&gcc USB_HS4_XCVR_CLK>,
462 <&gcc USB_HS4_H_CLK>;
463 clock-names = "core", "iface";
465 resets = <&gcc USB_HS4_RESET>;
466 reset-names = "link";
469 gadget1: gadget@12500000 {
470 compatible = "qcom,ci-hdrc";
471 reg = <0x12500000 0x400>;
473 dr_mode = "peripheral";
474 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
475 usb-phy = <&usb1_phy>;
479 compatible = "qcom,ehci-host";
480 reg = <0x12500000 0x400>;
481 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
483 usb-phy = <&usb1_phy>;
487 compatible = "qcom,ehci-host";
488 reg = <0x12520000 0x400>;
489 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
491 usb-phy = <&usb3_phy>;
495 compatible = "qcom,ehci-host";
496 reg = <0x12530000 0x400>;
497 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
499 usb-phy = <&usb4_phy>;
502 sata_phy0: phy@1b400000 {
503 compatible = "qcom,apq8064-sata-phy";
505 reg = <0x1b400000 0x200>;
506 reg-names = "phy_mem";
507 clocks = <&gcc SATA_PHY_CFG_CLK>;
512 sata0: sata@29000000 {
513 compatible = "generic-ahci";
515 reg = <0x29000000 0x180>;
516 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
518 clocks = <&gcc SFAB_SATA_S_H_CLK>,
521 <&gcc SATA_RXOOB_CLK>,
522 <&gcc SATA_PMALIVE_CLK>;
523 clock-names = "slave_iface",
529 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
530 <&gcc SATA_PMALIVE_CLK>;
531 assigned-clock-rates = <100000000>, <100000000>;
534 phy-names = "sata-phy";
537 /* Temporary fixed regulator */
538 sdcc1bam:dma@12402000{
539 compatible = "qcom,bam-v1.3.0";
540 reg = <0x12402000 0x8000>;
541 interrupts = <0 98 0>;
542 clocks = <&gcc SDC1_H_CLK>;
543 clock-names = "bam_clk";
548 sdcc3bam:dma@12182000{
549 compatible = "qcom,bam-v1.3.0";
550 reg = <0x12182000 0x8000>;
551 interrupts = <0 96 0>;
552 clocks = <&gcc SDC3_H_CLK>;
553 clock-names = "bam_clk";
558 sdcc4bam:dma@121c2000{
559 compatible = "qcom,bam-v1.3.0";
560 reg = <0x121c2000 0x8000>;
561 interrupts = <0 95 0>;
562 clocks = <&gcc SDC4_H_CLK>;
563 clock-names = "bam_clk";
569 compatible = "arm,amba-bus";
570 #address-cells = <1>;
573 sdcc1: sdcc@12400000 {
575 compatible = "arm,pl18x", "arm,primecell";
576 arm,primecell-periphid = <0x00051180>;
577 reg = <0x12400000 0x2000>;
578 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
579 interrupt-names = "cmd_irq";
580 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
581 clock-names = "mclk", "apb_pclk";
583 max-frequency = <96000000>;
587 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
588 dma-names = "tx", "rx";
591 sdcc3: sdcc@12180000 {
592 compatible = "arm,pl18x", "arm,primecell";
593 arm,primecell-periphid = <0x00051180>;
595 reg = <0x12180000 0x2000>;
596 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-names = "cmd_irq";
598 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
599 clock-names = "mclk", "apb_pclk";
603 max-frequency = <192000000>;
605 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
606 dma-names = "tx", "rx";
609 sdcc4: sdcc@121c0000 {
610 compatible = "arm,pl18x", "arm,primecell";
611 arm,primecell-periphid = <0x00051180>;
613 reg = <0x121c0000 0x2000>;
614 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "cmd_irq";
616 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
617 clock-names = "mclk", "apb_pclk";
621 max-frequency = <48000000>;
622 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
623 dma-names = "tx", "rx";
624 pinctrl-names = "default";
625 pinctrl-0 = <&sdc4_gpios>;
629 tcsr: syscon@1a400000 {
630 compatible = "qcom,tcsr-apq8064", "syscon";
631 reg = <0x1a400000 0x100>;