arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         model = "Qualcomm APQ8064";
  12         compatible = "qcom,apq8064";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "qcom,krait";
  21                         enable-method = "qcom,kpss-acc-v1";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                         cpu-idle-states = <&CPU_SPC>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu@2 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <2>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc2>;
  48                         qcom,saw = <&saw2>;
  49                         cpu-idle-states = <&CPU_SPC>;
  50                 };
  51
  52                 cpu@3 {
  53                         compatible = "qcom,krait";
  54                         enable-method = "qcom,kpss-acc-v1";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                         next-level-cache = <&L2>;
  58                         qcom,acc = <&acc3>;
  59                         qcom,saw = <&saw3>;
  60                         cpu-idle-states = <&CPU_SPC>;
  61                 };
  62
  63                 L2: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <2>;
  66                 };
  67
  68                 idle-states {
  69                         CPU_SPC: spc {
  70                                 compatible = "qcom,idle-state-spc",
  71                                                 "arm,idle-state";
  72                                 entry-latency-us = <400>;
  73                                 exit-latency-us = <900>;
  74                                 min-residency-us = <3000>;
  75                         };
  76                 };
  77         };
  78
  79         cpu-pmu {
  80                 compatible = "qcom,krait-pmu";
  81                 interrupts = <1 10 0x304>;
  82         };
  83
  84         soc: soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 compatible = "simple-bus";
  89
  90                 tlmm_pinmux: pinctrl@800000 {
  91                         compatible = "qcom,apq8064-pinctrl";
  92                         reg = <0x800000 0x4000>;
  93
  94                         gpio-controller;
  95                         #gpio-cells = <2>;
  96                         interrupt-controller;
  97                         #interrupt-cells = <2>;
  98                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  99
 100                         pinctrl-names = "default";
 101                         pinctrl-0 = <&ps_hold>;
 102
 103                         sdc4_gpios: sdc4-gpios {
 104                                 pios {
 105                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 106                                         function = "sdc4";
 107                                 };
 108                         };
 109
 110                         ps_hold: ps_hold {
 111                                 mux {
 112                                         pins = "gpio78";
 113                                         function = "ps_hold";
 114                                 };
 115                         };
 116                 };
 117
 118                 intc: interrupt-controller@2000000 {
 119                         compatible = "qcom,msm-qgic2";
 120                         interrupt-controller;
 121                         #interrupt-cells = <3>;
 122                         reg = <0x02000000 0x1000>,
 123                               <0x02002000 0x1000>;
 124                 };
 125
 126                 timer@200a000 {
 127                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 128                         interrupts = <1 1 0x301>,
 129                                      <1 2 0x301>,
 130                                      <1 3 0x301>;
 131                         reg = <0x0200a000 0x100>;
 132                         clock-frequency = <27000000>,
 133                                           <32768>;
 134                         cpu-offset = <0x80000>;
 135                 };
 136
 137                 acc0: clock-controller@2088000 {
 138                         compatible = "qcom,kpss-acc-v1";
 139                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 140                 };
 141
 142                 acc1: clock-controller@2098000 {
 143                         compatible = "qcom,kpss-acc-v1";
 144                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 145                 };
 146
 147                 acc2: clock-controller@20a8000 {
 148                         compatible = "qcom,kpss-acc-v1";
 149                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 150                 };
 151
 152                 acc3: clock-controller@20b8000 {
 153                         compatible = "qcom,kpss-acc-v1";
 154                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 155                 };
 156
 157                 saw0: power-controller@2089000 {
 158                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 159                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 160                         regulator;
 161                 };
 162
 163                 saw1: power-controller@2099000 {
 164                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 165                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 166                         regulator;
 167                 };
 168
 169                 saw2: power-controller@20a9000 {
 170                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 171                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 172                         regulator;
 173                 };
 174
 175                 saw3: power-controller@20b9000 {
 176                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 177                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 178                         regulator;
 179                 };
 180
 181                 gsbi1: gsbi@12440000 {
 182                         status = "disabled";
 183                         compatible = "qcom,gsbi-v1.0.0";
 184                         cell-index = <1>;
 185                         reg = <0x12440000 0x100>;
 186                         clocks = <&gcc GSBI1_H_CLK>;
 187                         clock-names = "iface";
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190                         ranges;
 191
 192                         syscon-tcsr = <&tcsr>;
 193
 194                         i2c1: i2c@12460000 {
 195                                 compatible = "qcom,i2c-qup-v1.1.1";
 196                                 reg = <0x12460000 0x1000>;
 197                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 198                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 199                                 clock-names = "core", "iface";
 200                                 #address-cells = <1>;
 201                                 #size-cells = <0>;
 202                         };
 203                 };
 204
 205                 gsbi2: gsbi@12480000 {
 206                         status = "disabled";
 207                         compatible = "qcom,gsbi-v1.0.0";
 208                         cell-index = <2>;
 209                         reg = <0x12480000 0x100>;
 210                         clocks = <&gcc GSBI2_H_CLK>;
 211                         clock-names = "iface";
 212                         #address-cells = <1>;
 213                         #size-cells = <1>;
 214                         ranges;
 215
 216                         syscon-tcsr = <&tcsr>;
 217
 218                         i2c2: i2c@124a0000 {
 219                                 compatible = "qcom,i2c-qup-v1.1.1";
 220                                 reg = <0x124a0000 0x1000>;
 221                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 222                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 223                                 clock-names = "core", "iface";
 224                                 #address-cells = <1>;
 225                                 #size-cells = <0>;
 226                         };
 227                 };
 228
 229                 gsbi7: gsbi@16600000 {
 230                         status = "disabled";
 231                         compatible = "qcom,gsbi-v1.0.0";
 232                         cell-index = <7>;
 233                         reg = <0x16600000 0x100>;
 234                         clocks = <&gcc GSBI7_H_CLK>;
 235                         clock-names = "iface";
 236                         #address-cells = <1>;
 237                         #size-cells = <1>;
 238                         ranges;
 239
 240                         syscon-tcsr = <&tcsr>;
 241
 242                         serial@16640000 {
 243                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 244                                 reg = <0x16640000 0x1000>,
 245                                       <0x16600000 0x1000>;
 246                                 interrupts = <0 158 0x0>;
 247                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 248                                 clock-names = "core", "iface";
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 qcom,ssbi@500000 {
 254                         compatible = "qcom,ssbi";
 255                         reg = <0x00500000 0x1000>;
 256                         qcom,controller-type = "pmic-arbiter";
 257                 };
 258
 259                 gcc: clock-controller@900000 {
 260                         compatible = "qcom,gcc-apq8064";
 261                         reg = <0x00900000 0x4000>;
 262                         #clock-cells = <1>;
 263                         #reset-cells = <1>;
 264                 };
 265
 266                 lcc: clock-controller@28000000 {
 267                         compatible = "qcom,lcc-apq8064";
 268                         reg = <0x28000000 0x1000>;
 269                         #clock-cells = <1>;
 270                         #reset-cells = <1>;
 271                 };
 272
 273                 mmcc: clock-controller@4000000 {
 274                         compatible = "qcom,mmcc-apq8064";
 275                         reg = <0x4000000 0x1000>;
 276                         #clock-cells = <1>;
 277                         #reset-cells = <1>;
 278                 };
 279
 280                 l2cc: clock-controller@2011000 {
 281                         compatible      = "syscon";
 282                         reg             = <0x2011000 0x1000>;
 283                 };
 284
 285                 rpm@108000 {
 286                         compatible      = "qcom,rpm-apq8064";
 287                         reg             = <0x108000 0x1000>;
 288                         qcom,ipc        = <&l2cc 0x8 2>;
 289
 290                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 291                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 292                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 293                         interrupt-names = "ack", "err", "wakeup";
 294
 295                         regulators {
 296                                 compatible = "qcom,rpm-pm8921-regulators";
 297
 298                                 pm8921_hdmi_switch: hdmi-switch {
 299                                         bias-pull-down;
 300                                 };
 301                         };
 302                 };
 303
 304                 usb3_phy: phy@12520000 {
 305                         compatible      = "qcom,usb-otg-ci";
 306                         reg             = <0x12520000 0x400>;
 307                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 308                         status          = "disabled";
 309                         dr_mode         = "host";
 310
 311                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 312                                           <&gcc USB_HS3_H_CLK>;
 313                         clock-names     = "core", "iface";
 314
 315                         resets          = <&gcc USB_HS3_RESET>;
 316                         reset-names     = "link";
 317                 };
 318
 319                 usb4_phy: phy@12530000 {
 320                         compatible      = "qcom,usb-otg-ci";
 321                         reg             = <0x12530000 0x400>;
 322                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 323                         status          = "disabled";
 324                         dr_mode         = "host";
 325
 326                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 327                                           <&gcc USB_HS4_H_CLK>;
 328                         clock-names     = "core", "iface";
 329
 330                         resets          = <&gcc USB_HS4_RESET>;
 331                         reset-names     = "link";
 332                 };
 333
 334                 usb3: usb@12520000 {
 335                         compatible      = "qcom,ehci-host";
 336                         reg             = <0x12520000 0x400>;
 337                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 338                         status          = "disabled";
 339                         usb-phy         = <&usb3_phy>;
 340                 };
 341
 342                 usb4: usb@12530000 {
 343                         compatible      = "qcom,ehci-host";
 344                         reg             = <0x12530000 0x400>;
 345                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 346                         status          = "disabled";
 347                         usb-phy         = <&usb4_phy>;
 348                 };
 349
 350                 /* Temporary fixed regulator */
 351                 vsdcc_fixed: vsdcc-regulator {
 352                         compatible = "regulator-fixed";
 353                         regulator-name = "SDCC Power";
 354                         regulator-min-microvolt = <2700000>;
 355                         regulator-max-microvolt = <2700000>;
 356                         regulator-always-on;
 357                 };
 358
 359                 sdcc1bam:dma@12402000{
 360                         compatible = "qcom,bam-v1.3.0";
 361                         reg = <0x12402000 0x8000>;
 362                         interrupts = <0 98 0>;
 363                         clocks = <&gcc SDC1_H_CLK>;
 364                         clock-names = "bam_clk";
 365                         #dma-cells = <1>;
 366                         qcom,ee = <0>;
 367                 };
 368
 369                 sdcc3bam:dma@12182000{
 370                         compatible = "qcom,bam-v1.3.0";
 371                         reg = <0x12182000 0x8000>;
 372                         interrupts = <0 96 0>;
 373                         clocks = <&gcc SDC3_H_CLK>;
 374                         clock-names = "bam_clk";
 375                         #dma-cells = <1>;
 376                         qcom,ee = <0>;
 377                 };
 378
 379                 sdcc4bam:dma@121c2000{
 380                         compatible = "qcom,bam-v1.3.0";
 381                         reg = <0x121c2000 0x8000>;
 382                         interrupts = <0 95 0>;
 383                         clocks = <&gcc SDC4_H_CLK>;
 384                         clock-names = "bam_clk";
 385                         #dma-cells = <1>;
 386                         qcom,ee = <0>;
 387                 };
 388
 389                 amba {
 390                         compatible = "arm,amba-bus";
 391                         #address-cells = <1>;
 392                         #size-cells = <1>;
 393                         ranges;
 394                         sdcc1: sdcc@12400000 {
 395                                 status          = "disabled";
 396                                 compatible      = "arm,pl18x", "arm,primecell";
 397                                 arm,primecell-periphid = <0x00051180>;
 398                                 reg             = <0x12400000 0x2000>;
 399                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 400                                 interrupt-names = "cmd_irq";
 401                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 402                                 clock-names     = "mclk", "apb_pclk";
 403                                 bus-width       = <8>;
 404                                 max-frequency   = <96000000>;
 405                                 non-removable;
 406                                 cap-sd-highspeed;
 407                                 cap-mmc-highspeed;
 408                                 vmmc-supply = <&vsdcc_fixed>;
 409                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 410                                 dma-names = "tx", "rx";
 411                         };
 412
 413                         sdcc3: sdcc@12180000 {
 414                                 compatible      = "arm,pl18x", "arm,primecell";
 415                                 arm,primecell-periphid = <0x00051180>;
 416                                 status          = "disabled";
 417                                 reg             = <0x12180000 0x2000>;
 418                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 419                                 interrupt-names = "cmd_irq";
 420                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 421                                 clock-names     = "mclk", "apb_pclk";
 422                                 bus-width       = <4>;
 423                                 cap-sd-highspeed;
 424                                 cap-mmc-highspeed;
 425                                 max-frequency   = <192000000>;
 426                                 no-1-8-v;
 427                                 vmmc-supply = <&vsdcc_fixed>;
 428                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 429                                 dma-names = "tx", "rx";
 430                         };
 431
 432                         sdcc4: sdcc@121c0000 {
 433                                 compatible      = "arm,pl18x", "arm,primecell";
 434                                 arm,primecell-periphid = <0x00051180>;
 435                                 status          = "disabled";
 436                                 reg             = <0x121c0000 0x2000>;
 437                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 438                                 interrupt-names = "cmd_irq";
 439                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 440                                 clock-names     = "mclk", "apb_pclk";
 441                                 bus-width       = <4>;
 442                                 cap-sd-highspeed;
 443                                 cap-mmc-highspeed;
 444                                 max-frequency   = <48000000>;
 445                                 vmmc-supply = <&vsdcc_fixed>;
 446                                 vqmmc-supply = <&vsdcc_fixed>;
 447                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 448                                 dma-names = "tx", "rx";
 449                                 pinctrl-names = "default";
 450                                 pinctrl-0 = <&sdc4_gpios>;
 451                         };
 452                 };
 453
 454                 tcsr: syscon@1a400000 {
 455                         compatible = "qcom,tcsr-apq8064", "syscon";
 456                         reg = <0x1a400000 0x100>;
 457                 };
 458         };
 459 };