arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,krait";
  20                         enable-method = "qcom,kpss-acc-v1";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         qcom,acc = <&acc0>;
  25                         qcom,saw = <&saw0>;
  26                         cpu-idle-states = <&CPU_SPC>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <1>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc1>;
  36                         qcom,saw = <&saw1>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@2 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <2>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc2>;
  47                         qcom,saw = <&saw2>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@3 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <3>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc3>;
  58                         qcom,saw = <&saw3>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 L2: l2-cache {
  63                         compatible = "cache";
  64                         cache-level = <2>;
  65                 };
  66
  67                 idle-states {
  68                         CPU_SPC: spc {
  69                                 compatible = "qcom,idle-state-spc",
  70                                                 "arm,idle-state";
  71                                 entry-latency-us = <400>;
  72                                 exit-latency-us = <900>;
  73                                 min-residency-us = <3000>;
  74                         };
  75                 };
  76         };
  77
  78         cpu-pmu {
  79                 compatible = "qcom,krait-pmu";
  80                 interrupts = <1 10 0x304>;
  81         };
  82
  83         soc: soc {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 ranges;
  87                 compatible = "simple-bus";
  88
  89                 tlmm_pinmux: pinctrl@800000 {
  90                         compatible = "qcom,apq8064-pinctrl";
  91                         reg = <0x800000 0x4000>;
  92
  93                         gpio-controller;
  94                         #gpio-cells = <2>;
  95                         interrupt-controller;
  96                         #interrupt-cells = <2>;
  97                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  98
  99                         pinctrl-names = "default";
 100                         pinctrl-0 = <&ps_hold>;
 101
 102                         sdc4_gpios: sdc4-gpios {
 103                                 pios {
 104                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 105                                         function = "sdc4";
 106                                 };
 107                         };
 108
 109                         ps_hold: ps_hold {
 110                                 mux {
 111                                         pins = "gpio78";
 112                                         function = "ps_hold";
 113                                 };
 114                         };
 115
 116                         i2c1_pins: i2c1 {
 117                                 mux {
 118                                         pins = "gpio20", "gpio21";
 119                                         function = "gsbi1";
 120                                 };
 121                         };
 122
 123                         i2c3_pins: i2c3 {
 124                                 mux {
 125                                         pins = "gpio8", "gpio9";
 126                                         function = "gsbi3";
 127                                 };
 128                         };
 129
 130                         uart_pins: uart_pins {
 131                                 mux {
 132                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 133                                         function = "gsbi6";
 134                                 };
 135                         };
 136                 };
 137
 138                 intc: interrupt-controller@2000000 {
 139                         compatible = "qcom,msm-qgic2";
 140                         interrupt-controller;
 141                         #interrupt-cells = <3>;
 142                         reg = <0x02000000 0x1000>,
 143                               <0x02002000 0x1000>;
 144                 };
 145
 146                 timer@200a000 {
 147                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 148                         interrupts = <1 1 0x301>,
 149                                      <1 2 0x301>,
 150                                      <1 3 0x301>;
 151                         reg = <0x0200a000 0x100>;
 152                         clock-frequency = <27000000>,
 153                                           <32768>;
 154                         cpu-offset = <0x80000>;
 155                 };
 156
 157                 acc0: clock-controller@2088000 {
 158                         compatible = "qcom,kpss-acc-v1";
 159                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 160                 };
 161
 162                 acc1: clock-controller@2098000 {
 163                         compatible = "qcom,kpss-acc-v1";
 164                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 165                 };
 166
 167                 acc2: clock-controller@20a8000 {
 168                         compatible = "qcom,kpss-acc-v1";
 169                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 170                 };
 171
 172                 acc3: clock-controller@20b8000 {
 173                         compatible = "qcom,kpss-acc-v1";
 174                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 175                 };
 176
 177                 saw0: power-controller@2089000 {
 178                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 179                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 180                         regulator;
 181                 };
 182
 183                 saw1: power-controller@2099000 {
 184                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 185                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 186                         regulator;
 187                 };
 188
 189                 saw2: power-controller@20a9000 {
 190                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 191                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 192                         regulator;
 193                 };
 194
 195                 saw3: power-controller@20b9000 {
 196                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 197                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 198                         regulator;
 199                 };
 200
 201                 gsbi1: gsbi@12440000 {
 202                         status = "disabled";
 203                         compatible = "qcom,gsbi-v1.0.0";
 204                         cell-index = <1>;
 205                         reg = <0x12440000 0x100>;
 206                         clocks = <&gcc GSBI1_H_CLK>;
 207                         clock-names = "iface";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         ranges;
 211
 212                         syscon-tcsr = <&tcsr>;
 213
 214                         i2c1: i2c@12460000 {
 215                                 compatible = "qcom,i2c-qup-v1.1.1";
 216                                 pinctrl-0 = <&i2c1_pins>;
 217                                 pinctrl-names = "default";
 218                                 reg = <0x12460000 0x1000>;
 219                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 220                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 221                                 clock-names = "core", "iface";
 222                                 #address-cells = <1>;
 223                                 #size-cells = <0>;
 224                         };
 225                 };
 226
 227                 gsbi2: gsbi@12480000 {
 228                         status = "disabled";
 229                         compatible = "qcom,gsbi-v1.0.0";
 230                         cell-index = <2>;
 231                         reg = <0x12480000 0x100>;
 232                         clocks = <&gcc GSBI2_H_CLK>;
 233                         clock-names = "iface";
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236                         ranges;
 237
 238                         syscon-tcsr = <&tcsr>;
 239
 240                         i2c2: i2c@124a0000 {
 241                                 compatible = "qcom,i2c-qup-v1.1.1";
 242                                 reg = <0x124a0000 0x1000>;
 243                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 244                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 245                                 clock-names = "core", "iface";
 246                                 #address-cells = <1>;
 247                                 #size-cells = <0>;
 248                         };
 249                 };
 250
 251                 gsbi3: gsbi@16200000 {
 252                         status = "disabled";
 253                         compatible = "qcom,gsbi-v1.0.0";
 254                         cell-index = <3>;
 255                         reg = <0x16200000 0x100>;
 256                         clocks = <&gcc GSBI3_H_CLK>;
 257                         clock-names = "iface";
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260                         ranges;
 261                         i2c3: i2c@16280000 {
 262                                 compatible = "qcom,i2c-qup-v1.1.1";
 263                                 pinctrl-0 = <&i2c3_pins>;
 264                                 pinctrl-names = "default";
 265                                 reg = <0x16280000 0x1000>;
 266                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 267                                 clocks = <&gcc GSBI3_QUP_CLK>,
 268                                          <&gcc GSBI3_H_CLK>;
 269                                 clock-names = "core", "iface";
 270                         };
 271                 };
 272
 273                 gsbi6: gsbi@16500000 {
 274                         status = "disabled";
 275                         compatible = "qcom,gsbi-v1.0.0";
 276                         cell-index = <6>;
 277                         reg = <0x16500000 0x03>;
 278                         clocks = <&gcc GSBI6_H_CLK>;
 279                         clock-names = "iface";
 280                         #address-cells = <1>;
 281                         #size-cells = <1>;
 282                         ranges;
 283
 284                         gsbi6_serial: serial@16540000 {
 285                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 286                                 reg = <0x16540000 0x100>,
 287                                       <0x16500000 0x03>;
 288                                 interrupts = <0 156 0x0>;
 289                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 290                                 clock-names = "core", "iface";
 291                                 status = "disabled";
 292                         };
 293                 };
 294
 295                 gsbi7: gsbi@16600000 {
 296                         status = "disabled";
 297                         compatible = "qcom,gsbi-v1.0.0";
 298                         cell-index = <7>;
 299                         reg = <0x16600000 0x100>;
 300                         clocks = <&gcc GSBI7_H_CLK>;
 301                         clock-names = "iface";
 302                         #address-cells = <1>;
 303                         #size-cells = <1>;
 304                         ranges;
 305                         syscon-tcsr = <&tcsr>;
 306
 307                         gsbi7_serial: serial@16640000 {
 308                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 309                                 reg = <0x16640000 0x1000>,
 310                                       <0x16600000 0x1000>;
 311                                 interrupts = <0 158 0x0>;
 312                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 313                                 clock-names = "core", "iface";
 314                                 status = "disabled";
 315                         };
 316                 };
 317
 318                 qcom,ssbi@500000 {
 319                         compatible = "qcom,ssbi";
 320                         reg = <0x00500000 0x1000>;
 321                         qcom,controller-type = "pmic-arbiter";
 322
 323                         pmicintc: pmic@0 {
 324                                 compatible = "qcom,pm8921";
 325                                 interrupt-parent = <&tlmm_pinmux>;
 326                                 interrupts = <74 8>;
 327                                 #interrupt-cells = <2>;
 328                                 interrupt-controller;
 329                                 #address-cells = <1>;
 330                                 #size-cells = <0>;
 331
 332                                 pm8921_gpio: gpio@150 {
 333
 334                                         compatible = "qcom,pm8921-gpio";
 335                                         reg = <0x150>;
 336                                         interrupts = <192 1>, <193 1>, <194 1>,
 337                                                      <195 1>, <196 1>, <197 1>,
 338                                                      <198 1>, <199 1>, <200 1>,
 339                                                      <201 1>, <202 1>, <203 1>,
 340                                                      <204 1>, <205 1>, <206 1>,
 341                                                      <207 1>, <208 1>, <209 1>,
 342                                                      <210 1>, <211 1>, <212 1>,
 343                                                      <213 1>, <214 1>, <215 1>,
 344                                                      <216 1>, <217 1>, <218 1>,
 345                                                      <219 1>, <220 1>, <221 1>,
 346                                                      <222 1>, <223 1>, <224 1>,
 347                                                      <225 1>, <226 1>, <227 1>,
 348                                                      <228 1>, <229 1>, <230 1>,
 349                                                      <231 1>, <232 1>, <233 1>,
 350                                                      <234 1>, <235 1>;
 351
 352                                         gpio-controller;
 353                                         #gpio-cells = <2>;
 354
 355                                 };
 356
 357                                 pm8921_mpps: mpps@50 {
 358                                         compatible = "qcom,pm8921-mpp";
 359                                         reg = <0x50>;
 360                                         gpio-controller;
 361                                         #gpio-cells = <2>;
 362                                         interrupts =
 363                                         <128 1>, <129 1>, <130 1>, <131 1>,
 364                                         <132 1>, <133 1>, <134 1>, <135 1>,
 365                                         <136 1>, <137 1>, <138 1>, <139 1>;
 366                                 };
 367
 368                         };
 369                 };
 370
 371                 gcc: clock-controller@900000 {
 372                         compatible = "qcom,gcc-apq8064";
 373                         reg = <0x00900000 0x4000>;
 374                         #clock-cells = <1>;
 375                         #reset-cells = <1>;
 376                 };
 377
 378                 lcc: clock-controller@28000000 {
 379                         compatible = "qcom,lcc-apq8064";
 380                         reg = <0x28000000 0x1000>;
 381                         #clock-cells = <1>;
 382                         #reset-cells = <1>;
 383                 };
 384
 385                 mmcc: clock-controller@4000000 {
 386                         compatible = "qcom,mmcc-apq8064";
 387                         reg = <0x4000000 0x1000>;
 388                         #clock-cells = <1>;
 389                         #reset-cells = <1>;
 390                 };
 391
 392                 l2cc: clock-controller@2011000 {
 393                         compatible      = "syscon";
 394                         reg             = <0x2011000 0x1000>;
 395                 };
 396
 397                 rpm@108000 {
 398                         compatible      = "qcom,rpm-apq8064";
 399                         reg             = <0x108000 0x1000>;
 400                         qcom,ipc        = <&l2cc 0x8 2>;
 401
 402                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 403                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 404                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 405                         interrupt-names = "ack", "err", "wakeup";
 406
 407                         regulators {
 408                                 compatible = "qcom,rpm-pm8921-regulators";
 409
 410                                 pm8921_hdmi_switch: hdmi-switch {
 411                                         bias-pull-down;
 412                                 };
 413                         };
 414                 };
 415
 416                 usb1_phy: phy@12500000 {
 417                         compatible      = "qcom,usb-otg-ci";
 418                         reg             = <0x12500000 0x400>;
 419                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 420                         status          = "disabled";
 421                         dr_mode         = "host";
 422
 423                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 424                                           <&gcc USB_HS1_H_CLK>;
 425                         clock-names     = "core", "iface";
 426
 427                         resets          = <&gcc USB_HS1_RESET>;
 428                         reset-names     = "link";
 429                 };
 430
 431                 usb3_phy: phy@12520000 {
 432                         compatible      = "qcom,usb-otg-ci";
 433                         reg             = <0x12520000 0x400>;
 434                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 435                         status          = "disabled";
 436                         dr_mode         = "host";
 437
 438                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 439                                           <&gcc USB_HS3_H_CLK>;
 440                         clock-names     = "core", "iface";
 441
 442                         resets          = <&gcc USB_HS3_RESET>;
 443                         reset-names     = "link";
 444                 };
 445
 446                 usb4_phy: phy@12530000 {
 447                         compatible      = "qcom,usb-otg-ci";
 448                         reg             = <0x12530000 0x400>;
 449                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 450                         status          = "disabled";
 451                         dr_mode         = "host";
 452
 453                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 454                                           <&gcc USB_HS4_H_CLK>;
 455                         clock-names     = "core", "iface";
 456
 457                         resets          = <&gcc USB_HS4_RESET>;
 458                         reset-names     = "link";
 459                 };
 460
 461                 gadget1: gadget@12500000 {
 462                         compatible      = "qcom,ci-hdrc";
 463                         reg             = <0x12500000 0x400>;
 464                         status          = "disabled";
 465                         dr_mode         = "peripheral";
 466                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 467                         usb-phy         = <&usb1_phy>;
 468                 };
 469
 470                 usb1: usb@12500000 {
 471                         compatible      = "qcom,ehci-host";
 472                         reg             = <0x12500000 0x400>;
 473                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 474                         status          = "disabled";
 475                         usb-phy         = <&usb1_phy>;
 476                 };
 477
 478                 usb3: usb@12520000 {
 479                         compatible      = "qcom,ehci-host";
 480                         reg             = <0x12520000 0x400>;
 481                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 482                         status          = "disabled";
 483                         usb-phy         = <&usb3_phy>;
 484                 };
 485
 486                 usb4: usb@12530000 {
 487                         compatible      = "qcom,ehci-host";
 488                         reg             = <0x12530000 0x400>;
 489                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 490                         status          = "disabled";
 491                         usb-phy         = <&usb4_phy>;
 492                 };
 493
 494                 sata_phy0: phy@1b400000 {
 495                         compatible      = "qcom,apq8064-sata-phy";
 496                         status          = "disabled";
 497                         reg             = <0x1b400000 0x200>;
 498                         reg-names       = "phy_mem";
 499                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 500                         clock-names     = "cfg";
 501                         #phy-cells      = <0>;
 502                 };
 503
 504                 sata0: sata@29000000 {
 505                         compatible              = "generic-ahci";
 506                         status                  = "disabled";
 507                         reg                     = <0x29000000 0x180>;
 508                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 509
 510                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 511                                                 <&gcc SATA_H_CLK>,
 512                                                 <&gcc SATA_A_CLK>,
 513                                                 <&gcc SATA_RXOOB_CLK>,
 514                                                 <&gcc SATA_PMALIVE_CLK>;
 515                         clock-names             = "slave_iface",
 516                                                 "iface",
 517                                                 "bus",
 518                                                 "rxoob",
 519                                                 "core_pmalive";
 520
 521                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 522                                                 <&gcc SATA_PMALIVE_CLK>;
 523                         assigned-clock-rates    = <100000000>, <100000000>;
 524
 525                         phys                    = <&sata_phy0>;
 526                         phy-names               = "sata-phy";
 527                 };
 528
 529                 /* Temporary fixed regulator */
 530                 sdcc1bam:dma@12402000{
 531                         compatible = "qcom,bam-v1.3.0";
 532                         reg = <0x12402000 0x8000>;
 533                         interrupts = <0 98 0>;
 534                         clocks = <&gcc SDC1_H_CLK>;
 535                         clock-names = "bam_clk";
 536                         #dma-cells = <1>;
 537                         qcom,ee = <0>;
 538                 };
 539
 540                 sdcc3bam:dma@12182000{
 541                         compatible = "qcom,bam-v1.3.0";
 542                         reg = <0x12182000 0x8000>;
 543                         interrupts = <0 96 0>;
 544                         clocks = <&gcc SDC3_H_CLK>;
 545                         clock-names = "bam_clk";
 546                         #dma-cells = <1>;
 547                         qcom,ee = <0>;
 548                 };
 549
 550                 sdcc4bam:dma@121c2000{
 551                         compatible = "qcom,bam-v1.3.0";
 552                         reg = <0x121c2000 0x8000>;
 553                         interrupts = <0 95 0>;
 554                         clocks = <&gcc SDC4_H_CLK>;
 555                         clock-names = "bam_clk";
 556                         #dma-cells = <1>;
 557                         qcom,ee = <0>;
 558                 };
 559
 560                 amba {
 561                         compatible = "arm,amba-bus";
 562                         #address-cells = <1>;
 563                         #size-cells = <1>;
 564                         ranges;
 565                         sdcc1: sdcc@12400000 {
 566                                 status          = "disabled";
 567                                 compatible      = "arm,pl18x", "arm,primecell";
 568                                 arm,primecell-periphid = <0x00051180>;
 569                                 reg             = <0x12400000 0x2000>;
 570                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 571                                 interrupt-names = "cmd_irq";
 572                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 573                                 clock-names     = "mclk", "apb_pclk";
 574                                 bus-width       = <8>;
 575                                 max-frequency   = <96000000>;
 576                                 non-removable;
 577                                 cap-sd-highspeed;
 578                                 cap-mmc-highspeed;
 579                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 580                                 dma-names = "tx", "rx";
 581                         };
 582
 583                         sdcc3: sdcc@12180000 {
 584                                 compatible      = "arm,pl18x", "arm,primecell";
 585                                 arm,primecell-periphid = <0x00051180>;
 586                                 status          = "disabled";
 587                                 reg             = <0x12180000 0x2000>;
 588                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 589                                 interrupt-names = "cmd_irq";
 590                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 591                                 clock-names     = "mclk", "apb_pclk";
 592                                 bus-width       = <4>;
 593                                 cap-sd-highspeed;
 594                                 cap-mmc-highspeed;
 595                                 max-frequency   = <192000000>;
 596                                 no-1-8-v;
 597                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 598                                 dma-names = "tx", "rx";
 599                         };
 600
 601                         sdcc4: sdcc@121c0000 {
 602                                 compatible      = "arm,pl18x", "arm,primecell";
 603                                 arm,primecell-periphid = <0x00051180>;
 604                                 status          = "disabled";
 605                                 reg             = <0x121c0000 0x2000>;
 606                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 607                                 interrupt-names = "cmd_irq";
 608                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 609                                 clock-names     = "mclk", "apb_pclk";
 610                                 bus-width       = <4>;
 611                                 cap-sd-highspeed;
 612                                 cap-mmc-highspeed;
 613                                 max-frequency   = <48000000>;
 614                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 615                                 dma-names = "tx", "rx";
 616                                 pinctrl-names = "default";
 617                                 pinctrl-0 = <&sdc4_gpios>;
 618                         };
 619                 };
 620
 621                 tcsr: syscon@1a400000 {
 622                         compatible = "qcom,tcsr-apq8064", "syscon";
 623                         reg = <0x1a400000 0x100>;
 624                 };
 625         };
 626 };