3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Qualcomm APQ8064";
12 compatible = "qcom,apq8064";
13 interrupt-parent = <&intc>;
20 compatible = "qcom,krait";
21 enable-method = "qcom,kpss-acc-v1";
24 next-level-cache = <&L2>;
27 cpu-idle-states = <&CPU_SPC>;
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
35 next-level-cache = <&L2>;
38 cpu-idle-states = <&CPU_SPC>;
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
46 next-level-cache = <&L2>;
49 cpu-idle-states = <&CPU_SPC>;
53 compatible = "qcom,krait";
54 enable-method = "qcom,kpss-acc-v1";
57 next-level-cache = <&L2>;
60 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,idle-state-spc",
72 entry-latency-us = <400>;
73 exit-latency-us = <900>;
74 min-residency-us = <3000>;
80 compatible = "qcom,krait-pmu";
81 interrupts = <1 10 0x304>;
88 compatible = "simple-bus";
90 tlmm_pinmux: pinctrl@800000 {
91 compatible = "qcom,apq8064-pinctrl";
92 reg = <0x800000 0x4000>;
97 #interrupt-cells = <2>;
98 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&ps_hold>;
103 sdc4_gpios: sdc4-gpios {
105 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
113 function = "ps_hold";
119 pins = "gpio20", "gpio21";
125 intc: interrupt-controller@2000000 {
126 compatible = "qcom,msm-qgic2";
127 interrupt-controller;
128 #interrupt-cells = <3>;
129 reg = <0x02000000 0x1000>,
134 compatible = "qcom,kpss-timer", "qcom,msm-timer";
135 interrupts = <1 1 0x301>,
138 reg = <0x0200a000 0x100>;
139 clock-frequency = <27000000>,
141 cpu-offset = <0x80000>;
144 acc0: clock-controller@2088000 {
145 compatible = "qcom,kpss-acc-v1";
146 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
149 acc1: clock-controller@2098000 {
150 compatible = "qcom,kpss-acc-v1";
151 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
154 acc2: clock-controller@20a8000 {
155 compatible = "qcom,kpss-acc-v1";
156 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
159 acc3: clock-controller@20b8000 {
160 compatible = "qcom,kpss-acc-v1";
161 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
164 saw0: power-controller@2089000 {
165 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
166 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
170 saw1: power-controller@2099000 {
171 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
172 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
176 saw2: power-controller@20a9000 {
177 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
178 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
182 saw3: power-controller@20b9000 {
183 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
184 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
188 gsbi1: gsbi@12440000 {
190 compatible = "qcom,gsbi-v1.0.0";
192 reg = <0x12440000 0x100>;
193 clocks = <&gcc GSBI1_H_CLK>;
194 clock-names = "iface";
195 #address-cells = <1>;
199 syscon-tcsr = <&tcsr>;
202 compatible = "qcom,i2c-qup-v1.1.1";
203 reg = <0x12460000 0x1000>;
204 interrupts = <0 194 IRQ_TYPE_NONE>;
205 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
206 clock-names = "core", "iface";
207 #address-cells = <1>;
212 gsbi2: gsbi@12480000 {
214 compatible = "qcom,gsbi-v1.0.0";
216 reg = <0x12480000 0x100>;
217 clocks = <&gcc GSBI2_H_CLK>;
218 clock-names = "iface";
219 #address-cells = <1>;
223 syscon-tcsr = <&tcsr>;
226 compatible = "qcom,i2c-qup-v1.1.1";
227 reg = <0x124a0000 0x1000>;
228 interrupts = <0 196 IRQ_TYPE_NONE>;
229 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
230 clock-names = "core", "iface";
231 #address-cells = <1>;
236 gsbi7: gsbi@16600000 {
238 compatible = "qcom,gsbi-v1.0.0";
240 reg = <0x16600000 0x100>;
241 clocks = <&gcc GSBI7_H_CLK>;
242 clock-names = "iface";
243 #address-cells = <1>;
246 syscon-tcsr = <&tcsr>;
248 gsbi7_serial: serial@16640000 {
249 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
250 reg = <0x16640000 0x1000>,
252 interrupts = <0 158 0x0>;
253 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
254 clock-names = "core", "iface";
260 compatible = "qcom,ssbi";
261 reg = <0x00500000 0x1000>;
262 qcom,controller-type = "pmic-arbiter";
265 gcc: clock-controller@900000 {
266 compatible = "qcom,gcc-apq8064";
267 reg = <0x00900000 0x4000>;
272 lcc: clock-controller@28000000 {
273 compatible = "qcom,lcc-apq8064";
274 reg = <0x28000000 0x1000>;
279 mmcc: clock-controller@4000000 {
280 compatible = "qcom,mmcc-apq8064";
281 reg = <0x4000000 0x1000>;
286 l2cc: clock-controller@2011000 {
287 compatible = "syscon";
288 reg = <0x2011000 0x1000>;
292 compatible = "qcom,rpm-apq8064";
293 reg = <0x108000 0x1000>;
294 qcom,ipc = <&l2cc 0x8 2>;
296 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
297 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
298 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
299 interrupt-names = "ack", "err", "wakeup";
302 compatible = "qcom,rpm-pm8921-regulators";
304 pm8921_hdmi_switch: hdmi-switch {
310 usb1_phy: phy@12500000 {
311 compatible = "qcom,usb-otg-ci";
312 reg = <0x12500000 0x400>;
313 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
317 clocks = <&gcc USB_HS1_XCVR_CLK>,
318 <&gcc USB_HS1_H_CLK>;
319 clock-names = "core", "iface";
321 resets = <&gcc USB_HS1_RESET>;
322 reset-names = "link";
325 usb3_phy: phy@12520000 {
326 compatible = "qcom,usb-otg-ci";
327 reg = <0x12520000 0x400>;
328 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
332 clocks = <&gcc USB_HS3_XCVR_CLK>,
333 <&gcc USB_HS3_H_CLK>;
334 clock-names = "core", "iface";
336 resets = <&gcc USB_HS3_RESET>;
337 reset-names = "link";
340 usb4_phy: phy@12530000 {
341 compatible = "qcom,usb-otg-ci";
342 reg = <0x12530000 0x400>;
343 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
347 clocks = <&gcc USB_HS4_XCVR_CLK>,
348 <&gcc USB_HS4_H_CLK>;
349 clock-names = "core", "iface";
351 resets = <&gcc USB_HS4_RESET>;
352 reset-names = "link";
355 gadget1: gadget@12500000 {
356 compatible = "qcom,ci-hdrc";
357 reg = <0x12500000 0x400>;
359 dr_mode = "peripheral";
360 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
361 usb-phy = <&usb1_phy>;
365 compatible = "qcom,ehci-host";
366 reg = <0x12500000 0x400>;
367 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
369 usb-phy = <&usb1_phy>;
373 compatible = "qcom,ehci-host";
374 reg = <0x12520000 0x400>;
375 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
377 usb-phy = <&usb3_phy>;
381 compatible = "qcom,ehci-host";
382 reg = <0x12530000 0x400>;
383 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
385 usb-phy = <&usb4_phy>;
388 sata_phy0: phy@1b400000 {
389 compatible = "qcom,apq8064-sata-phy";
391 reg = <0x1b400000 0x200>;
392 reg-names = "phy_mem";
393 clocks = <&gcc SATA_PHY_CFG_CLK>;
398 sata0: sata@29000000 {
399 compatible = "generic-ahci";
401 reg = <0x29000000 0x180>;
402 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
404 clocks = <&gcc SFAB_SATA_S_H_CLK>,
407 <&gcc SATA_RXOOB_CLK>,
408 <&gcc SATA_PMALIVE_CLK>;
409 clock-names = "slave_iface",
415 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
416 <&gcc SATA_PMALIVE_CLK>;
417 assigned-clock-rates = <100000000>, <100000000>;
420 phy-names = "sata-phy";
423 /* Temporary fixed regulator */
424 vsdcc_fixed: vsdcc-regulator {
425 compatible = "regulator-fixed";
426 regulator-name = "SDCC Power";
427 regulator-min-microvolt = <2700000>;
428 regulator-max-microvolt = <2700000>;
432 sdcc1bam:dma@12402000{
433 compatible = "qcom,bam-v1.3.0";
434 reg = <0x12402000 0x8000>;
435 interrupts = <0 98 0>;
436 clocks = <&gcc SDC1_H_CLK>;
437 clock-names = "bam_clk";
442 sdcc3bam:dma@12182000{
443 compatible = "qcom,bam-v1.3.0";
444 reg = <0x12182000 0x8000>;
445 interrupts = <0 96 0>;
446 clocks = <&gcc SDC3_H_CLK>;
447 clock-names = "bam_clk";
452 sdcc4bam:dma@121c2000{
453 compatible = "qcom,bam-v1.3.0";
454 reg = <0x121c2000 0x8000>;
455 interrupts = <0 95 0>;
456 clocks = <&gcc SDC4_H_CLK>;
457 clock-names = "bam_clk";
463 compatible = "arm,amba-bus";
464 #address-cells = <1>;
467 sdcc1: sdcc@12400000 {
469 compatible = "arm,pl18x", "arm,primecell";
470 arm,primecell-periphid = <0x00051180>;
471 reg = <0x12400000 0x2000>;
472 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-names = "cmd_irq";
474 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
475 clock-names = "mclk", "apb_pclk";
477 max-frequency = <96000000>;
481 vmmc-supply = <&vsdcc_fixed>;
482 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
483 dma-names = "tx", "rx";
486 sdcc3: sdcc@12180000 {
487 compatible = "arm,pl18x", "arm,primecell";
488 arm,primecell-periphid = <0x00051180>;
490 reg = <0x12180000 0x2000>;
491 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-names = "cmd_irq";
493 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
494 clock-names = "mclk", "apb_pclk";
498 max-frequency = <192000000>;
500 vmmc-supply = <&vsdcc_fixed>;
501 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
502 dma-names = "tx", "rx";
505 sdcc4: sdcc@121c0000 {
506 compatible = "arm,pl18x", "arm,primecell";
507 arm,primecell-periphid = <0x00051180>;
509 reg = <0x121c0000 0x2000>;
510 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "cmd_irq";
512 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
513 clock-names = "mclk", "apb_pclk";
517 max-frequency = <48000000>;
518 vmmc-supply = <&vsdcc_fixed>;
519 vqmmc-supply = <&vsdcc_fixed>;
520 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
521 dma-names = "tx", "rx";
522 pinctrl-names = "default";
523 pinctrl-0 = <&sdc4_gpios>;
527 tcsr: syscon@1a400000 {
528 compatible = "qcom,tcsr-apq8064", "syscon";
529 reg = <0x1a400000 0x100>;