2 * Device Tree Source for OMAP5 clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 pad_clks_src_ck: pad_clks_src_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <12000000>;
17 pad_clks_ck: pad_clks_ck {
19 compatible = "ti,gate-clock";
20 clocks = <&pad_clks_src_ck>;
25 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
31 slimbus_src_clk: slimbus_src_clk {
33 compatible = "fixed-clock";
34 clock-frequency = <12000000>;
37 slimbus_clk: slimbus_clk {
39 compatible = "ti,gate-clock";
40 clocks = <&slimbus_src_clk>;
45 sys_32k_ck: sys_32k_ck {
47 compatible = "fixed-clock";
48 clock-frequency = <32768>;
51 virt_12000000_ck: virt_12000000_ck {
53 compatible = "fixed-clock";
54 clock-frequency = <12000000>;
57 virt_13000000_ck: virt_13000000_ck {
59 compatible = "fixed-clock";
60 clock-frequency = <13000000>;
63 virt_16800000_ck: virt_16800000_ck {
65 compatible = "fixed-clock";
66 clock-frequency = <16800000>;
69 virt_19200000_ck: virt_19200000_ck {
71 compatible = "fixed-clock";
72 clock-frequency = <19200000>;
75 virt_26000000_ck: virt_26000000_ck {
77 compatible = "fixed-clock";
78 clock-frequency = <26000000>;
81 virt_27000000_ck: virt_27000000_ck {
83 compatible = "fixed-clock";
84 clock-frequency = <27000000>;
87 virt_38400000_ck: virt_38400000_ck {
89 compatible = "fixed-clock";
90 clock-frequency = <38400000>;
93 xclk60mhsp1_ck: xclk60mhsp1_ck {
95 compatible = "fixed-clock";
96 clock-frequency = <60000000>;
99 xclk60mhsp2_ck: xclk60mhsp2_ck {
101 compatible = "fixed-clock";
102 clock-frequency = <60000000>;
105 dpll_abe_ck: dpll_abe_ck {
107 compatible = "ti,omap4-dpll-m4xen-clock";
108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
109 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
112 dpll_abe_x2_ck: dpll_abe_x2_ck {
114 compatible = "ti,omap4-dpll-x2-clock";
115 clocks = <&dpll_abe_ck>;
118 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
120 compatible = "ti,divider-clock";
121 clocks = <&dpll_abe_x2_ck>;
124 ti,index-starts-at-one;
127 abe_24m_fclk: abe_24m_fclk {
129 compatible = "fixed-factor-clock";
130 clocks = <&dpll_abe_m2x2_ck>;
137 compatible = "ti,divider-clock";
138 clocks = <&dpll_abe_m2x2_ck>;
141 ti,index-power-of-two;
146 compatible = "ti,divider-clock";
147 clocks = <&aess_fclk>;
150 ti,dividers = <2>, <1>;
153 abe_lp_clk_div: abe_lp_clk_div {
155 compatible = "fixed-factor-clock";
156 clocks = <&dpll_abe_m2x2_ck>;
161 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
163 compatible = "ti,divider-clock";
164 clocks = <&dpll_abe_x2_ck>;
167 ti,index-starts-at-one;
170 dpll_core_ck: dpll_core_ck {
172 compatible = "ti,omap4-dpll-core-clock";
173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
174 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
177 dpll_core_x2_ck: dpll_core_x2_ck {
179 compatible = "ti,omap4-dpll-x2-clock";
180 clocks = <&dpll_core_ck>;
183 dpll_core_h21x2_ck: dpll_core_h21x2_ck {
185 compatible = "ti,divider-clock";
186 clocks = <&dpll_core_x2_ck>;
189 ti,index-starts-at-one;
194 compatible = "fixed-factor-clock";
195 clocks = <&dpll_core_h21x2_ck>;
202 compatible = "fixed-factor-clock";
203 clocks = <&c2c_fclk>;
208 dpll_core_h11x2_ck: dpll_core_h11x2_ck {
210 compatible = "ti,divider-clock";
211 clocks = <&dpll_core_x2_ck>;
214 ti,index-starts-at-one;
217 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
219 compatible = "ti,divider-clock";
220 clocks = <&dpll_core_x2_ck>;
223 ti,index-starts-at-one;
226 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
228 compatible = "ti,divider-clock";
229 clocks = <&dpll_core_x2_ck>;
232 ti,index-starts-at-one;
235 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_core_x2_ck>;
241 ti,index-starts-at-one;
244 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
246 compatible = "ti,divider-clock";
247 clocks = <&dpll_core_x2_ck>;
250 ti,index-starts-at-one;
253 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
255 compatible = "ti,divider-clock";
256 clocks = <&dpll_core_x2_ck>;
259 ti,index-starts-at-one;
262 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
264 compatible = "ti,divider-clock";
265 clocks = <&dpll_core_x2_ck>;
268 ti,index-starts-at-one;
271 dpll_core_m2_ck: dpll_core_m2_ck {
273 compatible = "ti,divider-clock";
274 clocks = <&dpll_core_ck>;
277 ti,index-starts-at-one;
280 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
282 compatible = "ti,divider-clock";
283 clocks = <&dpll_core_x2_ck>;
286 ti,index-starts-at-one;
289 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
291 compatible = "fixed-factor-clock";
292 clocks = <&dpll_core_h12x2_ck>;
297 dpll_iva_ck: dpll_iva_ck {
299 compatible = "ti,omap4-dpll-clock";
300 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
301 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
304 dpll_iva_x2_ck: dpll_iva_x2_ck {
306 compatible = "ti,omap4-dpll-x2-clock";
307 clocks = <&dpll_iva_ck>;
310 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
312 compatible = "ti,divider-clock";
313 clocks = <&dpll_iva_x2_ck>;
316 ti,index-starts-at-one;
319 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_iva_x2_ck>;
325 ti,index-starts-at-one;
328 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
330 compatible = "fixed-factor-clock";
331 clocks = <&dpll_core_h12x2_ck>;
336 dpll_mpu_ck: dpll_mpu_ck {
338 compatible = "ti,omap4-dpll-clock";
339 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
340 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
343 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
345 compatible = "ti,divider-clock";
346 clocks = <&dpll_mpu_ck>;
349 ti,index-starts-at-one;
352 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
354 compatible = "fixed-factor-clock";
355 clocks = <&dpll_abe_m3x2_ck>;
360 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
362 compatible = "fixed-factor-clock";
363 clocks = <&dpll_abe_m3x2_ck>;
368 l3_iclk_div: l3_iclk_div {
370 compatible = "fixed-factor-clock";
371 clocks = <&dpll_core_h12x2_ck>;
376 gpu_l3_iclk: gpu_l3_iclk {
378 compatible = "fixed-factor-clock";
379 clocks = <&l3_iclk_div>;
384 l4_root_clk_div: l4_root_clk_div {
386 compatible = "fixed-factor-clock";
387 clocks = <&l3_iclk_div>;
392 slimbus1_slimbus_clk: slimbus1_slimbus_clk {
394 compatible = "ti,gate-clock";
395 clocks = <&slimbus_clk>;
400 aess_fclk: aess_fclk {
402 compatible = "ti,divider-clock";
409 dmic_sync_mux_ck: dmic_sync_mux_ck {
411 compatible = "ti,mux-clock";
412 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
417 dmic_gfclk: dmic_gfclk {
419 compatible = "ti,mux-clock";
420 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
425 mcasp_sync_mux_ck: mcasp_sync_mux_ck {
427 compatible = "ti,mux-clock";
428 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
433 mcasp_gfclk: mcasp_gfclk {
435 compatible = "ti,mux-clock";
436 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
441 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
443 compatible = "ti,mux-clock";
444 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
449 mcbsp1_gfclk: mcbsp1_gfclk {
451 compatible = "ti,mux-clock";
452 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
457 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
459 compatible = "ti,mux-clock";
460 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
465 mcbsp2_gfclk: mcbsp2_gfclk {
467 compatible = "ti,mux-clock";
468 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
473 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
475 compatible = "ti,mux-clock";
476 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
481 mcbsp3_gfclk: mcbsp3_gfclk {
483 compatible = "ti,mux-clock";
484 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
489 timer5_gfclk_mux: timer5_gfclk_mux {
491 compatible = "ti,mux-clock";
492 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
497 timer6_gfclk_mux: timer6_gfclk_mux {
499 compatible = "ti,mux-clock";
500 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
505 timer7_gfclk_mux: timer7_gfclk_mux {
507 compatible = "ti,mux-clock";
508 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
513 timer8_gfclk_mux: timer8_gfclk_mux {
515 compatible = "ti,mux-clock";
516 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
523 compatible = "fixed-clock";
524 clock-frequency = <0>;
528 sys_clkin: sys_clkin {
530 compatible = "ti,mux-clock";
531 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
533 ti,index-starts-at-one;
536 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
538 compatible = "ti,mux-clock";
539 clocks = <&sys_clkin>, <&sys_32k_ck>;
543 abe_dpll_clk_mux: abe_dpll_clk_mux {
545 compatible = "ti,mux-clock";
546 clocks = <&sys_clkin>, <&sys_32k_ck>;
550 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
552 compatible = "fixed-factor-clock";
553 clocks = <&sys_clkin>;
558 dss_syc_gfclk_div: dss_syc_gfclk_div {
560 compatible = "fixed-factor-clock";
561 clocks = <&sys_clkin>;
566 wkupaon_iclk_mux: wkupaon_iclk_mux {
568 compatible = "ti,mux-clock";
569 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
573 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
575 compatible = "fixed-factor-clock";
576 clocks = <&wkupaon_iclk_mux>;
581 gpio1_dbclk: gpio1_dbclk {
583 compatible = "ti,gate-clock";
584 clocks = <&sys_32k_ck>;
589 timer1_gfclk_mux: timer1_gfclk_mux {
591 compatible = "ti,mux-clock";
592 clocks = <&sys_clkin>, <&sys_32k_ck>;
598 dpll_per_ck: dpll_per_ck {
600 compatible = "ti,omap4-dpll-clock";
601 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
602 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
605 dpll_per_x2_ck: dpll_per_x2_ck {
607 compatible = "ti,omap4-dpll-x2-clock";
608 clocks = <&dpll_per_ck>;
611 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
613 compatible = "ti,divider-clock";
614 clocks = <&dpll_per_x2_ck>;
617 ti,index-starts-at-one;
620 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
622 compatible = "ti,divider-clock";
623 clocks = <&dpll_per_x2_ck>;
626 ti,index-starts-at-one;
629 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
631 compatible = "ti,divider-clock";
632 clocks = <&dpll_per_x2_ck>;
635 ti,index-starts-at-one;
638 dpll_per_m2_ck: dpll_per_m2_ck {
640 compatible = "ti,divider-clock";
641 clocks = <&dpll_per_ck>;
644 ti,index-starts-at-one;
647 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
649 compatible = "ti,divider-clock";
650 clocks = <&dpll_per_x2_ck>;
653 ti,index-starts-at-one;
656 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
658 compatible = "ti,divider-clock";
659 clocks = <&dpll_per_x2_ck>;
662 ti,index-starts-at-one;
665 dpll_unipro1_ck: dpll_unipro1_ck {
667 compatible = "ti,omap4-dpll-clock";
668 clocks = <&sys_clkin>, <&sys_clkin>;
669 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
672 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
674 compatible = "fixed-factor-clock";
675 clocks = <&dpll_unipro1_ck>;
680 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
682 compatible = "ti,divider-clock";
683 clocks = <&dpll_unipro1_ck>;
686 ti,index-starts-at-one;
689 dpll_unipro2_ck: dpll_unipro2_ck {
691 compatible = "ti,omap4-dpll-clock";
692 clocks = <&sys_clkin>, <&sys_clkin>;
693 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
696 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
698 compatible = "fixed-factor-clock";
699 clocks = <&dpll_unipro2_ck>;
704 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
706 compatible = "ti,divider-clock";
707 clocks = <&dpll_unipro2_ck>;
710 ti,index-starts-at-one;
713 dpll_usb_ck: dpll_usb_ck {
715 compatible = "ti,omap4-dpll-j-type-clock";
716 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
717 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
720 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
722 compatible = "fixed-factor-clock";
723 clocks = <&dpll_usb_ck>;
728 dpll_usb_m2_ck: dpll_usb_m2_ck {
730 compatible = "ti,divider-clock";
731 clocks = <&dpll_usb_ck>;
734 ti,index-starts-at-one;
737 func_128m_clk: func_128m_clk {
739 compatible = "fixed-factor-clock";
740 clocks = <&dpll_per_h11x2_ck>;
745 func_12m_fclk: func_12m_fclk {
747 compatible = "fixed-factor-clock";
748 clocks = <&dpll_per_m2x2_ck>;
753 func_24m_clk: func_24m_clk {
755 compatible = "fixed-factor-clock";
756 clocks = <&dpll_per_m2_ck>;
761 func_48m_fclk: func_48m_fclk {
763 compatible = "fixed-factor-clock";
764 clocks = <&dpll_per_m2x2_ck>;
769 func_96m_fclk: func_96m_fclk {
771 compatible = "fixed-factor-clock";
772 clocks = <&dpll_per_m2x2_ck>;
777 l3init_60m_fclk: l3init_60m_fclk {
779 compatible = "ti,divider-clock";
780 clocks = <&dpll_usb_m2_ck>;
782 ti,dividers = <1>, <8>;
785 dss_32khz_clk: dss_32khz_clk {
787 compatible = "ti,gate-clock";
788 clocks = <&sys_32k_ck>;
793 dss_48mhz_clk: dss_48mhz_clk {
795 compatible = "ti,gate-clock";
796 clocks = <&func_48m_fclk>;
801 dss_dss_clk: dss_dss_clk {
803 compatible = "ti,gate-clock";
804 clocks = <&dpll_per_h12x2_ck>;
810 dss_sys_clk: dss_sys_clk {
812 compatible = "ti,gate-clock";
813 clocks = <&dss_syc_gfclk_div>;
818 gpio2_dbclk: gpio2_dbclk {
820 compatible = "ti,gate-clock";
821 clocks = <&sys_32k_ck>;
826 gpio3_dbclk: gpio3_dbclk {
828 compatible = "ti,gate-clock";
829 clocks = <&sys_32k_ck>;
834 gpio4_dbclk: gpio4_dbclk {
836 compatible = "ti,gate-clock";
837 clocks = <&sys_32k_ck>;
842 gpio5_dbclk: gpio5_dbclk {
844 compatible = "ti,gate-clock";
845 clocks = <&sys_32k_ck>;
850 gpio6_dbclk: gpio6_dbclk {
852 compatible = "ti,gate-clock";
853 clocks = <&sys_32k_ck>;
858 gpio7_dbclk: gpio7_dbclk {
860 compatible = "ti,gate-clock";
861 clocks = <&sys_32k_ck>;
866 gpio8_dbclk: gpio8_dbclk {
868 compatible = "ti,gate-clock";
869 clocks = <&sys_32k_ck>;
874 iss_ctrlclk: iss_ctrlclk {
876 compatible = "ti,gate-clock";
877 clocks = <&func_96m_fclk>;
882 lli_txphy_clk: lli_txphy_clk {
884 compatible = "ti,gate-clock";
885 clocks = <&dpll_unipro1_clkdcoldo>;
890 lli_txphy_ls_clk: lli_txphy_ls_clk {
892 compatible = "ti,gate-clock";
893 clocks = <&dpll_unipro1_m2_ck>;
898 mmc1_32khz_clk: mmc1_32khz_clk {
900 compatible = "ti,gate-clock";
901 clocks = <&sys_32k_ck>;
906 sata_ref_clk: sata_ref_clk {
908 compatible = "ti,gate-clock";
909 clocks = <&sys_clkin>;
914 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
916 compatible = "ti,gate-clock";
917 clocks = <&dpll_usb_m2_ck>;
922 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
924 compatible = "ti,gate-clock";
925 clocks = <&dpll_usb_m2_ck>;
930 usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
932 compatible = "ti,gate-clock";
933 clocks = <&dpll_usb_m2_ck>;
938 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
940 compatible = "ti,gate-clock";
941 clocks = <&l3init_60m_fclk>;
946 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
948 compatible = "ti,gate-clock";
949 clocks = <&l3init_60m_fclk>;
954 usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
956 compatible = "ti,gate-clock";
957 clocks = <&l3init_60m_fclk>;
962 utmi_p1_gfclk: utmi_p1_gfclk {
964 compatible = "ti,mux-clock";
965 clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
970 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
972 compatible = "ti,gate-clock";
973 clocks = <&utmi_p1_gfclk>;
978 utmi_p2_gfclk: utmi_p2_gfclk {
980 compatible = "ti,mux-clock";
981 clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
986 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
988 compatible = "ti,gate-clock";
989 clocks = <&utmi_p2_gfclk>;
994 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
996 compatible = "ti,gate-clock";
997 clocks = <&l3init_60m_fclk>;
1002 usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
1004 compatible = "ti,gate-clock";
1005 clocks = <&dpll_usb_clkdcoldo>;
1010 usb_phy_cm_clk32k: usb_phy_cm_clk32k {
1012 compatible = "ti,gate-clock";
1013 clocks = <&sys_32k_ck>;
1018 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
1020 compatible = "ti,gate-clock";
1021 clocks = <&l3init_60m_fclk>;
1026 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
1028 compatible = "ti,gate-clock";
1029 clocks = <&l3init_60m_fclk>;
1034 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
1036 compatible = "ti,gate-clock";
1037 clocks = <&l3init_60m_fclk>;
1038 ti,bit-shift = <10>;
1042 fdif_fclk: fdif_fclk {
1044 compatible = "ti,divider-clock";
1045 clocks = <&dpll_per_h11x2_ck>;
1046 ti,bit-shift = <24>;
1051 gpu_core_gclk_mux: gpu_core_gclk_mux {
1053 compatible = "ti,mux-clock";
1054 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1055 ti,bit-shift = <24>;
1059 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1061 compatible = "ti,mux-clock";
1062 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1063 ti,bit-shift = <25>;
1067 hsi_fclk: hsi_fclk {
1069 compatible = "ti,divider-clock";
1070 clocks = <&dpll_per_m2x2_ck>;
1071 ti,bit-shift = <24>;
1076 mmc1_fclk_mux: mmc1_fclk_mux {
1078 compatible = "ti,mux-clock";
1079 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1080 ti,bit-shift = <24>;
1084 mmc1_fclk: mmc1_fclk {
1086 compatible = "ti,divider-clock";
1087 clocks = <&mmc1_fclk_mux>;
1088 ti,bit-shift = <25>;
1093 mmc2_fclk_mux: mmc2_fclk_mux {
1095 compatible = "ti,mux-clock";
1096 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1097 ti,bit-shift = <24>;
1101 mmc2_fclk: mmc2_fclk {
1103 compatible = "ti,divider-clock";
1104 clocks = <&mmc2_fclk_mux>;
1105 ti,bit-shift = <25>;
1110 timer10_gfclk_mux: timer10_gfclk_mux {
1112 compatible = "ti,mux-clock";
1113 clocks = <&sys_clkin>, <&sys_32k_ck>;
1114 ti,bit-shift = <24>;
1118 timer11_gfclk_mux: timer11_gfclk_mux {
1120 compatible = "ti,mux-clock";
1121 clocks = <&sys_clkin>, <&sys_32k_ck>;
1122 ti,bit-shift = <24>;
1126 timer2_gfclk_mux: timer2_gfclk_mux {
1128 compatible = "ti,mux-clock";
1129 clocks = <&sys_clkin>, <&sys_32k_ck>;
1130 ti,bit-shift = <24>;
1134 timer3_gfclk_mux: timer3_gfclk_mux {
1136 compatible = "ti,mux-clock";
1137 clocks = <&sys_clkin>, <&sys_32k_ck>;
1138 ti,bit-shift = <24>;
1142 timer4_gfclk_mux: timer4_gfclk_mux {
1144 compatible = "ti,mux-clock";
1145 clocks = <&sys_clkin>, <&sys_32k_ck>;
1146 ti,bit-shift = <24>;
1150 timer9_gfclk_mux: timer9_gfclk_mux {
1152 compatible = "ti,mux-clock";
1153 clocks = <&sys_clkin>, <&sys_32k_ck>;
1154 ti,bit-shift = <24>;
1159 &cm_core_clockdomains {
1160 l3init_clkdm: l3init_clkdm {
1161 compatible = "ti,clockdomain";
1162 clocks = <&dpll_usb_ck>;
1167 auxclk0_src_gate_ck: auxclk0_src_gate_ck {
1169 compatible = "ti,composite-no-wait-gate-clock";
1170 clocks = <&dpll_core_m3x2_ck>;
1175 auxclk0_src_mux_ck: auxclk0_src_mux_ck {
1177 compatible = "ti,composite-mux-clock";
1178 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1183 auxclk0_src_ck: auxclk0_src_ck {
1185 compatible = "ti,composite-clock";
1186 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
1189 auxclk0_ck: auxclk0_ck {
1191 compatible = "ti,divider-clock";
1192 clocks = <&auxclk0_src_ck>;
1193 ti,bit-shift = <16>;
1198 auxclk1_src_gate_ck: auxclk1_src_gate_ck {
1200 compatible = "ti,composite-no-wait-gate-clock";
1201 clocks = <&dpll_core_m3x2_ck>;
1206 auxclk1_src_mux_ck: auxclk1_src_mux_ck {
1208 compatible = "ti,composite-mux-clock";
1209 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1214 auxclk1_src_ck: auxclk1_src_ck {
1216 compatible = "ti,composite-clock";
1217 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
1220 auxclk1_ck: auxclk1_ck {
1222 compatible = "ti,divider-clock";
1223 clocks = <&auxclk1_src_ck>;
1224 ti,bit-shift = <16>;
1229 auxclk2_src_gate_ck: auxclk2_src_gate_ck {
1231 compatible = "ti,composite-no-wait-gate-clock";
1232 clocks = <&dpll_core_m3x2_ck>;
1237 auxclk2_src_mux_ck: auxclk2_src_mux_ck {
1239 compatible = "ti,composite-mux-clock";
1240 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1245 auxclk2_src_ck: auxclk2_src_ck {
1247 compatible = "ti,composite-clock";
1248 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
1251 auxclk2_ck: auxclk2_ck {
1253 compatible = "ti,divider-clock";
1254 clocks = <&auxclk2_src_ck>;
1255 ti,bit-shift = <16>;
1260 auxclk3_src_gate_ck: auxclk3_src_gate_ck {
1262 compatible = "ti,composite-no-wait-gate-clock";
1263 clocks = <&dpll_core_m3x2_ck>;
1268 auxclk3_src_mux_ck: auxclk3_src_mux_ck {
1270 compatible = "ti,composite-mux-clock";
1271 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1276 auxclk3_src_ck: auxclk3_src_ck {
1278 compatible = "ti,composite-clock";
1279 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1282 auxclk3_ck: auxclk3_ck {
1284 compatible = "ti,divider-clock";
1285 clocks = <&auxclk3_src_ck>;
1286 ti,bit-shift = <16>;
1291 auxclk4_src_gate_ck: auxclk4_src_gate_ck {
1293 compatible = "ti,composite-no-wait-gate-clock";
1294 clocks = <&dpll_core_m3x2_ck>;
1299 auxclk4_src_mux_ck: auxclk4_src_mux_ck {
1301 compatible = "ti,composite-mux-clock";
1302 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1307 auxclk4_src_ck: auxclk4_src_ck {
1309 compatible = "ti,composite-clock";
1310 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1313 auxclk4_ck: auxclk4_ck {
1315 compatible = "ti,divider-clock";
1316 clocks = <&auxclk4_src_ck>;
1317 ti,bit-shift = <16>;
1322 auxclkreq0_ck: auxclkreq0_ck {
1324 compatible = "ti,mux-clock";
1325 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1330 auxclkreq1_ck: auxclkreq1_ck {
1332 compatible = "ti,mux-clock";
1333 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1338 auxclkreq2_ck: auxclkreq2_ck {
1340 compatible = "ti,mux-clock";
1341 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1346 auxclkreq3_ck: auxclkreq3_ck {
1348 compatible = "ti,mux-clock";
1349 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;