arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 /*
  11  * Carveout for multimedia usecases
  12  * It should be the last 48MB of the first 512MB memory part
  13  * In theory, it should not even exist. That zone should be reserved
  14  * dynamically during the .reserve callback.
  15  */
  16 /memreserve/ 0x9d000000 0x03000000;
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         compatible = "ti,omap5";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         cpus {
  37                 cpu@0 {
  38                         compatible = "arm,cortex-a15";
  39                 };
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a15";
  42                 };
  43         };
  44
  45         timer {
  46                 compatible = "arm,armv7-timer";
  47                 /* PPI secure/nonsecure IRQ, active low level-sensitive */
  48                 interrupts = <1 13 0x308>,
  49                              <1 14 0x308>,
  50                              <1 11 0x308>,
  51                              <1 10 0x308>;
  52                 clock-frequency = <6144000>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63         };
  64
  65         /*
  66          * The soc node represents the soc top level view. It is uses for IPs
  67          * that are not memory mapped in the MPU view or for the MPU itself.
  68          */
  69         soc {
  70                 compatible = "ti,omap-infra";
  71                 mpu {
  72                         compatible = "ti,omap5-mpu";
  73                         ti,hwmods = "mpu";
  74                 };
  75         };
  76
  77         /*
  78          * XXX: Use a flat representation of the OMAP3 interconnect.
  79          * The real OMAP interconnect network is quite complex.
  80          * Since that will not bring real advantage to represent that in DT for
  81          * the moment, just use a fake OCP bus entry to represent the whole bus
  82          * hierarchy.
  83          */
  84         ocp {
  85                 compatible = "ti,omap4-l3-noc", "simple-bus";
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges;
  89                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  90
  91                 counter32k: counter@4ae04000 {
  92                         compatible = "ti,omap-counter32k";
  93                         reg = <0x4ae04000 0x40>;
  94                         ti,hwmods = "counter_32k";
  95                 };
  96
  97                 omap5_pmx_core: pinmux@4a002840 {
  98                         compatible = "ti,omap4-padconf", "pinctrl-single";
  99                         reg = <0x4a002840 0x01b6>;
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         pinctrl-single,register-width = <16>;
 103                         pinctrl-single,function-mask = <0x7fff>;
 104                 };
 105                 omap5_pmx_wkup: pinmux@4ae0c840 {
 106                         compatible = "ti,omap4-padconf", "pinctrl-single";
 107                         reg = <0x4ae0c840 0x0038>;
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                         pinctrl-single,register-width = <16>;
 111                         pinctrl-single,function-mask = <0x7fff>;
 112                 };
 113
 114                 sdma: dma-controller@4a056000 {
 115                         compatible = "ti,omap4430-sdma";
 116                         reg = <0x4a056000 0x1000>;
 117                         interrupts = <0 12 0x4>,
 118                                      <0 13 0x4>,
 119                                      <0 14 0x4>,
 120                                      <0 15 0x4>;
 121                         #dma-cells = <1>;
 122                         #dma-channels = <32>;
 123                         #dma-requests = <127>;
 124                 };
 125
 126                 gpio1: gpio@4ae10000 {
 127                         compatible = "ti,omap4-gpio";
 128                         reg = <0x4ae10000 0x200>;
 129                         interrupts = <0 29 0x4>;
 130                         ti,hwmods = "gpio1";
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133                         interrupt-controller;
 134                         #interrupt-cells = <2>;
 135                 };
 136
 137                 gpio2: gpio@48055000 {
 138                         compatible = "ti,omap4-gpio";
 139                         reg = <0x48055000 0x200>;
 140                         interrupts = <0 30 0x4>;
 141                         ti,hwmods = "gpio2";
 142                         gpio-controller;
 143                         #gpio-cells = <2>;
 144                         interrupt-controller;
 145                         #interrupt-cells = <2>;
 146                 };
 147
 148                 gpio3: gpio@48057000 {
 149                         compatible = "ti,omap4-gpio";
 150                         reg = <0x48057000 0x200>;
 151                         interrupts = <0 31 0x4>;
 152                         ti,hwmods = "gpio3";
 153                         gpio-controller;
 154                         #gpio-cells = <2>;
 155                         interrupt-controller;
 156                         #interrupt-cells = <2>;
 157                 };
 158
 159                 gpio4: gpio@48059000 {
 160                         compatible = "ti,omap4-gpio";
 161                         reg = <0x48059000 0x200>;
 162                         interrupts = <0 32 0x4>;
 163                         ti,hwmods = "gpio4";
 164                         gpio-controller;
 165                         #gpio-cells = <2>;
 166                         interrupt-controller;
 167                         #interrupt-cells = <2>;
 168                 };
 169
 170                 gpio5: gpio@4805b000 {
 171                         compatible = "ti,omap4-gpio";
 172                         reg = <0x4805b000 0x200>;
 173                         interrupts = <0 33 0x4>;
 174                         ti,hwmods = "gpio5";
 175                         gpio-controller;
 176                         #gpio-cells = <2>;
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                 };
 180
 181                 gpio6: gpio@4805d000 {
 182                         compatible = "ti,omap4-gpio";
 183                         reg = <0x4805d000 0x200>;
 184                         interrupts = <0 34 0x4>;
 185                         ti,hwmods = "gpio6";
 186                         gpio-controller;
 187                         #gpio-cells = <2>;
 188                         interrupt-controller;
 189                         #interrupt-cells = <2>;
 190                 };
 191
 192                 gpio7: gpio@48051000 {
 193                         compatible = "ti,omap4-gpio";
 194                         reg = <0x48051000 0x200>;
 195                         interrupts = <0 35 0x4>;
 196                         ti,hwmods = "gpio7";
 197                         gpio-controller;
 198                         #gpio-cells = <2>;
 199                         interrupt-controller;
 200                         #interrupt-cells = <2>;
 201                 };
 202
 203                 gpio8: gpio@48053000 {
 204                         compatible = "ti,omap4-gpio";
 205                         reg = <0x48053000 0x200>;
 206                         interrupts = <0 121 0x4>;
 207                         ti,hwmods = "gpio8";
 208                         gpio-controller;
 209                         #gpio-cells = <2>;
 210                         interrupt-controller;
 211                         #interrupt-cells = <2>;
 212                 };
 213
 214                 gpmc: gpmc@50000000 {
 215                         compatible = "ti,omap4430-gpmc";
 216                         reg = <0x50000000 0x1000>;
 217                         #address-cells = <2>;
 218                         #size-cells = <1>;
 219                         interrupts = <0 20 0x4>;
 220                         gpmc,num-cs = <8>;
 221                         gpmc,num-waitpins = <4>;
 222                         ti,hwmods = "gpmc";
 223                 };
 224
 225                 i2c1: i2c@48070000 {
 226                         compatible = "ti,omap4-i2c";
 227                         reg = <0x48070000 0x100>;
 228                         interrupts = <0 56 0x4>;
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         ti,hwmods = "i2c1";
 232                 };
 233
 234                 i2c2: i2c@48072000 {
 235                         compatible = "ti,omap4-i2c";
 236                         reg = <0x48072000 0x100>;
 237                         interrupts = <0 57 0x4>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         ti,hwmods = "i2c2";
 241                 };
 242
 243                 i2c3: i2c@48060000 {
 244                         compatible = "ti,omap4-i2c";
 245                         reg = <0x48060000 0x100>;
 246                         interrupts = <0 61 0x4>;
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         ti,hwmods = "i2c3";
 250                 };
 251
 252                 i2c4: i2c@4807a000 {
 253                         compatible = "ti,omap4-i2c";
 254                         reg = <0x4807a000 0x100>;
 255                         interrupts = <0 62 0x4>;
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         ti,hwmods = "i2c4";
 259                 };
 260
 261                 i2c5: i2c@4807c000 {
 262                         compatible = "ti,omap4-i2c";
 263                         reg = <0x4807c000 0x100>;
 264                         interrupts = <0 60 0x4>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         ti,hwmods = "i2c5";
 268                 };
 269
 270                 mcspi1: spi@48098000 {
 271                         compatible = "ti,omap4-mcspi";
 272                         reg = <0x48098000 0x200>;
 273                         interrupts = <0 65 0x4>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         ti,hwmods = "mcspi1";
 277                         ti,spi-num-cs = <4>;
 278                         dmas = <&sdma 35>,
 279                                <&sdma 36>,
 280                                <&sdma 37>,
 281                                <&sdma 38>,
 282                                <&sdma 39>,
 283                                <&sdma 40>,
 284                                <&sdma 41>,
 285                                <&sdma 42>;
 286                         dma-names = "tx0", "rx0", "tx1", "rx1",
 287                                     "tx2", "rx2", "tx3", "rx3";
 288                 };
 289
 290                 mcspi2: spi@4809a000 {
 291                         compatible = "ti,omap4-mcspi";
 292                         reg = <0x4809a000 0x200>;
 293                         interrupts = <0 66 0x4>;
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                         ti,hwmods = "mcspi2";
 297                         ti,spi-num-cs = <2>;
 298                         dmas = <&sdma 43>,
 299                                <&sdma 44>,
 300                                <&sdma 45>,
 301                                <&sdma 46>;
 302                         dma-names = "tx0", "rx0", "tx1", "rx1";
 303                 };
 304
 305                 mcspi3: spi@480b8000 {
 306                         compatible = "ti,omap4-mcspi";
 307                         reg = <0x480b8000 0x200>;
 308                         interrupts = <0 91 0x4>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         ti,hwmods = "mcspi3";
 312                         ti,spi-num-cs = <2>;
 313                         dmas = <&sdma 15>, <&sdma 16>;
 314                         dma-names = "tx0", "rx0";
 315                 };
 316
 317                 mcspi4: spi@480ba000 {
 318                         compatible = "ti,omap4-mcspi";
 319                         reg = <0x480ba000 0x200>;
 320                         interrupts = <0 48 0x4>;
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         ti,hwmods = "mcspi4";
 324                         ti,spi-num-cs = <1>;
 325                         dmas = <&sdma 70>, <&sdma 71>;
 326                         dma-names = "tx0", "rx0";
 327                 };
 328
 329                 uart1: serial@4806a000 {
 330                         compatible = "ti,omap4-uart";
 331                         reg = <0x4806a000 0x100>;
 332                         interrupts = <0 72 0x4>;
 333                         ti,hwmods = "uart1";
 334                         clock-frequency = <48000000>;
 335                 };
 336
 337                 uart2: serial@4806c000 {
 338                         compatible = "ti,omap4-uart";
 339                         reg = <0x4806c000 0x100>;
 340                         interrupts = <0 73 0x4>;
 341                         ti,hwmods = "uart2";
 342                         clock-frequency = <48000000>;
 343                 };
 344
 345                 uart3: serial@48020000 {
 346                         compatible = "ti,omap4-uart";
 347                         reg = <0x48020000 0x100>;
 348                         interrupts = <0 74 0x4>;
 349                         ti,hwmods = "uart3";
 350                         clock-frequency = <48000000>;
 351                 };
 352
 353                 uart4: serial@4806e000 {
 354                         compatible = "ti,omap4-uart";
 355                         reg = <0x4806e000 0x100>;
 356                         interrupts = <0 70 0x4>;
 357                         ti,hwmods = "uart4";
 358                         clock-frequency = <48000000>;
 359                 };
 360
 361                 uart5: serial@48066000 {
 362                         compatible = "ti,omap4-uart";
 363                         reg = <0x48066000 0x100>;
 364                         interrupts = <0 105 0x4>;
 365                         ti,hwmods = "uart5";
 366                         clock-frequency = <48000000>;
 367                 };
 368
 369                 uart6: serial@48068000 {
 370                         compatible = "ti,omap4-uart";
 371                         reg = <0x48068000 0x100>;
 372                         interrupts = <0 106 0x4>;
 373                         ti,hwmods = "uart6";
 374                         clock-frequency = <48000000>;
 375                 };
 376
 377                 mmc1: mmc@4809c000 {
 378                         compatible = "ti,omap4-hsmmc";
 379                         reg = <0x4809c000 0x400>;
 380                         interrupts = <0 83 0x4>;
 381                         ti,hwmods = "mmc1";
 382                         ti,dual-volt;
 383                         ti,needs-special-reset;
 384                         dmas = <&sdma 61>, <&sdma 62>;
 385                         dma-names = "tx", "rx";
 386                 };
 387
 388                 mmc2: mmc@480b4000 {
 389                         compatible = "ti,omap4-hsmmc";
 390                         reg = <0x480b4000 0x400>;
 391                         interrupts = <0 86 0x4>;
 392                         ti,hwmods = "mmc2";
 393                         ti,needs-special-reset;
 394                         dmas = <&sdma 47>, <&sdma 48>;
 395                         dma-names = "tx", "rx";
 396                 };
 397
 398                 mmc3: mmc@480ad000 {
 399                         compatible = "ti,omap4-hsmmc";
 400                         reg = <0x480ad000 0x400>;
 401                         interrupts = <0 94 0x4>;
 402                         ti,hwmods = "mmc3";
 403                         ti,needs-special-reset;
 404                         dmas = <&sdma 77>, <&sdma 78>;
 405                         dma-names = "tx", "rx";
 406                 };
 407
 408                 mmc4: mmc@480d1000 {
 409                         compatible = "ti,omap4-hsmmc";
 410                         reg = <0x480d1000 0x400>;
 411                         interrupts = <0 96 0x4>;
 412                         ti,hwmods = "mmc4";
 413                         ti,needs-special-reset;
 414                         dmas = <&sdma 57>, <&sdma 58>;
 415                         dma-names = "tx", "rx";
 416                 };
 417
 418                 mmc5: mmc@480d5000 {
 419                         compatible = "ti,omap4-hsmmc";
 420                         reg = <0x480d5000 0x400>;
 421                         interrupts = <0 59 0x4>;
 422                         ti,hwmods = "mmc5";
 423                         ti,needs-special-reset;
 424                         dmas = <&sdma 59>, <&sdma 60>;
 425                         dma-names = "tx", "rx";
 426                 };
 427
 428                 keypad: keypad@4ae1c000 {
 429                         compatible = "ti,omap4-keypad";
 430                         ti,hwmods = "kbd";
 431                 };
 432
 433                 mcpdm: mcpdm@40132000 {
 434                         compatible = "ti,omap4-mcpdm";
 435                         reg = <0x40132000 0x7f>, /* MPU private access */
 436                               <0x49032000 0x7f>; /* L3 Interconnect */
 437                         reg-names = "mpu", "dma";
 438                         interrupts = <0 112 0x4>;
 439                         ti,hwmods = "mcpdm";
 440                         dmas = <&sdma 65>,
 441                                <&sdma 66>;
 442                         dma-names = "up_link", "dn_link";
 443                 };
 444
 445                 dmic: dmic@4012e000 {
 446                         compatible = "ti,omap4-dmic";
 447                         reg = <0x4012e000 0x7f>, /* MPU private access */
 448                               <0x4902e000 0x7f>; /* L3 Interconnect */
 449                         reg-names = "mpu", "dma";
 450                         interrupts = <0 114 0x4>;
 451                         ti,hwmods = "dmic";
 452                         dmas = <&sdma 67>;
 453                         dma-names = "up_link";
 454                 };
 455
 456                 mcbsp1: mcbsp@40122000 {
 457                         compatible = "ti,omap4-mcbsp";
 458                         reg = <0x40122000 0xff>, /* MPU private access */
 459                               <0x49022000 0xff>; /* L3 Interconnect */
 460                         reg-names = "mpu", "dma";
 461                         interrupts = <0 17 0x4>;
 462                         interrupt-names = "common";
 463                         ti,buffer-size = <128>;
 464                         ti,hwmods = "mcbsp1";
 465                         dmas = <&sdma 33>,
 466                                <&sdma 34>;
 467                         dma-names = "tx", "rx";
 468                 };
 469
 470                 mcbsp2: mcbsp@40124000 {
 471                         compatible = "ti,omap4-mcbsp";
 472                         reg = <0x40124000 0xff>, /* MPU private access */
 473                               <0x49024000 0xff>; /* L3 Interconnect */
 474                         reg-names = "mpu", "dma";
 475                         interrupts = <0 22 0x4>;
 476                         interrupt-names = "common";
 477                         ti,buffer-size = <128>;
 478                         ti,hwmods = "mcbsp2";
 479                         dmas = <&sdma 17>,
 480                                <&sdma 18>;
 481                         dma-names = "tx", "rx";
 482                 };
 483
 484                 mcbsp3: mcbsp@40126000 {
 485                         compatible = "ti,omap4-mcbsp";
 486                         reg = <0x40126000 0xff>, /* MPU private access */
 487                               <0x49026000 0xff>; /* L3 Interconnect */
 488                         reg-names = "mpu", "dma";
 489                         interrupts = <0 23 0x4>;
 490                         interrupt-names = "common";
 491                         ti,buffer-size = <128>;
 492                         ti,hwmods = "mcbsp3";
 493                         dmas = <&sdma 19>,
 494                                <&sdma 20>;
 495                         dma-names = "tx", "rx";
 496                 };
 497
 498                 timer1: timer@4ae18000 {
 499                         compatible = "ti,omap2-timer";
 500                         reg = <0x4ae18000 0x80>;
 501                         interrupts = <0 37 0x4>;
 502                         ti,hwmods = "timer1";
 503                         ti,timer-alwon;
 504                 };
 505
 506                 timer2: timer@48032000 {
 507                         compatible = "ti,omap2-timer";
 508                         reg = <0x48032000 0x80>;
 509                         interrupts = <0 38 0x4>;
 510                         ti,hwmods = "timer2";
 511                 };
 512
 513                 timer3: timer@48034000 {
 514                         compatible = "ti,omap2-timer";
 515                         reg = <0x48034000 0x80>;
 516                         interrupts = <0 39 0x4>;
 517                         ti,hwmods = "timer3";
 518                 };
 519
 520                 timer4: timer@48036000 {
 521                         compatible = "ti,omap2-timer";
 522                         reg = <0x48036000 0x80>;
 523                         interrupts = <0 40 0x4>;
 524                         ti,hwmods = "timer4";
 525                 };
 526
 527                 timer5: timer@40138000 {
 528                         compatible = "ti,omap2-timer";
 529                         reg = <0x40138000 0x80>,
 530                               <0x49038000 0x80>;
 531                         interrupts = <0 41 0x4>;
 532                         ti,hwmods = "timer5";
 533                         ti,timer-dsp;
 534                 };
 535
 536                 timer6: timer@4013a000 {
 537                         compatible = "ti,omap2-timer";
 538                         reg = <0x4013a000 0x80>,
 539                               <0x4903a000 0x80>;
 540                         interrupts = <0 42 0x4>;
 541                         ti,hwmods = "timer6";
 542                         ti,timer-dsp;
 543                         ti,timer-pwm;
 544                 };
 545
 546                 timer7: timer@4013c000 {
 547                         compatible = "ti,omap2-timer";
 548                         reg = <0x4013c000 0x80>,
 549                               <0x4903c000 0x80>;
 550                         interrupts = <0 43 0x4>;
 551                         ti,hwmods = "timer7";
 552                         ti,timer-dsp;
 553                 };
 554
 555                 timer8: timer@4013e000 {
 556                         compatible = "ti,omap2-timer";
 557                         reg = <0x4013e000 0x80>,
 558                               <0x4903e000 0x80>;
 559                         interrupts = <0 44 0x4>;
 560                         ti,hwmods = "timer8";
 561                         ti,timer-dsp;
 562                         ti,timer-pwm;
 563                 };
 564
 565                 timer9: timer@4803e000 {
 566                         compatible = "ti,omap2-timer";
 567                         reg = <0x4803e000 0x80>;
 568                         interrupts = <0 45 0x4>;
 569                         ti,hwmods = "timer9";
 570                 };
 571
 572                 timer10: timer@48086000 {
 573                         compatible = "ti,omap2-timer";
 574                         reg = <0x48086000 0x80>;
 575                         interrupts = <0 46 0x4>;
 576                         ti,hwmods = "timer10";
 577                 };
 578
 579                 timer11: timer@48088000 {
 580                         compatible = "ti,omap2-timer";
 581                         reg = <0x48088000 0x80>;
 582                         interrupts = <0 47 0x4>;
 583                         ti,hwmods = "timer11";
 584                         ti,timer-pwm;
 585                 };
 586
 587                 emif1: emif@0x4c000000 {
 588                         compatible      = "ti,emif-4d5";
 589                         ti,hwmods       = "emif1";
 590                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 591                         reg = <0x4c000000 0x400>;
 592                         interrupts = <0 110 0x4>;
 593                         hw-caps-read-idle-ctrl;
 594                         hw-caps-ll-interface;
 595                         hw-caps-temp-alert;
 596                 };
 597
 598                 emif2: emif@0x4d000000 {
 599                         compatible      = "ti,emif-4d5";
 600                         ti,hwmods       = "emif2";
 601                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 602                         reg = <0x4d000000 0x400>;
 603                         interrupts = <0 111 0x4>;
 604                         hw-caps-read-idle-ctrl;
 605                         hw-caps-ll-interface;
 606                         hw-caps-temp-alert;
 607                 };
 608
 609                 omap_control_usb: omap-control-usb@4a002300 {
 610                         compatible = "ti,omap-control-usb";
 611                         reg = <0x4a002300 0x4>,
 612                               <0x4a002370 0x4>;
 613                         reg-names = "control_dev_conf", "phy_power_usb";
 614                         ti,type = <2>;
 615                 };
 616
 617                 omap_dwc3@4a020000 {
 618                         compatible = "ti,dwc3";
 619                         ti,hwmods = "usb_otg_ss";
 620                         reg = <0x4a020000 0x1000>;
 621                         interrupts = <0 93 4>;
 622                         #address-cells = <1>;
 623                         #size-cells = <1>;
 624                         utmi-mode = <2>;
 625                         ranges;
 626                         dwc3@4a030000 {
 627                                 compatible = "synopsys,dwc3";
 628                                 reg = <0x4a030000 0x1000>;
 629                                 interrupts = <0 92 4>;
 630                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
 631                                 tx-fifo-resize;
 632                         };
 633                 };
 634
 635                 ocp2scp {
 636                         compatible = "ti,omap-ocp2scp";
 637                         #address-cells = <1>;
 638                         #size-cells = <1>;
 639                         ranges;
 640                         ti,hwmods = "ocp2scp1";
 641                         usb2_phy: usb2phy@4a084000 {
 642                                 compatible = "ti,omap-usb2";
 643                                 reg = <0x4a084000 0x7c>;
 644                                 ctrl-module = <&omap_control_usb>;
 645                         };
 646
 647                         usb3_phy: usb3phy@4a084400 {
 648                                 compatible = "ti,omap-usb3";
 649                                 reg = <0x4a084400 0x80>,
 650                                       <0x4a084800 0x64>,
 651                                       <0x4a084c00 0x40>;
 652                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 653                                 ctrl-module = <&omap_control_usb>;
 654                         };
 655                 };
 656         };
 657 };