2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 /include/ "skeleton.dtsi"
14 compatible = "ti,omap3430", "ti,omap3";
24 compatible = "arm,cortex-a8";
29 * The soc node represents the soc top level view. It is uses for IPs
30 * that are not memory mapped in the MPU view or for the MPU itself.
33 compatible = "ti,omap-infra";
35 compatible = "ti,omap3-mpu";
40 compatible = "ti,iva2.2";
44 compatible = "ti,omap3-c64";
50 * XXX: Use a flat representation of the OMAP3 interconnect.
51 * The real OMAP interconnect network is quite complex.
52 * Since that will not bring real advantage to represent that in DT for
53 * the moment, just use a fake OCP bus entry to represent the whole bus
57 compatible = "simple-bus";
61 ti,hwmods = "l3_main";
63 intc: interrupt-controller@48200000 {
64 compatible = "ti,omap2-intc";
66 #interrupt-cells = <1>;
68 reg = <0x48200000 0x1000>;
71 omap3_pmx_core: pinmux@48002030 {
72 compatible = "ti,omap3-padconf", "pinctrl-single";
73 reg = <0x48002030 0x05cc>;
76 pinctrl-single,register-width = <16>;
77 pinctrl-single,function-mask = <0x7fff>;
80 omap3_pmx_wkup: pinmux@0x48002a58 {
81 compatible = "ti,omap3-padconf", "pinctrl-single";
82 reg = <0x48002a58 0x5c>;
85 pinctrl-single,register-width = <16>;
86 pinctrl-single,function-mask = <0x7fff>;
89 gpio1: gpio@48310000 {
90 compatible = "ti,omap3-gpio";
95 #interrupt-cells = <1>;
98 gpio2: gpio@49050000 {
99 compatible = "ti,omap3-gpio";
103 interrupt-controller;
104 #interrupt-cells = <1>;
107 gpio3: gpio@49052000 {
108 compatible = "ti,omap3-gpio";
112 interrupt-controller;
113 #interrupt-cells = <1>;
116 gpio4: gpio@49054000 {
117 compatible = "ti,omap3-gpio";
121 interrupt-controller;
122 #interrupt-cells = <1>;
125 gpio5: gpio@49056000 {
126 compatible = "ti,omap3-gpio";
130 interrupt-controller;
131 #interrupt-cells = <1>;
134 gpio6: gpio@49058000 {
135 compatible = "ti,omap3-gpio";
139 interrupt-controller;
140 #interrupt-cells = <1>;
143 uart1: serial@4806a000 {
144 compatible = "ti,omap3-uart";
146 clock-frequency = <48000000>;
149 uart2: serial@4806c000 {
150 compatible = "ti,omap3-uart";
152 clock-frequency = <48000000>;
155 uart3: serial@49020000 {
156 compatible = "ti,omap3-uart";
158 clock-frequency = <48000000>;
162 compatible = "ti,omap3-i2c";
163 #address-cells = <1>;
169 compatible = "ti,omap3-i2c";
170 #address-cells = <1>;
176 compatible = "ti,omap3-i2c";
177 #address-cells = <1>;
182 mcspi1: spi@48098000 {
183 compatible = "ti,omap2-mcspi";
184 #address-cells = <1>;
186 ti,hwmods = "mcspi1";
190 mcspi2: spi@4809a000 {
191 compatible = "ti,omap2-mcspi";
192 #address-cells = <1>;
194 ti,hwmods = "mcspi2";
198 mcspi3: spi@480b8000 {
199 compatible = "ti,omap2-mcspi";
200 #address-cells = <1>;
202 ti,hwmods = "mcspi3";
206 mcspi4: spi@480ba000 {
207 compatible = "ti,omap2-mcspi";
208 #address-cells = <1>;
210 ti,hwmods = "mcspi4";
215 compatible = "ti,omap3-hsmmc";
221 compatible = "ti,omap3-hsmmc";
226 compatible = "ti,omap3-hsmmc";
231 compatible = "ti,omap3-wdt";
232 ti,hwmods = "wd_timer2";
235 mcbsp1: mcbsp@48074000 {
236 compatible = "ti,omap3-mcbsp";
237 reg = <0x48074000 0xff>;
239 interrupts = <16>, /* OCP compliant interrupt */
240 <59>, /* TX interrupt */
241 <60>; /* RX interrupt */
242 interrupt-names = "common", "tx", "rx";
243 interrupt-parent = <&intc>;
244 ti,buffer-size = <128>;
245 ti,hwmods = "mcbsp1";
248 mcbsp2: mcbsp@49022000 {
249 compatible = "ti,omap3-mcbsp";
250 reg = <0x49022000 0xff>,
252 reg-names = "mpu", "sidetone";
253 interrupts = <17>, /* OCP compliant interrupt */
254 <62>, /* TX interrupt */
255 <63>, /* RX interrupt */
257 interrupt-names = "common", "tx", "rx", "sidetone";
258 interrupt-parent = <&intc>;
259 ti,buffer-size = <1280>;
260 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
263 mcbsp3: mcbsp@49024000 {
264 compatible = "ti,omap3-mcbsp";
265 reg = <0x49024000 0xff>,
267 reg-names = "mpu", "sidetone";
268 interrupts = <22>, /* OCP compliant interrupt */
269 <89>, /* TX interrupt */
270 <90>, /* RX interrupt */
272 interrupt-names = "common", "tx", "rx", "sidetone";
273 interrupt-parent = <&intc>;
274 ti,buffer-size = <128>;
275 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
278 mcbsp4: mcbsp@49026000 {
279 compatible = "ti,omap3-mcbsp";
280 reg = <0x49026000 0xff>;
282 interrupts = <23>, /* OCP compliant interrupt */
283 <54>, /* TX interrupt */
284 <55>; /* RX interrupt */
285 interrupt-names = "common", "tx", "rx";
286 interrupt-parent = <&intc>;
287 ti,buffer-size = <128>;
288 ti,hwmods = "mcbsp4";
291 mcbsp5: mcbsp@48096000 {
292 compatible = "ti,omap3-mcbsp";
293 reg = <0x48096000 0xff>;
295 interrupts = <27>, /* OCP compliant interrupt */
296 <81>, /* TX interrupt */
297 <82>; /* RX interrupt */
298 interrupt-names = "common", "tx", "rx";
299 interrupt-parent = <&intc>;
300 ti,buffer-size = <128>;
301 ti,hwmods = "mcbsp5";