arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap3430", "ti,omap3";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a8";
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38
  39                         clocks = <&dpll1_ck>;
  40                         clock-names = "cpu";
  41
  42                         clock-latency = <300000>; /* From omap-cpufreq driver */
  43                 };
  44         };
  45
  46         pmu {
  47                 compatible = "arm,cortex-a8-pmu";
  48                 reg = <0x54000000 0x800000>;
  49                 interrupts = <3>;
  50                 ti,hwmods = "debugss";
  51         };
  52
  53         /*
  54          * The soc node represents the soc top level view. It is used for IPs
  55          * that are not memory mapped in the MPU view or for the MPU itself.
  56          */
  57         soc {
  58                 compatible = "ti,omap-infra";
  59                 mpu {
  60                         compatible = "ti,omap3-mpu";
  61                         ti,hwmods = "mpu";
  62                 };
  63
  64                 iva: iva {
  65                         compatible = "ti,iva2.2";
  66                         ti,hwmods = "iva";
  67
  68                         dsp {
  69                                 compatible = "ti,omap3-c64";
  70                         };
  71                 };
  72         };
  73
  74         /*
  75          * XXX: Use a flat representation of the OMAP3 interconnect.
  76          * The real OMAP interconnect network is quite complex.
  77          * Since it will not bring real advantage to represent that in DT for
  78          * the moment, just use a fake OCP bus entry to represent the whole bus
  79          * hierarchy.
  80          */
  81         ocp {
  82                 compatible = "simple-bus";
  83                 reg = <0x68000000 0x10000>;
  84                 interrupts = <9 10>;
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 ti,hwmods = "l3_main";
  89
  90                 aes: aes@480c5000 {
  91                         compatible = "ti,omap3-aes";
  92                         ti,hwmods = "aes";
  93                         reg = <0x480c5000 0x50>;
  94                         interrupts = <0>;
  95                 };
  96
  97                 prm: prm@48306000 {
  98                         compatible = "ti,omap3-prm";
  99                         reg = <0x48306000 0x4000>;
 100
 101                         prm_clocks: clocks {
 102                                 #address-cells = <1>;
 103                                 #size-cells = <0>;
 104                         };
 105
 106                         prm_clockdomains: clockdomains {
 107                         };
 108                 };
 109
 110                 cm: cm@48004000 {
 111                         compatible = "ti,omap3-cm";
 112                         reg = <0x48004000 0x4000>;
 113
 114                         cm_clocks: clocks {
 115                                 #address-cells = <1>;
 116                                 #size-cells = <0>;
 117                         };
 118
 119                         cm_clockdomains: clockdomains {
 120                         };
 121                 };
 122
 123                 scrm: scrm@48002000 {
 124                         compatible = "ti,omap3-scrm";
 125                         reg = <0x48002000 0x2000>;
 126
 127                         scrm_clocks: clocks {
 128                                 #address-cells = <1>;
 129                                 #size-cells = <0>;
 130                         };
 131
 132                         scrm_clockdomains: clockdomains {
 133                         };
 134                 };
 135
 136                 counter32k: counter@48320000 {
 137                         compatible = "ti,omap-counter32k";
 138                         reg = <0x48320000 0x20>;
 139                         ti,hwmods = "counter_32k";
 140                 };
 141
 142                 intc: interrupt-controller@48200000 {
 143                         compatible = "ti,omap2-intc";
 144                         interrupt-controller;
 145                         #interrupt-cells = <1>;
 146                         ti,intc-size = <96>;
 147                         reg = <0x48200000 0x1000>;
 148                 };
 149
 150                 sdma: dma-controller@48056000 {
 151                         compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 152                         reg = <0x48056000 0x1000>;
 153                         interrupts = <12>,
 154                                      <13>,
 155                                      <14>,
 156                                      <15>;
 157                         #dma-cells = <1>;
 158                         #dma-channels = <32>;
 159                         #dma-requests = <96>;
 160                 };
 161
 162                 omap3_pmx_core: pinmux@48002030 {
 163                         compatible = "ti,omap3-padconf", "pinctrl-single";
 164                         reg = <0x48002030 0x0238>;
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         #interrupt-cells = <1>;
 168                         interrupt-controller;
 169                         pinctrl-single,register-width = <16>;
 170                         pinctrl-single,function-mask = <0xff1f>;
 171                 };
 172
 173                 omap3_pmx_wkup: pinmux@48002a00 {
 174                         compatible = "ti,omap3-padconf", "pinctrl-single";
 175                         reg = <0x48002a00 0x5c>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         #interrupt-cells = <1>;
 179                         interrupt-controller;
 180                         pinctrl-single,register-width = <16>;
 181                         pinctrl-single,function-mask = <0xff1f>;
 182                 };
 183
 184                 omap3_scm_general: tisyscon@48002270 {
 185                         compatible = "syscon";
 186                         reg = <0x48002270 0x2f0>;
 187                 };
 188
 189                 pbias_regulator: pbias_regulator {
 190                         compatible = "ti,pbias-omap";
 191                         reg = <0x2b0 0x4>;
 192                         syscon = <&omap3_scm_general>;
 193                         pbias_mmc_reg: pbias_mmc_omap2430 {
 194                                 regulator-name = "pbias_mmc_omap2430";
 195                                 regulator-min-microvolt = <1800000>;
 196                                 regulator-max-microvolt = <3000000>;
 197                         };
 198                 };
 199
 200                 gpio1: gpio@48310000 {
 201                         compatible = "ti,omap3-gpio";
 202                         reg = <0x48310000 0x200>;
 203                         interrupts = <29>;
 204                         ti,hwmods = "gpio1";
 205                         ti,gpio-always-on;
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208                         interrupt-controller;
 209                         #interrupt-cells = <2>;
 210                 };
 211
 212                 gpio2: gpio@49050000 {
 213                         compatible = "ti,omap3-gpio";
 214                         reg = <0x49050000 0x200>;
 215                         interrupts = <30>;
 216                         ti,hwmods = "gpio2";
 217                         gpio-controller;
 218                         #gpio-cells = <2>;
 219                         interrupt-controller;
 220                         #interrupt-cells = <2>;
 221                 };
 222
 223                 gpio3: gpio@49052000 {
 224                         compatible = "ti,omap3-gpio";
 225                         reg = <0x49052000 0x200>;
 226                         interrupts = <31>;
 227                         ti,hwmods = "gpio3";
 228                         gpio-controller;
 229                         #gpio-cells = <2>;
 230                         interrupt-controller;
 231                         #interrupt-cells = <2>;
 232                 };
 233
 234                 gpio4: gpio@49054000 {
 235                         compatible = "ti,omap3-gpio";
 236                         reg = <0x49054000 0x200>;
 237                         interrupts = <32>;
 238                         ti,hwmods = "gpio4";
 239                         gpio-controller;
 240                         #gpio-cells = <2>;
 241                         interrupt-controller;
 242                         #interrupt-cells = <2>;
 243                 };
 244
 245                 gpio5: gpio@49056000 {
 246                         compatible = "ti,omap3-gpio";
 247                         reg = <0x49056000 0x200>;
 248                         interrupts = <33>;
 249                         ti,hwmods = "gpio5";
 250                         gpio-controller;
 251                         #gpio-cells = <2>;
 252                         interrupt-controller;
 253                         #interrupt-cells = <2>;
 254                 };
 255
 256                 gpio6: gpio@49058000 {
 257                         compatible = "ti,omap3-gpio";
 258                         reg = <0x49058000 0x200>;
 259                         interrupts = <34>;
 260                         ti,hwmods = "gpio6";
 261                         gpio-controller;
 262                         #gpio-cells = <2>;
 263                         interrupt-controller;
 264                         #interrupt-cells = <2>;
 265                 };
 266
 267                 uart1: serial@4806a000 {
 268                         compatible = "ti,omap3-uart";
 269                         reg = <0x4806a000 0x2000>;
 270                         interrupts-extended = <&intc 72>;
 271                         dmas = <&sdma 49 &sdma 50>;
 272                         dma-names = "tx", "rx";
 273                         ti,hwmods = "uart1";
 274                         clock-frequency = <48000000>;
 275                 };
 276
 277                 uart2: serial@4806c000 {
 278                         compatible = "ti,omap3-uart";
 279                         reg = <0x4806c000 0x400>;
 280                         interrupts-extended = <&intc 73>;
 281                         dmas = <&sdma 51 &sdma 52>;
 282                         dma-names = "tx", "rx";
 283                         ti,hwmods = "uart2";
 284                         clock-frequency = <48000000>;
 285                 };
 286
 287                 uart3: serial@49020000 {
 288                         compatible = "ti,omap3-uart";
 289                         reg = <0x49020000 0x400>;
 290                         interrupts-extended = <&intc 74>;
 291                         dmas = <&sdma 53 &sdma 54>;
 292                         dma-names = "tx", "rx";
 293                         ti,hwmods = "uart3";
 294                         clock-frequency = <48000000>;
 295                 };
 296
 297                 i2c1: i2c@48070000 {
 298                         compatible = "ti,omap3-i2c";
 299                         reg = <0x48070000 0x80>;
 300                         interrupts = <56>;
 301                         dmas = <&sdma 27 &sdma 28>;
 302                         dma-names = "tx", "rx";
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         ti,hwmods = "i2c1";
 306                 };
 307
 308                 i2c2: i2c@48072000 {
 309                         compatible = "ti,omap3-i2c";
 310                         reg = <0x48072000 0x80>;
 311                         interrupts = <57>;
 312                         dmas = <&sdma 29 &sdma 30>;
 313                         dma-names = "tx", "rx";
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                         ti,hwmods = "i2c2";
 317                 };
 318
 319                 i2c3: i2c@48060000 {
 320                         compatible = "ti,omap3-i2c";
 321                         reg = <0x48060000 0x80>;
 322                         interrupts = <61>;
 323                         dmas = <&sdma 25 &sdma 26>;
 324                         dma-names = "tx", "rx";
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         ti,hwmods = "i2c3";
 328                 };
 329
 330                 mailbox: mailbox@48094000 {
 331                         compatible = "ti,omap3-mailbox";
 332                         ti,hwmods = "mailbox";
 333                         reg = <0x48094000 0x200>;
 334                         interrupts = <26>;
 335                         ti,mbox-num-users = <2>;
 336                         ti,mbox-num-fifos = <2>;
 337                 };
 338
 339                 mcspi1: spi@48098000 {
 340                         compatible = "ti,omap2-mcspi";
 341                         reg = <0x48098000 0x100>;
 342                         interrupts = <65>;
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         ti,hwmods = "mcspi1";
 346                         ti,spi-num-cs = <4>;
 347                         dmas = <&sdma 35>,
 348                                <&sdma 36>,
 349                                <&sdma 37>,
 350                                <&sdma 38>,
 351                                <&sdma 39>,
 352                                <&sdma 40>,
 353                                <&sdma 41>,
 354                                <&sdma 42>;
 355                         dma-names = "tx0", "rx0", "tx1", "rx1",
 356                                     "tx2", "rx2", "tx3", "rx3";
 357                 };
 358
 359                 mcspi2: spi@4809a000 {
 360                         compatible = "ti,omap2-mcspi";
 361                         reg = <0x4809a000 0x100>;
 362                         interrupts = <66>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         ti,hwmods = "mcspi2";
 366                         ti,spi-num-cs = <2>;
 367                         dmas = <&sdma 43>,
 368                                <&sdma 44>,
 369                                <&sdma 45>,
 370                                <&sdma 46>;
 371                         dma-names = "tx0", "rx0", "tx1", "rx1";
 372                 };
 373
 374                 mcspi3: spi@480b8000 {
 375                         compatible = "ti,omap2-mcspi";
 376                         reg = <0x480b8000 0x100>;
 377                         interrupts = <91>;
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         ti,hwmods = "mcspi3";
 381                         ti,spi-num-cs = <2>;
 382                         dmas = <&sdma 15>,
 383                                <&sdma 16>,
 384                                <&sdma 23>,
 385                                <&sdma 24>;
 386                         dma-names = "tx0", "rx0", "tx1", "rx1";
 387                 };
 388
 389                 mcspi4: spi@480ba000 {
 390                         compatible = "ti,omap2-mcspi";
 391                         reg = <0x480ba000 0x100>;
 392                         interrupts = <48>;
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         ti,hwmods = "mcspi4";
 396                         ti,spi-num-cs = <1>;
 397                         dmas = <&sdma 70>, <&sdma 71>;
 398                         dma-names = "tx0", "rx0";
 399                 };
 400
 401                 hdqw1w: 1w@480b2000 {
 402                         compatible = "ti,omap3-1w";
 403                         reg = <0x480b2000 0x1000>;
 404                         interrupts = <58>;
 405                         ti,hwmods = "hdq1w";
 406                 };
 407
 408                 mmc1: mmc@4809c000 {
 409                         compatible = "ti,omap3-hsmmc";
 410                         reg = <0x4809c000 0x200>;
 411                         interrupts = <83>;
 412                         ti,hwmods = "mmc1";
 413                         ti,dual-volt;
 414                         dmas = <&sdma 61>, <&sdma 62>;
 415                         dma-names = "tx", "rx";
 416                         pbias-supply = <&pbias_mmc_reg>;
 417                 };
 418
 419                 mmc2: mmc@480b4000 {
 420                         compatible = "ti,omap3-hsmmc";
 421                         reg = <0x480b4000 0x200>;
 422                         interrupts = <86>;
 423                         ti,hwmods = "mmc2";
 424                         dmas = <&sdma 47>, <&sdma 48>;
 425                         dma-names = "tx", "rx";
 426                 };
 427
 428                 mmc3: mmc@480ad000 {
 429                         compatible = "ti,omap3-hsmmc";
 430                         reg = <0x480ad000 0x200>;
 431                         interrupts = <94>;
 432                         ti,hwmods = "mmc3";
 433                         dmas = <&sdma 77>, <&sdma 78>;
 434                         dma-names = "tx", "rx";
 435                 };
 436
 437                 mmu_isp: mmu@480bd400 {
 438                         compatible = "ti,omap2-iommu";
 439                         reg = <0x480bd400 0x80>;
 440                         interrupts = <24>;
 441                         ti,hwmods = "mmu_isp";
 442                         ti,#tlb-entries = <8>;
 443                 };
 444
 445                 mmu_iva: mmu@5d000000 {
 446                         compatible = "ti,omap2-iommu";
 447                         reg = <0x5d000000 0x80>;
 448                         interrupts = <28>;
 449                         ti,hwmods = "mmu_iva";
 450                         status = "disabled";
 451                 };
 452
 453                 wdt2: wdt@48314000 {
 454                         compatible = "ti,omap3-wdt";
 455                         reg = <0x48314000 0x80>;
 456                         ti,hwmods = "wd_timer2";
 457                 };
 458
 459                 mcbsp1: mcbsp@48074000 {
 460                         compatible = "ti,omap3-mcbsp";
 461                         reg = <0x48074000 0xff>;
 462                         reg-names = "mpu";
 463                         interrupts = <16>, /* OCP compliant interrupt */
 464                                      <59>, /* TX interrupt */
 465                                      <60>; /* RX interrupt */
 466                         interrupt-names = "common", "tx", "rx";
 467                         ti,buffer-size = <128>;
 468                         ti,hwmods = "mcbsp1";
 469                         dmas = <&sdma 31>,
 470                                <&sdma 32>;
 471                         dma-names = "tx", "rx";
 472                         status = "disabled";
 473                 };
 474
 475                 mcbsp2: mcbsp@49022000 {
 476                         compatible = "ti,omap3-mcbsp";
 477                         reg = <0x49022000 0xff>,
 478                               <0x49028000 0xff>;
 479                         reg-names = "mpu", "sidetone";
 480                         interrupts = <17>, /* OCP compliant interrupt */
 481                                      <62>, /* TX interrupt */
 482                                      <63>, /* RX interrupt */
 483                                      <4>;  /* Sidetone */
 484                         interrupt-names = "common", "tx", "rx", "sidetone";
 485                         ti,buffer-size = <1280>;
 486                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 487                         dmas = <&sdma 33>,
 488                                <&sdma 34>;
 489                         dma-names = "tx", "rx";
 490                         status = "disabled";
 491                 };
 492
 493                 mcbsp3: mcbsp@49024000 {
 494                         compatible = "ti,omap3-mcbsp";
 495                         reg = <0x49024000 0xff>,
 496                               <0x4902a000 0xff>;
 497                         reg-names = "mpu", "sidetone";
 498                         interrupts = <22>, /* OCP compliant interrupt */
 499                                      <89>, /* TX interrupt */
 500                                      <90>, /* RX interrupt */
 501                                      <5>;  /* Sidetone */
 502                         interrupt-names = "common", "tx", "rx", "sidetone";
 503                         ti,buffer-size = <128>;
 504                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 505                         dmas = <&sdma 17>,
 506                                <&sdma 18>;
 507                         dma-names = "tx", "rx";
 508                         status = "disabled";
 509                 };
 510
 511                 mcbsp4: mcbsp@49026000 {
 512                         compatible = "ti,omap3-mcbsp";
 513                         reg = <0x49026000 0xff>;
 514                         reg-names = "mpu";
 515                         interrupts = <23>, /* OCP compliant interrupt */
 516                                      <54>, /* TX interrupt */
 517                                      <55>; /* RX interrupt */
 518                         interrupt-names = "common", "tx", "rx";
 519                         ti,buffer-size = <128>;
 520                         ti,hwmods = "mcbsp4";
 521                         dmas = <&sdma 19>,
 522                                <&sdma 20>;
 523                         dma-names = "tx", "rx";
 524                         status = "disabled";
 525                 };
 526
 527                 mcbsp5: mcbsp@48096000 {
 528                         compatible = "ti,omap3-mcbsp";
 529                         reg = <0x48096000 0xff>;
 530                         reg-names = "mpu";
 531                         interrupts = <27>, /* OCP compliant interrupt */
 532                                      <81>, /* TX interrupt */
 533                                      <82>; /* RX interrupt */
 534                         interrupt-names = "common", "tx", "rx";
 535                         ti,buffer-size = <128>;
 536                         ti,hwmods = "mcbsp5";
 537                         dmas = <&sdma 21>,
 538                                <&sdma 22>;
 539                         dma-names = "tx", "rx";
 540                         status = "disabled";
 541                 };
 542
 543                 sham: sham@480c3000 {
 544                         compatible = "ti,omap3-sham";
 545                         ti,hwmods = "sham";
 546                         reg = <0x480c3000 0x64>;
 547                         interrupts = <49>;
 548                 };
 549
 550                 smartreflex_core: smartreflex@480cb000 {
 551                         compatible = "ti,omap3-smartreflex-core";
 552                         ti,hwmods = "smartreflex_core";
 553                         reg = <0x480cb000 0x400>;
 554                         interrupts = <19>;
 555                 };
 556
 557                 smartreflex_mpu_iva: smartreflex@480c9000 {
 558                         compatible = "ti,omap3-smartreflex-iva";
 559                         ti,hwmods = "smartreflex_mpu_iva";
 560                         reg = <0x480c9000 0x400>;
 561                         interrupts = <18>;
 562                 };
 563
 564                 timer1: timer@48318000 {
 565                         compatible = "ti,omap3430-timer";
 566                         reg = <0x48318000 0x400>;
 567                         interrupts = <37>;
 568                         ti,hwmods = "timer1";
 569                         ti,timer-alwon;
 570                 };
 571
 572                 timer2: timer@49032000 {
 573                         compatible = "ti,omap3430-timer";
 574                         reg = <0x49032000 0x400>;
 575                         interrupts = <38>;
 576                         ti,hwmods = "timer2";
 577                 };
 578
 579                 timer3: timer@49034000 {
 580                         compatible = "ti,omap3430-timer";
 581                         reg = <0x49034000 0x400>;
 582                         interrupts = <39>;
 583                         ti,hwmods = "timer3";
 584                 };
 585
 586                 timer4: timer@49036000 {
 587                         compatible = "ti,omap3430-timer";
 588                         reg = <0x49036000 0x400>;
 589                         interrupts = <40>;
 590                         ti,hwmods = "timer4";
 591                 };
 592
 593                 timer5: timer@49038000 {
 594                         compatible = "ti,omap3430-timer";
 595                         reg = <0x49038000 0x400>;
 596                         interrupts = <41>;
 597                         ti,hwmods = "timer5";
 598                         ti,timer-dsp;
 599                 };
 600
 601                 timer6: timer@4903a000 {
 602                         compatible = "ti,omap3430-timer";
 603                         reg = <0x4903a000 0x400>;
 604                         interrupts = <42>;
 605                         ti,hwmods = "timer6";
 606                         ti,timer-dsp;
 607                 };
 608
 609                 timer7: timer@4903c000 {
 610                         compatible = "ti,omap3430-timer";
 611                         reg = <0x4903c000 0x400>;
 612                         interrupts = <43>;
 613                         ti,hwmods = "timer7";
 614                         ti,timer-dsp;
 615                 };
 616
 617                 timer8: timer@4903e000 {
 618                         compatible = "ti,omap3430-timer";
 619                         reg = <0x4903e000 0x400>;
 620                         interrupts = <44>;
 621                         ti,hwmods = "timer8";
 622                         ti,timer-pwm;
 623                         ti,timer-dsp;
 624                 };
 625
 626                 timer9: timer@49040000 {
 627                         compatible = "ti,omap3430-timer";
 628                         reg = <0x49040000 0x400>;
 629                         interrupts = <45>;
 630                         ti,hwmods = "timer9";
 631                         ti,timer-pwm;
 632                 };
 633
 634                 timer10: timer@48086000 {
 635                         compatible = "ti,omap3430-timer";
 636                         reg = <0x48086000 0x400>;
 637                         interrupts = <46>;
 638                         ti,hwmods = "timer10";
 639                         ti,timer-pwm;
 640                 };
 641
 642                 timer11: timer@48088000 {
 643                         compatible = "ti,omap3430-timer";
 644                         reg = <0x48088000 0x400>;
 645                         interrupts = <47>;
 646                         ti,hwmods = "timer11";
 647                         ti,timer-pwm;
 648                 };
 649
 650                 timer12: timer@48304000 {
 651                         compatible = "ti,omap3430-timer";
 652                         reg = <0x48304000 0x400>;
 653                         interrupts = <95>;
 654                         ti,hwmods = "timer12";
 655                         ti,timer-alwon;
 656                         ti,timer-secure;
 657                 };
 658
 659                 usbhstll: usbhstll@48062000 {
 660                         compatible = "ti,usbhs-tll";
 661                         reg = <0x48062000 0x1000>;
 662                         interrupts = <78>;
 663                         ti,hwmods = "usb_tll_hs";
 664                 };
 665
 666                 usbhshost: usbhshost@48064000 {
 667                         compatible = "ti,usbhs-host";
 668                         reg = <0x48064000 0x400>;
 669                         ti,hwmods = "usb_host_hs";
 670                         #address-cells = <1>;
 671                         #size-cells = <1>;
 672                         ranges;
 673
 674                         usbhsohci: ohci@48064400 {
 675                                 compatible = "ti,ohci-omap3";
 676                                 reg = <0x48064400 0x400>;
 677                                 interrupt-parent = <&intc>;
 678                                 interrupts = <76>;
 679                         };
 680
 681                         usbhsehci: ehci@48064800 {
 682                                 compatible = "ti,ehci-omap";
 683                                 reg = <0x48064800 0x400>;
 684                                 interrupt-parent = <&intc>;
 685                                 interrupts = <77>;
 686                         };
 687                 };
 688
 689                 gpmc: gpmc@6e000000 {
 690                         compatible = "ti,omap3430-gpmc";
 691                         ti,hwmods = "gpmc";
 692                         reg = <0x6e000000 0x02d0>;
 693                         interrupts = <20>;
 694                         gpmc,num-cs = <8>;
 695                         gpmc,num-waitpins = <4>;
 696                         #address-cells = <2>;
 697                         #size-cells = <1>;
 698                 };
 699
 700                 usb_otg_hs: usb_otg_hs@480ab000 {
 701                         compatible = "ti,omap3-musb";
 702                         reg = <0x480ab000 0x1000>;
 703                         interrupts = <92>, <93>;
 704                         interrupt-names = "mc", "dma";
 705                         ti,hwmods = "usb_otg_hs";
 706                         multipoint = <1>;
 707                         num-eps = <16>;
 708                         ram-bits = <12>;
 709                 };
 710
 711                 dss: dss@48050000 {
 712                         compatible = "ti,omap3-dss";
 713                         reg = <0x48050000 0x200>;
 714                         status = "disabled";
 715                         ti,hwmods = "dss_core";
 716                         clocks = <&dss1_alwon_fck>;
 717                         clock-names = "fck";
 718                         #address-cells = <1>;
 719                         #size-cells = <1>;
 720                         ranges;
 721
 722                         dispc@48050400 {
 723                                 compatible = "ti,omap3-dispc";
 724                                 reg = <0x48050400 0x400>;
 725                                 interrupts = <25>;
 726                                 ti,hwmods = "dss_dispc";
 727                                 clocks = <&dss1_alwon_fck>;
 728                                 clock-names = "fck";
 729                         };
 730
 731                         dsi: encoder@4804fc00 {
 732                                 compatible = "ti,omap3-dsi";
 733                                 reg = <0x4804fc00 0x200>,
 734                                       <0x4804fe00 0x40>,
 735                                       <0x4804ff00 0x20>;
 736                                 reg-names = "proto", "phy", "pll";
 737                                 interrupts = <25>;
 738                                 status = "disabled";
 739                                 ti,hwmods = "dss_dsi1";
 740                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 741                                 clock-names = "fck", "sys_clk";
 742                         };
 743
 744                         rfbi: encoder@48050800 {
 745                                 compatible = "ti,omap3-rfbi";
 746                                 reg = <0x48050800 0x100>;
 747                                 status = "disabled";
 748                                 ti,hwmods = "dss_rfbi";
 749                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 750                                 clock-names = "fck", "ick";
 751                         };
 752
 753                         venc: encoder@48050c00 {
 754                                 compatible = "ti,omap3-venc";
 755                                 reg = <0x48050c00 0x100>;
 756                                 status = "disabled";
 757                                 ti,hwmods = "dss_venc";
 758                                 clocks = <&dss_tv_fck>;
 759                                 clock-names = "fck";
 760                         };
 761                 };
 762
 763                 ssi: ssi-controller@48058000 {
 764                         compatible = "ti,omap3-ssi";
 765                         ti,hwmods = "ssi";
 766
 767                         status = "disabled";
 768
 769                         reg = <0x48058000 0x1000>,
 770                               <0x48059000 0x1000>;
 771                         reg-names = "sys",
 772                                     "gdd";
 773
 774                         interrupts = <71>;
 775                         interrupt-names = "gdd_mpu";
 776
 777                         #address-cells = <1>;
 778                         #size-cells = <1>;
 779                         ranges;
 780
 781                         ssi_port1: ssi-port@4805a000 {
 782                                 compatible = "ti,omap3-ssi-port";
 783
 784                                 reg = <0x4805a000 0x800>,
 785                                       <0x4805a800 0x800>;
 786                                 reg-names = "tx",
 787                                             "rx";
 788
 789                                 interrupt-parent = <&intc>;
 790                                 interrupts = <67>,
 791                                              <68>;
 792                         };
 793
 794                         ssi_port2: ssi-port@4805b000 {
 795                                 compatible = "ti,omap3-ssi-port";
 796
 797                                 reg = <0x4805b000 0x800>,
 798                                       <0x4805b800 0x800>;
 799                                 reg-names = "tx",
 800                                             "rx";
 801
 802                                 interrupt-parent = <&intc>;
 803                                 interrupts = <69>,
 804                                              <70>;
 805                         };
 806                 };
 807         };
 808 };
 809
 810 /include/ "omap3xxx-clocks.dtsi"