2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
15 #include "skeleton.dtsi"
18 compatible = "ti,omap3430", "ti,omap3";
19 interrupt-parent = <&intc>;
35 compatible = "arm,cortex-a8";
42 clock-latency = <300000>; /* From omap-cpufreq driver */
47 compatible = "arm,cortex-a8-pmu";
48 reg = <0x54000000 0x800000>;
50 ti,hwmods = "debugss";
54 * The soc node represents the soc top level view. It is used for IPs
55 * that are not memory mapped in the MPU view or for the MPU itself.
58 compatible = "ti,omap-infra";
60 compatible = "ti,omap3-mpu";
65 compatible = "ti,iva2.2";
69 compatible = "ti,omap3-c64";
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
77 * Since it will not bring real advantage to represent that in DT for
78 * the moment, just use a fake OCP bus entry to represent the whole bus
82 compatible = "ti,omap3-l3-smx", "simple-bus";
83 reg = <0x68000000 0x10000>;
88 ti,hwmods = "l3_main";
91 compatible = "ti,omap3-aes";
93 reg = <0x480c5000 0x50>;
95 dmas = <&sdma 65 &sdma 66>;
96 dma-names = "tx", "rx";
100 compatible = "ti,omap3-prm";
101 reg = <0x48306000 0x4000>;
105 #address-cells = <1>;
109 prm_clockdomains: clockdomains {
114 compatible = "ti,omap3-cm";
115 reg = <0x48004000 0x4000>;
118 #address-cells = <1>;
122 cm_clockdomains: clockdomains {
126 scrm: scrm@48002000 {
127 compatible = "ti,omap3-scrm";
128 reg = <0x48002000 0x2000>;
130 scrm_clocks: clocks {
131 #address-cells = <1>;
135 scrm_clockdomains: clockdomains {
139 counter32k: counter@48320000 {
140 compatible = "ti,omap-counter32k";
141 reg = <0x48320000 0x20>;
142 ti,hwmods = "counter_32k";
145 intc: interrupt-controller@48200000 {
146 compatible = "ti,omap3-intc";
147 interrupt-controller;
148 #interrupt-cells = <1>;
149 reg = <0x48200000 0x1000>;
152 sdma: dma-controller@48056000 {
153 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
154 reg = <0x48056000 0x1000>;
164 omap3_pmx_core: pinmux@48002030 {
165 compatible = "ti,omap3-padconf", "pinctrl-single";
166 reg = <0x48002030 0x0238>;
167 #address-cells = <1>;
169 #interrupt-cells = <1>;
170 interrupt-controller;
171 pinctrl-single,register-width = <16>;
172 pinctrl-single,function-mask = <0xff1f>;
175 omap3_pmx_wkup: pinmux@48002a00 {
176 compatible = "ti,omap3-padconf", "pinctrl-single";
177 reg = <0x48002a00 0x5c>;
178 #address-cells = <1>;
180 #interrupt-cells = <1>;
181 interrupt-controller;
182 pinctrl-single,register-width = <16>;
183 pinctrl-single,function-mask = <0xff1f>;
186 omap3_scm_general: tisyscon@48002270 {
187 compatible = "syscon";
188 reg = <0x48002270 0x2f0>;
191 pbias_regulator: pbias_regulator {
192 compatible = "ti,pbias-omap";
194 syscon = <&omap3_scm_general>;
195 pbias_mmc_reg: pbias_mmc_omap2430 {
196 regulator-name = "pbias_mmc_omap2430";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <3000000>;
202 gpio1: gpio@48310000 {
203 compatible = "ti,omap3-gpio";
204 reg = <0x48310000 0x200>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
214 gpio2: gpio@49050000 {
215 compatible = "ti,omap3-gpio";
216 reg = <0x49050000 0x200>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
225 gpio3: gpio@49052000 {
226 compatible = "ti,omap3-gpio";
227 reg = <0x49052000 0x200>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
236 gpio4: gpio@49054000 {
237 compatible = "ti,omap3-gpio";
238 reg = <0x49054000 0x200>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
247 gpio5: gpio@49056000 {
248 compatible = "ti,omap3-gpio";
249 reg = <0x49056000 0x200>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
258 gpio6: gpio@49058000 {
259 compatible = "ti,omap3-gpio";
260 reg = <0x49058000 0x200>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
269 uart1: serial@4806a000 {
270 compatible = "ti,omap3-uart";
271 reg = <0x4806a000 0x2000>;
272 interrupts-extended = <&intc 72>;
273 dmas = <&sdma 49 &sdma 50>;
274 dma-names = "tx", "rx";
276 clock-frequency = <48000000>;
279 uart2: serial@4806c000 {
280 compatible = "ti,omap3-uart";
281 reg = <0x4806c000 0x400>;
282 interrupts-extended = <&intc 73>;
283 dmas = <&sdma 51 &sdma 52>;
284 dma-names = "tx", "rx";
286 clock-frequency = <48000000>;
289 uart3: serial@49020000 {
290 compatible = "ti,omap3-uart";
291 reg = <0x49020000 0x400>;
292 interrupts-extended = <&intc 74>;
293 dmas = <&sdma 53 &sdma 54>;
294 dma-names = "tx", "rx";
296 clock-frequency = <48000000>;
300 compatible = "ti,omap3-i2c";
301 reg = <0x48070000 0x80>;
303 dmas = <&sdma 27 &sdma 28>;
304 dma-names = "tx", "rx";
305 #address-cells = <1>;
311 compatible = "ti,omap3-i2c";
312 reg = <0x48072000 0x80>;
314 dmas = <&sdma 29 &sdma 30>;
315 dma-names = "tx", "rx";
316 #address-cells = <1>;
322 compatible = "ti,omap3-i2c";
323 reg = <0x48060000 0x80>;
325 dmas = <&sdma 25 &sdma 26>;
326 dma-names = "tx", "rx";
327 #address-cells = <1>;
332 mailbox: mailbox@48094000 {
333 compatible = "ti,omap3-mailbox";
334 ti,hwmods = "mailbox";
335 reg = <0x48094000 0x200>;
338 ti,mbox-num-users = <2>;
339 ti,mbox-num-fifos = <2>;
341 ti,mbox-tx = <0 0 0>;
342 ti,mbox-rx = <1 0 0>;
346 mcspi1: spi@48098000 {
347 compatible = "ti,omap2-mcspi";
348 reg = <0x48098000 0x100>;
350 #address-cells = <1>;
352 ti,hwmods = "mcspi1";
362 dma-names = "tx0", "rx0", "tx1", "rx1",
363 "tx2", "rx2", "tx3", "rx3";
366 mcspi2: spi@4809a000 {
367 compatible = "ti,omap2-mcspi";
368 reg = <0x4809a000 0x100>;
370 #address-cells = <1>;
372 ti,hwmods = "mcspi2";
378 dma-names = "tx0", "rx0", "tx1", "rx1";
381 mcspi3: spi@480b8000 {
382 compatible = "ti,omap2-mcspi";
383 reg = <0x480b8000 0x100>;
385 #address-cells = <1>;
387 ti,hwmods = "mcspi3";
393 dma-names = "tx0", "rx0", "tx1", "rx1";
396 mcspi4: spi@480ba000 {
397 compatible = "ti,omap2-mcspi";
398 reg = <0x480ba000 0x100>;
400 #address-cells = <1>;
402 ti,hwmods = "mcspi4";
404 dmas = <&sdma 70>, <&sdma 71>;
405 dma-names = "tx0", "rx0";
408 hdqw1w: 1w@480b2000 {
409 compatible = "ti,omap3-1w";
410 reg = <0x480b2000 0x1000>;
416 compatible = "ti,omap3-hsmmc";
417 reg = <0x4809c000 0x200>;
421 dmas = <&sdma 61>, <&sdma 62>;
422 dma-names = "tx", "rx";
423 pbias-supply = <&pbias_mmc_reg>;
427 compatible = "ti,omap3-hsmmc";
428 reg = <0x480b4000 0x200>;
431 dmas = <&sdma 47>, <&sdma 48>;
432 dma-names = "tx", "rx";
436 compatible = "ti,omap3-hsmmc";
437 reg = <0x480ad000 0x200>;
440 dmas = <&sdma 77>, <&sdma 78>;
441 dma-names = "tx", "rx";
444 mmu_isp: mmu@480bd400 {
445 compatible = "ti,omap2-iommu";
446 reg = <0x480bd400 0x80>;
448 ti,hwmods = "mmu_isp";
449 ti,#tlb-entries = <8>;
452 mmu_iva: mmu@5d000000 {
453 compatible = "ti,omap2-iommu";
454 reg = <0x5d000000 0x80>;
456 ti,hwmods = "mmu_iva";
461 compatible = "ti,omap3-wdt";
462 reg = <0x48314000 0x80>;
463 ti,hwmods = "wd_timer2";
466 mcbsp1: mcbsp@48074000 {
467 compatible = "ti,omap3-mcbsp";
468 reg = <0x48074000 0xff>;
470 interrupts = <16>, /* OCP compliant interrupt */
471 <59>, /* TX interrupt */
472 <60>; /* RX interrupt */
473 interrupt-names = "common", "tx", "rx";
474 ti,buffer-size = <128>;
475 ti,hwmods = "mcbsp1";
478 dma-names = "tx", "rx";
482 mcbsp2: mcbsp@49022000 {
483 compatible = "ti,omap3-mcbsp";
484 reg = <0x49022000 0xff>,
486 reg-names = "mpu", "sidetone";
487 interrupts = <17>, /* OCP compliant interrupt */
488 <62>, /* TX interrupt */
489 <63>, /* RX interrupt */
491 interrupt-names = "common", "tx", "rx", "sidetone";
492 ti,buffer-size = <1280>;
493 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
496 dma-names = "tx", "rx";
500 mcbsp3: mcbsp@49024000 {
501 compatible = "ti,omap3-mcbsp";
502 reg = <0x49024000 0xff>,
504 reg-names = "mpu", "sidetone";
505 interrupts = <22>, /* OCP compliant interrupt */
506 <89>, /* TX interrupt */
507 <90>, /* RX interrupt */
509 interrupt-names = "common", "tx", "rx", "sidetone";
510 ti,buffer-size = <128>;
511 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
514 dma-names = "tx", "rx";
518 mcbsp4: mcbsp@49026000 {
519 compatible = "ti,omap3-mcbsp";
520 reg = <0x49026000 0xff>;
522 interrupts = <23>, /* OCP compliant interrupt */
523 <54>, /* TX interrupt */
524 <55>; /* RX interrupt */
525 interrupt-names = "common", "tx", "rx";
526 ti,buffer-size = <128>;
527 ti,hwmods = "mcbsp4";
530 dma-names = "tx", "rx";
534 mcbsp5: mcbsp@48096000 {
535 compatible = "ti,omap3-mcbsp";
536 reg = <0x48096000 0xff>;
538 interrupts = <27>, /* OCP compliant interrupt */
539 <81>, /* TX interrupt */
540 <82>; /* RX interrupt */
541 interrupt-names = "common", "tx", "rx";
542 ti,buffer-size = <128>;
543 ti,hwmods = "mcbsp5";
546 dma-names = "tx", "rx";
550 sham: sham@480c3000 {
551 compatible = "ti,omap3-sham";
553 reg = <0x480c3000 0x64>;
559 smartreflex_core: smartreflex@480cb000 {
560 compatible = "ti,omap3-smartreflex-core";
561 ti,hwmods = "smartreflex_core";
562 reg = <0x480cb000 0x400>;
566 smartreflex_mpu_iva: smartreflex@480c9000 {
567 compatible = "ti,omap3-smartreflex-iva";
568 ti,hwmods = "smartreflex_mpu_iva";
569 reg = <0x480c9000 0x400>;
573 timer1: timer@48318000 {
574 compatible = "ti,omap3430-timer";
575 reg = <0x48318000 0x400>;
577 ti,hwmods = "timer1";
581 timer2: timer@49032000 {
582 compatible = "ti,omap3430-timer";
583 reg = <0x49032000 0x400>;
585 ti,hwmods = "timer2";
588 timer3: timer@49034000 {
589 compatible = "ti,omap3430-timer";
590 reg = <0x49034000 0x400>;
592 ti,hwmods = "timer3";
595 timer4: timer@49036000 {
596 compatible = "ti,omap3430-timer";
597 reg = <0x49036000 0x400>;
599 ti,hwmods = "timer4";
602 timer5: timer@49038000 {
603 compatible = "ti,omap3430-timer";
604 reg = <0x49038000 0x400>;
606 ti,hwmods = "timer5";
610 timer6: timer@4903a000 {
611 compatible = "ti,omap3430-timer";
612 reg = <0x4903a000 0x400>;
614 ti,hwmods = "timer6";
618 timer7: timer@4903c000 {
619 compatible = "ti,omap3430-timer";
620 reg = <0x4903c000 0x400>;
622 ti,hwmods = "timer7";
626 timer8: timer@4903e000 {
627 compatible = "ti,omap3430-timer";
628 reg = <0x4903e000 0x400>;
630 ti,hwmods = "timer8";
635 timer9: timer@49040000 {
636 compatible = "ti,omap3430-timer";
637 reg = <0x49040000 0x400>;
639 ti,hwmods = "timer9";
643 timer10: timer@48086000 {
644 compatible = "ti,omap3430-timer";
645 reg = <0x48086000 0x400>;
647 ti,hwmods = "timer10";
651 timer11: timer@48088000 {
652 compatible = "ti,omap3430-timer";
653 reg = <0x48088000 0x400>;
655 ti,hwmods = "timer11";
659 timer12: timer@48304000 {
660 compatible = "ti,omap3430-timer";
661 reg = <0x48304000 0x400>;
663 ti,hwmods = "timer12";
668 usbhstll: usbhstll@48062000 {
669 compatible = "ti,usbhs-tll";
670 reg = <0x48062000 0x1000>;
672 ti,hwmods = "usb_tll_hs";
675 usbhshost: usbhshost@48064000 {
676 compatible = "ti,usbhs-host";
677 reg = <0x48064000 0x400>;
678 ti,hwmods = "usb_host_hs";
679 #address-cells = <1>;
683 usbhsohci: ohci@48064400 {
684 compatible = "ti,ohci-omap3";
685 reg = <0x48064400 0x400>;
686 interrupt-parent = <&intc>;
690 usbhsehci: ehci@48064800 {
691 compatible = "ti,ehci-omap";
692 reg = <0x48064800 0x400>;
693 interrupt-parent = <&intc>;
698 gpmc: gpmc@6e000000 {
699 compatible = "ti,omap3430-gpmc";
701 reg = <0x6e000000 0x02d0>;
704 gpmc,num-waitpins = <4>;
705 #address-cells = <2>;
709 usb_otg_hs: usb_otg_hs@480ab000 {
710 compatible = "ti,omap3-musb";
711 reg = <0x480ab000 0x1000>;
712 interrupts = <92>, <93>;
713 interrupt-names = "mc", "dma";
714 ti,hwmods = "usb_otg_hs";
721 compatible = "ti,omap3-dss";
722 reg = <0x48050000 0x200>;
724 ti,hwmods = "dss_core";
725 clocks = <&dss1_alwon_fck>;
727 #address-cells = <1>;
732 compatible = "ti,omap3-dispc";
733 reg = <0x48050400 0x400>;
735 ti,hwmods = "dss_dispc";
736 clocks = <&dss1_alwon_fck>;
740 dsi: encoder@4804fc00 {
741 compatible = "ti,omap3-dsi";
742 reg = <0x4804fc00 0x200>,
745 reg-names = "proto", "phy", "pll";
748 ti,hwmods = "dss_dsi1";
749 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
750 clock-names = "fck", "sys_clk";
753 rfbi: encoder@48050800 {
754 compatible = "ti,omap3-rfbi";
755 reg = <0x48050800 0x100>;
757 ti,hwmods = "dss_rfbi";
758 clocks = <&dss1_alwon_fck>, <&dss_ick>;
759 clock-names = "fck", "ick";
762 venc: encoder@48050c00 {
763 compatible = "ti,omap3-venc";
764 reg = <0x48050c00 0x100>;
766 ti,hwmods = "dss_venc";
767 clocks = <&dss_tv_fck>;
772 ssi: ssi-controller@48058000 {
773 compatible = "ti,omap3-ssi";
778 reg = <0x48058000 0x1000>,
784 interrupt-names = "gdd_mpu";
786 #address-cells = <1>;
790 ssi_port1: ssi-port@4805a000 {
791 compatible = "ti,omap3-ssi-port";
793 reg = <0x4805a000 0x800>,
798 interrupt-parent = <&intc>;
803 ssi_port2: ssi-port@4805b000 {
804 compatible = "ti,omap3-ssi-port";
806 reg = <0x4805b000 0x800>,
811 interrupt-parent = <&intc>;
819 /include/ "omap3xxx-clocks.dtsi"