arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap3430", "ti,omap3";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a8";
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38
  39                         clocks = <&dpll1_ck>;
  40                         clock-names = "cpu";
  41
  42                         clock-latency = <300000>; /* From omap-cpufreq driver */
  43                 };
  44         };
  45
  46         pmu {
  47                 compatible = "arm,cortex-a8-pmu";
  48                 reg = <0x54000000 0x800000>;
  49                 interrupts = <3>;
  50                 ti,hwmods = "debugss";
  51         };
  52
  53         /*
  54          * The soc node represents the soc top level view. It is used for IPs
  55          * that are not memory mapped in the MPU view or for the MPU itself.
  56          */
  57         soc {
  58                 compatible = "ti,omap-infra";
  59                 mpu {
  60                         compatible = "ti,omap3-mpu";
  61                         ti,hwmods = "mpu";
  62                 };
  63
  64                 iva: iva {
  65                         compatible = "ti,iva2.2";
  66                         ti,hwmods = "iva";
  67
  68                         dsp {
  69                                 compatible = "ti,omap3-c64";
  70                         };
  71                 };
  72         };
  73
  74         /*
  75          * XXX: Use a flat representation of the OMAP3 interconnect.
  76          * The real OMAP interconnect network is quite complex.
  77          * Since it will not bring real advantage to represent that in DT for
  78          * the moment, just use a fake OCP bus entry to represent the whole bus
  79          * hierarchy.
  80          */
  81         ocp {
  82                 compatible = "ti,omap3-l3-smx", "simple-bus";
  83                 reg = <0x68000000 0x10000>;
  84                 interrupts = <9 10>;
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 ti,hwmods = "l3_main";
  89
  90                 l4_core: l4@48000000 {
  91                         compatible = "ti,omap3-l4-core", "simple-bus";
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         ranges = <0 0x48000000 0x1000000>;
  95
  96                         scm: scm@2000 {
  97                                 compatible = "ti,omap3-scm", "simple-bus";
  98                                 reg = <0x2000 0x2000>;
  99                                 #address-cells = <1>;
 100                                 #size-cells = <1>;
 101                                 ranges = <0 0x2000 0x2000>;
 102
 103                                 omap3_pmx_core: pinmux@30 {
 104                                         compatible = "ti,omap3-padconf",
 105                                                      "pinctrl-single";
 106                                         reg = <0x30 0x238>;
 107                                         #address-cells = <1>;
 108                                         #size-cells = <0>;
 109                                         #interrupt-cells = <1>;
 110                                         interrupt-controller;
 111                                         pinctrl-single,register-width = <16>;
 112                                         pinctrl-single,function-mask = <0xff1f>;
 113                                 };
 114
 115                                 scm_conf: scm_conf@270 {
 116                                         compatible = "syscon";
 117                                         reg = <0x270 0x330>;
 118                                         #address-cells = <1>;
 119                                         #size-cells = <1>;
 120
 121                                         scm_clocks: clocks {
 122                                                 #address-cells = <1>;
 123                                                 #size-cells = <0>;
 124                                         };
 125                                 };
 126
 127                                 scm_clockdomains: clockdomains {
 128                                 };
 129
 130                                 omap3_pmx_wkup: pinmux@a00 {
 131                                         compatible = "ti,omap3-padconf",
 132                                                      "pinctrl-single";
 133                                         reg = <0xa00 0x5c>;
 134                                         #address-cells = <1>;
 135                                         #size-cells = <0>;
 136                                         #interrupt-cells = <1>;
 137                                         interrupt-controller;
 138                                         pinctrl-single,register-width = <16>;
 139                                         pinctrl-single,function-mask = <0xff1f>;
 140                                 };
 141                         };
 142                 };
 143
 144                 aes: aes@480c5000 {
 145                         compatible = "ti,omap3-aes";
 146                         ti,hwmods = "aes";
 147                         reg = <0x480c5000 0x50>;
 148                         interrupts = <0>;
 149                 };
 150
 151                 prm: prm@48306000 {
 152                         compatible = "ti,omap3-prm";
 153                         reg = <0x48306000 0x4000>;
 154                         interrupts = <11>;
 155
 156                         prm_clocks: clocks {
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                         };
 160
 161                         prm_clockdomains: clockdomains {
 162                         };
 163                 };
 164
 165                 cm: cm@48004000 {
 166                         compatible = "ti,omap3-cm";
 167                         reg = <0x48004000 0x4000>;
 168
 169                         cm_clocks: clocks {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172                         };
 173
 174                         cm_clockdomains: clockdomains {
 175                         };
 176                 };
 177
 178                 counter32k: counter@48320000 {
 179                         compatible = "ti,omap-counter32k";
 180                         reg = <0x48320000 0x20>;
 181                         ti,hwmods = "counter_32k";
 182                 };
 183
 184                 intc: interrupt-controller@48200000 {
 185                         compatible = "ti,omap3-intc";
 186                         interrupt-controller;
 187                         #interrupt-cells = <1>;
 188                         reg = <0x48200000 0x1000>;
 189                 };
 190
 191                 sdma: dma-controller@48056000 {
 192                         compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 193                         reg = <0x48056000 0x1000>;
 194                         interrupts = <12>,
 195                                      <13>,
 196                                      <14>,
 197                                      <15>;
 198                         #dma-cells = <1>;
 199                         dma-channels = <32>;
 200                         dma-requests = <96>;
 201                 };
 202
 203                 pbias_regulator: pbias_regulator {
 204                         compatible = "ti,pbias-omap";
 205                         reg = <0x2b0 0x4>;
 206                         syscon = <&scm_conf>;
 207                         pbias_mmc_reg: pbias_mmc_omap2430 {
 208                                 regulator-name = "pbias_mmc_omap2430";
 209                                 regulator-min-microvolt = <1800000>;
 210                                 regulator-max-microvolt = <3000000>;
 211                         };
 212                 };
 213
 214                 gpio1: gpio@48310000 {
 215                         compatible = "ti,omap3-gpio";
 216                         reg = <0x48310000 0x200>;
 217                         interrupts = <29>;
 218                         ti,hwmods = "gpio1";
 219                         ti,gpio-always-on;
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222                         interrupt-controller;
 223                         #interrupt-cells = <2>;
 224                 };
 225
 226                 gpio2: gpio@49050000 {
 227                         compatible = "ti,omap3-gpio";
 228                         reg = <0x49050000 0x200>;
 229                         interrupts = <30>;
 230                         ti,hwmods = "gpio2";
 231                         gpio-controller;
 232                         #gpio-cells = <2>;
 233                         interrupt-controller;
 234                         #interrupt-cells = <2>;
 235                 };
 236
 237                 gpio3: gpio@49052000 {
 238                         compatible = "ti,omap3-gpio";
 239                         reg = <0x49052000 0x200>;
 240                         interrupts = <31>;
 241                         ti,hwmods = "gpio3";
 242                         gpio-controller;
 243                         #gpio-cells = <2>;
 244                         interrupt-controller;
 245                         #interrupt-cells = <2>;
 246                 };
 247
 248                 gpio4: gpio@49054000 {
 249                         compatible = "ti,omap3-gpio";
 250                         reg = <0x49054000 0x200>;
 251                         interrupts = <32>;
 252                         ti,hwmods = "gpio4";
 253                         gpio-controller;
 254                         #gpio-cells = <2>;
 255                         interrupt-controller;
 256                         #interrupt-cells = <2>;
 257                 };
 258
 259                 gpio5: gpio@49056000 {
 260                         compatible = "ti,omap3-gpio";
 261                         reg = <0x49056000 0x200>;
 262                         interrupts = <33>;
 263                         ti,hwmods = "gpio5";
 264                         gpio-controller;
 265                         #gpio-cells = <2>;
 266                         interrupt-controller;
 267                         #interrupt-cells = <2>;
 268                 };
 269
 270                 gpio6: gpio@49058000 {
 271                         compatible = "ti,omap3-gpio";
 272                         reg = <0x49058000 0x200>;
 273                         interrupts = <34>;
 274                         ti,hwmods = "gpio6";
 275                         gpio-controller;
 276                         #gpio-cells = <2>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                 };
 280
 281                 uart1: serial@4806a000 {
 282                         compatible = "ti,omap3-uart";
 283                         reg = <0x4806a000 0x2000>;
 284                         interrupts-extended = <&intc 72>;
 285                         dmas = <&sdma 49 &sdma 50>;
 286                         dma-names = "tx", "rx";
 287                         ti,hwmods = "uart1";
 288                         clock-frequency = <48000000>;
 289                 };
 290
 291                 uart2: serial@4806c000 {
 292                         compatible = "ti,omap3-uart";
 293                         reg = <0x4806c000 0x400>;
 294                         interrupts-extended = <&intc 73>;
 295                         dmas = <&sdma 51 &sdma 52>;
 296                         dma-names = "tx", "rx";
 297                         ti,hwmods = "uart2";
 298                         clock-frequency = <48000000>;
 299                 };
 300
 301                 uart3: serial@49020000 {
 302                         compatible = "ti,omap3-uart";
 303                         reg = <0x49020000 0x400>;
 304                         interrupts-extended = <&intc 74>;
 305                         dmas = <&sdma 53 &sdma 54>;
 306                         dma-names = "tx", "rx";
 307                         ti,hwmods = "uart3";
 308                         clock-frequency = <48000000>;
 309                 };
 310
 311                 i2c1: i2c@48070000 {
 312                         compatible = "ti,omap3-i2c";
 313                         reg = <0x48070000 0x80>;
 314                         interrupts = <56>;
 315                         dmas = <&sdma 27 &sdma 28>;
 316                         dma-names = "tx", "rx";
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         ti,hwmods = "i2c1";
 320                 };
 321
 322                 i2c2: i2c@48072000 {
 323                         compatible = "ti,omap3-i2c";
 324                         reg = <0x48072000 0x80>;
 325                         interrupts = <57>;
 326                         dmas = <&sdma 29 &sdma 30>;
 327                         dma-names = "tx", "rx";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         ti,hwmods = "i2c2";
 331                 };
 332
 333                 i2c3: i2c@48060000 {
 334                         compatible = "ti,omap3-i2c";
 335                         reg = <0x48060000 0x80>;
 336                         interrupts = <61>;
 337                         dmas = <&sdma 25 &sdma 26>;
 338                         dma-names = "tx", "rx";
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         ti,hwmods = "i2c3";
 342                 };
 343
 344                 mailbox: mailbox@48094000 {
 345                         compatible = "ti,omap3-mailbox";
 346                         ti,hwmods = "mailbox";
 347                         reg = <0x48094000 0x200>;
 348                         interrupts = <26>;
 349                         #mbox-cells = <1>;
 350                         ti,mbox-num-users = <2>;
 351                         ti,mbox-num-fifos = <2>;
 352                         mbox_dsp: dsp {
 353                                 ti,mbox-tx = <0 0 0>;
 354                                 ti,mbox-rx = <1 0 0>;
 355                         };
 356                 };
 357
 358                 mcspi1: spi@48098000 {
 359                         compatible = "ti,omap2-mcspi";
 360                         reg = <0x48098000 0x100>;
 361                         interrupts = <65>;
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         ti,hwmods = "mcspi1";
 365                         ti,spi-num-cs = <4>;
 366                         dmas = <&sdma 35>,
 367                                <&sdma 36>,
 368                                <&sdma 37>,
 369                                <&sdma 38>,
 370                                <&sdma 39>,
 371                                <&sdma 40>,
 372                                <&sdma 41>,
 373                                <&sdma 42>;
 374                         dma-names = "tx0", "rx0", "tx1", "rx1",
 375                                     "tx2", "rx2", "tx3", "rx3";
 376                 };
 377
 378                 mcspi2: spi@4809a000 {
 379                         compatible = "ti,omap2-mcspi";
 380                         reg = <0x4809a000 0x100>;
 381                         interrupts = <66>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         ti,hwmods = "mcspi2";
 385                         ti,spi-num-cs = <2>;
 386                         dmas = <&sdma 43>,
 387                                <&sdma 44>,
 388                                <&sdma 45>,
 389                                <&sdma 46>;
 390                         dma-names = "tx0", "rx0", "tx1", "rx1";
 391                 };
 392
 393                 mcspi3: spi@480b8000 {
 394                         compatible = "ti,omap2-mcspi";
 395                         reg = <0x480b8000 0x100>;
 396                         interrupts = <91>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         ti,hwmods = "mcspi3";
 400                         ti,spi-num-cs = <2>;
 401                         dmas = <&sdma 15>,
 402                                <&sdma 16>,
 403                                <&sdma 23>,
 404                                <&sdma 24>;
 405                         dma-names = "tx0", "rx0", "tx1", "rx1";
 406                 };
 407
 408                 mcspi4: spi@480ba000 {
 409                         compatible = "ti,omap2-mcspi";
 410                         reg = <0x480ba000 0x100>;
 411                         interrupts = <48>;
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         ti,hwmods = "mcspi4";
 415                         ti,spi-num-cs = <1>;
 416                         dmas = <&sdma 70>, <&sdma 71>;
 417                         dma-names = "tx0", "rx0";
 418                 };
 419
 420                 hdqw1w: 1w@480b2000 {
 421                         compatible = "ti,omap3-1w";
 422                         reg = <0x480b2000 0x1000>;
 423                         interrupts = <58>;
 424                         ti,hwmods = "hdq1w";
 425                 };
 426
 427                 mmc1: mmc@4809c000 {
 428                         compatible = "ti,omap3-hsmmc";
 429                         reg = <0x4809c000 0x200>;
 430                         interrupts = <83>;
 431                         ti,hwmods = "mmc1";
 432                         ti,dual-volt;
 433                         dmas = <&sdma 61>, <&sdma 62>;
 434                         dma-names = "tx", "rx";
 435                         pbias-supply = <&pbias_mmc_reg>;
 436                 };
 437
 438                 mmc2: mmc@480b4000 {
 439                         compatible = "ti,omap3-hsmmc";
 440                         reg = <0x480b4000 0x200>;
 441                         interrupts = <86>;
 442                         ti,hwmods = "mmc2";
 443                         dmas = <&sdma 47>, <&sdma 48>;
 444                         dma-names = "tx", "rx";
 445                 };
 446
 447                 mmc3: mmc@480ad000 {
 448                         compatible = "ti,omap3-hsmmc";
 449                         reg = <0x480ad000 0x200>;
 450                         interrupts = <94>;
 451                         ti,hwmods = "mmc3";
 452                         dmas = <&sdma 77>, <&sdma 78>;
 453                         dma-names = "tx", "rx";
 454                 };
 455
 456                 mmu_isp: mmu@480bd400 {
 457                         compatible = "ti,omap2-iommu";
 458                         reg = <0x480bd400 0x80>;
 459                         interrupts = <24>;
 460                         ti,hwmods = "mmu_isp";
 461                         ti,#tlb-entries = <8>;
 462                 };
 463
 464                 mmu_iva: mmu@5d000000 {
 465                         compatible = "ti,omap2-iommu";
 466                         reg = <0x5d000000 0x80>;
 467                         interrupts = <28>;
 468                         ti,hwmods = "mmu_iva";
 469                         status = "disabled";
 470                 };
 471
 472                 wdt2: wdt@48314000 {
 473                         compatible = "ti,omap3-wdt";
 474                         reg = <0x48314000 0x80>;
 475                         ti,hwmods = "wd_timer2";
 476                 };
 477
 478                 mcbsp1: mcbsp@48074000 {
 479                         compatible = "ti,omap3-mcbsp";
 480                         reg = <0x48074000 0xff>;
 481                         reg-names = "mpu";
 482                         interrupts = <16>, /* OCP compliant interrupt */
 483                                      <59>, /* TX interrupt */
 484                                      <60>; /* RX interrupt */
 485                         interrupt-names = "common", "tx", "rx";
 486                         ti,buffer-size = <128>;
 487                         ti,hwmods = "mcbsp1";
 488                         dmas = <&sdma 31>,
 489                                <&sdma 32>;
 490                         dma-names = "tx", "rx";
 491                         status = "disabled";
 492                 };
 493
 494                 mcbsp2: mcbsp@49022000 {
 495                         compatible = "ti,omap3-mcbsp";
 496                         reg = <0x49022000 0xff>,
 497                               <0x49028000 0xff>;
 498                         reg-names = "mpu", "sidetone";
 499                         interrupts = <17>, /* OCP compliant interrupt */
 500                                      <62>, /* TX interrupt */
 501                                      <63>, /* RX interrupt */
 502                                      <4>;  /* Sidetone */
 503                         interrupt-names = "common", "tx", "rx", "sidetone";
 504                         ti,buffer-size = <1280>;
 505                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 506                         dmas = <&sdma 33>,
 507                                <&sdma 34>;
 508                         dma-names = "tx", "rx";
 509                         status = "disabled";
 510                 };
 511
 512                 mcbsp3: mcbsp@49024000 {
 513                         compatible = "ti,omap3-mcbsp";
 514                         reg = <0x49024000 0xff>,
 515                               <0x4902a000 0xff>;
 516                         reg-names = "mpu", "sidetone";
 517                         interrupts = <22>, /* OCP compliant interrupt */
 518                                      <89>, /* TX interrupt */
 519                                      <90>, /* RX interrupt */
 520                                      <5>;  /* Sidetone */
 521                         interrupt-names = "common", "tx", "rx", "sidetone";
 522                         ti,buffer-size = <128>;
 523                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 524                         dmas = <&sdma 17>,
 525                                <&sdma 18>;
 526                         dma-names = "tx", "rx";
 527                         status = "disabled";
 528                 };
 529
 530                 mcbsp4: mcbsp@49026000 {
 531                         compatible = "ti,omap3-mcbsp";
 532                         reg = <0x49026000 0xff>;
 533                         reg-names = "mpu";
 534                         interrupts = <23>, /* OCP compliant interrupt */
 535                                      <54>, /* TX interrupt */
 536                                      <55>; /* RX interrupt */
 537                         interrupt-names = "common", "tx", "rx";
 538                         ti,buffer-size = <128>;
 539                         ti,hwmods = "mcbsp4";
 540                         dmas = <&sdma 19>,
 541                                <&sdma 20>;
 542                         dma-names = "tx", "rx";
 543                         status = "disabled";
 544                 };
 545
 546                 mcbsp5: mcbsp@48096000 {
 547                         compatible = "ti,omap3-mcbsp";
 548                         reg = <0x48096000 0xff>;
 549                         reg-names = "mpu";
 550                         interrupts = <27>, /* OCP compliant interrupt */
 551                                      <81>, /* TX interrupt */
 552                                      <82>; /* RX interrupt */
 553                         interrupt-names = "common", "tx", "rx";
 554                         ti,buffer-size = <128>;
 555                         ti,hwmods = "mcbsp5";
 556                         dmas = <&sdma 21>,
 557                                <&sdma 22>;
 558                         dma-names = "tx", "rx";
 559                         status = "disabled";
 560                 };
 561
 562                 sham: sham@480c3000 {
 563                         compatible = "ti,omap3-sham";
 564                         ti,hwmods = "sham";
 565                         reg = <0x480c3000 0x64>;
 566                         interrupts = <49>;
 567                 };
 568
 569                 smartreflex_core: smartreflex@480cb000 {
 570                         compatible = "ti,omap3-smartreflex-core";
 571                         ti,hwmods = "smartreflex_core";
 572                         reg = <0x480cb000 0x400>;
 573                         interrupts = <19>;
 574                 };
 575
 576                 smartreflex_mpu_iva: smartreflex@480c9000 {
 577                         compatible = "ti,omap3-smartreflex-iva";
 578                         ti,hwmods = "smartreflex_mpu_iva";
 579                         reg = <0x480c9000 0x400>;
 580                         interrupts = <18>;
 581                 };
 582
 583                 timer1: timer@48318000 {
 584                         compatible = "ti,omap3430-timer";
 585                         reg = <0x48318000 0x400>;
 586                         interrupts = <37>;
 587                         ti,hwmods = "timer1";
 588                         ti,timer-alwon;
 589                 };
 590
 591                 timer2: timer@49032000 {
 592                         compatible = "ti,omap3430-timer";
 593                         reg = <0x49032000 0x400>;
 594                         interrupts = <38>;
 595                         ti,hwmods = "timer2";
 596                 };
 597
 598                 timer3: timer@49034000 {
 599                         compatible = "ti,omap3430-timer";
 600                         reg = <0x49034000 0x400>;
 601                         interrupts = <39>;
 602                         ti,hwmods = "timer3";
 603                 };
 604
 605                 timer4: timer@49036000 {
 606                         compatible = "ti,omap3430-timer";
 607                         reg = <0x49036000 0x400>;
 608                         interrupts = <40>;
 609                         ti,hwmods = "timer4";
 610                 };
 611
 612                 timer5: timer@49038000 {
 613                         compatible = "ti,omap3430-timer";
 614                         reg = <0x49038000 0x400>;
 615                         interrupts = <41>;
 616                         ti,hwmods = "timer5";
 617                         ti,timer-dsp;
 618                 };
 619
 620                 timer6: timer@4903a000 {
 621                         compatible = "ti,omap3430-timer";
 622                         reg = <0x4903a000 0x400>;
 623                         interrupts = <42>;
 624                         ti,hwmods = "timer6";
 625                         ti,timer-dsp;
 626                 };
 627
 628                 timer7: timer@4903c000 {
 629                         compatible = "ti,omap3430-timer";
 630                         reg = <0x4903c000 0x400>;
 631                         interrupts = <43>;
 632                         ti,hwmods = "timer7";
 633                         ti,timer-dsp;
 634                 };
 635
 636                 timer8: timer@4903e000 {
 637                         compatible = "ti,omap3430-timer";
 638                         reg = <0x4903e000 0x400>;
 639                         interrupts = <44>;
 640                         ti,hwmods = "timer8";
 641                         ti,timer-pwm;
 642                         ti,timer-dsp;
 643                 };
 644
 645                 timer9: timer@49040000 {
 646                         compatible = "ti,omap3430-timer";
 647                         reg = <0x49040000 0x400>;
 648                         interrupts = <45>;
 649                         ti,hwmods = "timer9";
 650                         ti,timer-pwm;
 651                 };
 652
 653                 timer10: timer@48086000 {
 654                         compatible = "ti,omap3430-timer";
 655                         reg = <0x48086000 0x400>;
 656                         interrupts = <46>;
 657                         ti,hwmods = "timer10";
 658                         ti,timer-pwm;
 659                 };
 660
 661                 timer11: timer@48088000 {
 662                         compatible = "ti,omap3430-timer";
 663                         reg = <0x48088000 0x400>;
 664                         interrupts = <47>;
 665                         ti,hwmods = "timer11";
 666                         ti,timer-pwm;
 667                 };
 668
 669                 timer12: timer@48304000 {
 670                         compatible = "ti,omap3430-timer";
 671                         reg = <0x48304000 0x400>;
 672                         interrupts = <95>;
 673                         ti,hwmods = "timer12";
 674                         ti,timer-alwon;
 675                         ti,timer-secure;
 676                 };
 677
 678                 usbhstll: usbhstll@48062000 {
 679                         compatible = "ti,usbhs-tll";
 680                         reg = <0x48062000 0x1000>;
 681                         interrupts = <78>;
 682                         ti,hwmods = "usb_tll_hs";
 683                 };
 684
 685                 usbhshost: usbhshost@48064000 {
 686                         compatible = "ti,usbhs-host";
 687                         reg = <0x48064000 0x400>;
 688                         ti,hwmods = "usb_host_hs";
 689                         #address-cells = <1>;
 690                         #size-cells = <1>;
 691                         ranges;
 692
 693                         usbhsohci: ohci@48064400 {
 694                                 compatible = "ti,ohci-omap3";
 695                                 reg = <0x48064400 0x400>;
 696                                 interrupt-parent = <&intc>;
 697                                 interrupts = <76>;
 698                         };
 699
 700                         usbhsehci: ehci@48064800 {
 701                                 compatible = "ti,ehci-omap";
 702                                 reg = <0x48064800 0x400>;
 703                                 interrupt-parent = <&intc>;
 704                                 interrupts = <77>;
 705                         };
 706                 };
 707
 708                 gpmc: gpmc@6e000000 {
 709                         compatible = "ti,omap3430-gpmc";
 710                         ti,hwmods = "gpmc";
 711                         reg = <0x6e000000 0x02d0>;
 712                         interrupts = <20>;
 713                         gpmc,num-cs = <8>;
 714                         gpmc,num-waitpins = <4>;
 715                         #address-cells = <2>;
 716                         #size-cells = <1>;
 717                 };
 718
 719                 usb_otg_hs: usb_otg_hs@480ab000 {
 720                         compatible = "ti,omap3-musb";
 721                         reg = <0x480ab000 0x1000>;
 722                         interrupts = <92>, <93>;
 723                         interrupt-names = "mc", "dma";
 724                         ti,hwmods = "usb_otg_hs";
 725                         multipoint = <1>;
 726                         num-eps = <16>;
 727                         ram-bits = <12>;
 728                 };
 729
 730                 dss: dss@48050000 {
 731                         compatible = "ti,omap3-dss";
 732                         reg = <0x48050000 0x200>;
 733                         status = "disabled";
 734                         ti,hwmods = "dss_core";
 735                         clocks = <&dss1_alwon_fck>;
 736                         clock-names = "fck";
 737                         #address-cells = <1>;
 738                         #size-cells = <1>;
 739                         ranges;
 740
 741                         dispc@48050400 {
 742                                 compatible = "ti,omap3-dispc";
 743                                 reg = <0x48050400 0x400>;
 744                                 interrupts = <25>;
 745                                 ti,hwmods = "dss_dispc";
 746                                 clocks = <&dss1_alwon_fck>;
 747                                 clock-names = "fck";
 748                         };
 749
 750                         dsi: encoder@4804fc00 {
 751                                 compatible = "ti,omap3-dsi";
 752                                 reg = <0x4804fc00 0x200>,
 753                                       <0x4804fe00 0x40>,
 754                                       <0x4804ff00 0x20>;
 755                                 reg-names = "proto", "phy", "pll";
 756                                 interrupts = <25>;
 757                                 status = "disabled";
 758                                 ti,hwmods = "dss_dsi1";
 759                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 760                                 clock-names = "fck", "sys_clk";
 761                         };
 762
 763                         rfbi: encoder@48050800 {
 764                                 compatible = "ti,omap3-rfbi";
 765                                 reg = <0x48050800 0x100>;
 766                                 status = "disabled";
 767                                 ti,hwmods = "dss_rfbi";
 768                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 769                                 clock-names = "fck", "ick";
 770                         };
 771
 772                         venc: encoder@48050c00 {
 773                                 compatible = "ti,omap3-venc";
 774                                 reg = <0x48050c00 0x100>;
 775                                 status = "disabled";
 776                                 ti,hwmods = "dss_venc";
 777                                 clocks = <&dss_tv_fck>;
 778                                 clock-names = "fck";
 779                         };
 780                 };
 781
 782                 ssi: ssi-controller@48058000 {
 783                         compatible = "ti,omap3-ssi";
 784                         ti,hwmods = "ssi";
 785
 786                         status = "disabled";
 787
 788                         reg = <0x48058000 0x1000>,
 789                               <0x48059000 0x1000>;
 790                         reg-names = "sys",
 791                                     "gdd";
 792
 793                         interrupts = <71>;
 794                         interrupt-names = "gdd_mpu";
 795
 796                         #address-cells = <1>;
 797                         #size-cells = <1>;
 798                         ranges;
 799
 800                         ssi_port1: ssi-port@4805a000 {
 801                                 compatible = "ti,omap3-ssi-port";
 802
 803                                 reg = <0x4805a000 0x800>,
 804                                       <0x4805a800 0x800>;
 805                                 reg-names = "tx",
 806                                             "rx";
 807
 808                                 interrupt-parent = <&intc>;
 809                                 interrupts = <67>,
 810                                              <68>;
 811                         };
 812
 813                         ssi_port2: ssi-port@4805b000 {
 814                                 compatible = "ti,omap3-ssi-port";
 815
 816                                 reg = <0x4805b000 0x800>,
 817                                       <0x4805b800 0x800>;
 818                                 reg-names = "tx",
 819                                             "rx";
 820
 821                                 interrupt-parent = <&intc>;
 822                                 interrupts = <69>,
 823                                              <70>;
 824                         };
 825                 };
 826         };
 827 };
 828
 829 /include/ "omap3xxx-clocks.dtsi"