Merge branch 'upstream' of git://git.infradead.org/users/pcmoore/selinux into for...
[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / mt6592.dtsi
1 /*
2  * Copyright (c) 2014 MediaTek Inc.
3  * Author: Howard Chen <ibanezchen@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "skeleton.dtsi"
18
19 / {
20         compatible = "mediatek,mt6592";
21         interrupt-parent = <&sysirq>;
22
23         cpus {
24                 #address-cells = <1>;
25                 #size-cells = <0>;
26
27                 cpu@0 {
28                         device_type = "cpu";
29                         compatible = "arm,cortex-a7";
30                         reg = <0x0>;
31                 };
32                 cpu@1 {
33                         device_type = "cpu";
34                         compatible = "arm,cortex-a7";
35                         reg = <0x1>;
36                 };
37                 cpu@2 {
38                         device_type = "cpu";
39                         compatible = "arm,cortex-a7";
40                         reg = <0x2>;
41                 };
42                 cpu@3 {
43                         device_type = "cpu";
44                         compatible = "arm,cortex-a7";
45                         reg = <0x3>;
46                 };
47                 cpu@4 {
48                         device_type = "cpu";
49                         compatible = "arm,cortex-a7";
50                         reg = <0x4>;
51                 };
52                 cpu@5 {
53                         device_type = "cpu";
54                         compatible = "arm,cortex-a7";
55                         reg = <0x5>;
56                 };
57                 cpu@6 {
58                         device_type = "cpu";
59                         compatible = "arm,cortex-a7";
60                         reg = <0x6>;
61                 };
62                 cpu@7 {
63                         device_type = "cpu";
64                         compatible = "arm,cortex-a7";
65                         reg = <0x7>;
66                 };
67         };
68
69         system_clk: dummy13m {
70                 compatible = "fixed-clock";
71                 clock-frequency = <13000000>;
72                 #clock-cells = <0>;
73         };
74
75         rtc_clk: dummy32k {
76                 compatible = "fixed-clock";
77                 clock-frequency = <32000>;
78                 #clock-cells = <0>;
79         };
80
81         uart_clk: dummy26m {
82                 compatible = "fixed-clock";
83                 clock-frequency = <26000000>;
84                 #clock-cells = <0>;
85         };
86
87         timer: timer@10008000 {
88                 compatible = "mediatek,mt6577-timer";
89                 reg = <0x10008000 0x80>;
90                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
91                 clocks = <&system_clk>, <&rtc_clk>;
92                 clock-names = "system-clk", "rtc-clk";
93         };
94
95         sysirq: interrupt-controller@10200220 {
96                 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
97                 interrupt-controller;
98                 #interrupt-cells = <3>;
99                 interrupt-parent = <&gic>;
100                 reg = <0x10200220 0x1c>;
101         };
102
103         gic: interrupt-controller@10211000 {
104                 compatible = "arm,cortex-a7-gic";
105                 interrupt-controller;
106                 #interrupt-cells = <3>;
107                 interrupt-parent = <&gic>;
108                 reg = <0x10211000 0x1000>,
109                       <0x10212000 0x1000>;
110         };
111
112         uart0: serial@11002000 {
113                 compatible = "mediatek,mt6577-uart";
114                 reg = <0x11002000 0x400>;
115                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
116                 clocks = <&uart_clk>;
117                 status = "disabled";
118         };
119
120         uart1: serial@11003000 {
121                 compatible = "mediatek,mt6577-uart";
122                 reg = <0x11003000 0x400>;
123                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
124                 clocks = <&uart_clk>;
125                 status = "disabled";
126         };
127
128         uart2: serial@11004000 {
129                 compatible = "mediatek,mt6577-uart";
130                 reg = <0x11004000 0x400>;
131                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
132                 clocks = <&uart_clk>;
133                 status = "disabled";
134         };
135
136         uart3: serial@11005000 {
137                 compatible = "mediatek,mt6577-uart";
138                 reg = <0x11005000 0x400>;
139                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
140                 clocks = <&uart_clk>;
141                 status = "disabled";
142         };
143 };