2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Howard Chen <ibanezchen@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "skeleton.dtsi"
20 compatible = "mediatek,mt6592";
21 interrupt-parent = <&sysirq>;
29 compatible = "arm,cortex-a7";
34 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7";
44 compatible = "arm,cortex-a7";
49 compatible = "arm,cortex-a7";
54 compatible = "arm,cortex-a7";
59 compatible = "arm,cortex-a7";
64 compatible = "arm,cortex-a7";
69 system_clk: dummy13m {
70 compatible = "fixed-clock";
71 clock-frequency = <13000000>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
82 compatible = "fixed-clock";
83 clock-frequency = <26000000>;
87 timer: timer@10008000 {
88 compatible = "mediatek,mt6577-timer";
89 reg = <0x10008000 0x80>;
90 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
91 clocks = <&system_clk>, <&rtc_clk>;
92 clock-names = "system-clk", "rtc-clk";
95 sysirq: interrupt-controller@10200220 {
96 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
98 #interrupt-cells = <3>;
99 interrupt-parent = <&gic>;
100 reg = <0x10200220 0x1c>;
103 gic: interrupt-controller@10211000 {
104 compatible = "arm,cortex-a7-gic";
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 interrupt-parent = <&gic>;
108 reg = <0x10211000 0x1000>,
112 uart0: serial@11002000 {
113 compatible = "mediatek,mt6577-uart";
114 reg = <0x11002000 0x400>;
115 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
116 clocks = <&uart_clk>;
120 uart1: serial@11003000 {
121 compatible = "mediatek,mt6577-uart";
122 reg = <0x11003000 0x400>;
123 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
124 clocks = <&uart_clk>;
128 uart2: serial@11004000 {
129 compatible = "mediatek,mt6577-uart";
130 reg = <0x11004000 0x400>;
131 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
132 clocks = <&uart_clk>;
136 uart3: serial@11005000 {
137 compatible = "mediatek,mt6577-uart";
138 reg = <0x11005000 0x400>;
139 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
140 clocks = <&uart_clk>;