arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "skeleton.dtsi"
  12 #include "imx6sl-pinfunc.h"
  13 #include <dt-bindings/clock/imx6sl-clock.h>
  14
  15 / {
  16         aliases {
  17                 ethernet0 = &fec;
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 serial0 = &uart1;
  24                 serial1 = &uart2;
  25                 serial2 = &uart3;
  26                 serial3 = &uart4;
  27                 serial4 = &uart5;
  28                 spi0 = &ecspi1;
  29                 spi1 = &ecspi2;
  30                 spi2 = &ecspi3;
  31                 spi3 = &ecspi4;
  32                 usbphy0 = &usbphy1;
  33                 usbphy1 = &usbphy2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         reg = <0x0>;
  44                         next-level-cache = <&L2>;
  45                         operating-points = <
  46                                 /* kHz    uV */
  47                                 996000  1275000
  48                                 792000  1175000
  49                                 396000  975000
  50                         >;
  51                         fsl,soc-operating-points = <
  52                                 /* ARM kHz      SOC-PU uV */
  53                                 996000          1225000
  54                                 792000          1175000
  55                                 396000          1175000
  56                         >;
  57                         clock-latency = <61036>; /* two CLK32 periods */
  58                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  59                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  60                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  61                         clock-names = "arm", "pll2_pfd2_396m", "step",
  62                                       "pll1_sw", "pll1_sys";
  63                         arm-supply = <&reg_arm>;
  64                         pu-supply = <&reg_pu>;
  65                         soc-supply = <&reg_soc>;
  66                 };
  67         };
  68
  69         intc: interrupt-controller@00a01000 {
  70                 compatible = "arm,cortex-a9-gic";
  71                 #interrupt-cells = <3>;
  72                 interrupt-controller;
  73                 reg = <0x00a01000 0x1000>,
  74                       <0x00a00100 0x100>;
  75         };
  76
  77         clocks {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 ckil {
  82                         compatible = "fixed-clock";
  83                         #clock-cells = <0>;
  84                         clock-frequency = <32768>;
  85                 };
  86
  87                 osc {
  88                         compatible = "fixed-clock";
  89                         #clock-cells = <0>;
  90                         clock-frequency = <24000000>;
  91                 };
  92         };
  93
  94         soc {
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 compatible = "simple-bus";
  98                 interrupt-parent = <&intc>;
  99                 ranges;
 100
 101                 ocram: sram@00900000 {
 102                         compatible = "mmio-sram";
 103                         reg = <0x00900000 0x20000>;
 104                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 105                 };
 106
 107                 L2: l2-cache@00a02000 {
 108                         compatible = "arm,pl310-cache";
 109                         reg = <0x00a02000 0x1000>;
 110                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 111                         cache-unified;
 112                         cache-level = <2>;
 113                         arm,tag-latency = <4 2 3>;
 114                         arm,data-latency = <4 2 3>;
 115                 };
 116
 117                 pmu {
 118                         compatible = "arm,cortex-a9-pmu";
 119                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 120                 };
 121
 122                 aips1: aips-bus@02000000 {
 123                         compatible = "fsl,aips-bus", "simple-bus";
 124                         #address-cells = <1>;
 125                         #size-cells = <1>;
 126                         reg = <0x02000000 0x100000>;
 127                         ranges;
 128
 129                         spba: spba-bus@02000000 {
 130                                 compatible = "fsl,spba-bus", "simple-bus";
 131                                 #address-cells = <1>;
 132                                 #size-cells = <1>;
 133                                 reg = <0x02000000 0x40000>;
 134                                 ranges;
 135
 136                                 spdif: spdif@02004000 {
 137                                         reg = <0x02004000 0x4000>;
 138                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 139                                 };
 140
 141                                 ecspi1: ecspi@02008000 {
 142                                         #address-cells = <1>;
 143                                         #size-cells = <0>;
 144                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 145                                         reg = <0x02008000 0x4000>;
 146                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 147                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 148                                                  <&clks IMX6SL_CLK_ECSPI1>;
 149                                         clock-names = "ipg", "per";
 150                                         status = "disabled";
 151                                 };
 152
 153                                 ecspi2: ecspi@0200c000 {
 154                                         #address-cells = <1>;
 155                                         #size-cells = <0>;
 156                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 157                                         reg = <0x0200c000 0x4000>;
 158                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 159                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 160                                                  <&clks IMX6SL_CLK_ECSPI2>;
 161                                         clock-names = "ipg", "per";
 162                                         status = "disabled";
 163                                 };
 164
 165                                 ecspi3: ecspi@02010000 {
 166                                         #address-cells = <1>;
 167                                         #size-cells = <0>;
 168                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 169                                         reg = <0x02010000 0x4000>;
 170                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 171                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 172                                                  <&clks IMX6SL_CLK_ECSPI3>;
 173                                         clock-names = "ipg", "per";
 174                                         status = "disabled";
 175                                 };
 176
 177                                 ecspi4: ecspi@02014000 {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 181                                         reg = <0x02014000 0x4000>;
 182                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 183                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 184                                                  <&clks IMX6SL_CLK_ECSPI4>;
 185                                         clock-names = "ipg", "per";
 186                                         status = "disabled";
 187                                 };
 188
 189                                 uart5: serial@02018000 {
 190                                         compatible = "fsl,imx6sl-uart",
 191                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 192                                         reg = <0x02018000 0x4000>;
 193                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 194                                         clocks = <&clks IMX6SL_CLK_UART>,
 195                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 196                                         clock-names = "ipg", "per";
 197                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 198                                         dma-names = "rx", "tx";
 199                                         status = "disabled";
 200                                 };
 201
 202                                 uart1: serial@02020000 {
 203                                         compatible = "fsl,imx6sl-uart",
 204                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 205                                         reg = <0x02020000 0x4000>;
 206                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 207                                         clocks = <&clks IMX6SL_CLK_UART>,
 208                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 209                                         clock-names = "ipg", "per";
 210                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 211                                         dma-names = "rx", "tx";
 212                                         status = "disabled";
 213                                 };
 214
 215                                 uart2: serial@02024000 {
 216                                         compatible = "fsl,imx6sl-uart",
 217                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 218                                         reg = <0x02024000 0x4000>;
 219                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 220                                         clocks = <&clks IMX6SL_CLK_UART>,
 221                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 222                                         clock-names = "ipg", "per";
 223                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 224                                         dma-names = "rx", "tx";
 225                                         status = "disabled";
 226                                 };
 227
 228                                 ssi1: ssi@02028000 {
 229                                         compatible = "fsl,imx6sl-ssi",
 230                                                         "fsl,imx51-ssi";
 231                                         reg = <0x02028000 0x4000>;
 232                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6SL_CLK_SSI1>;
 234                                         dmas = <&sdma 37 1 0>,
 235                                                <&sdma 38 1 0>;
 236                                         dma-names = "rx", "tx";
 237                                         fsl,fifo-depth = <15>;
 238                                         status = "disabled";
 239                                 };
 240
 241                                 ssi2: ssi@0202c000 {
 242                                         compatible = "fsl,imx6sl-ssi",
 243                                                         "fsl,imx51-ssi";
 244                                         reg = <0x0202c000 0x4000>;
 245                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 246                                         clocks = <&clks IMX6SL_CLK_SSI2>;
 247                                         dmas = <&sdma 41 1 0>,
 248                                                <&sdma 42 1 0>;
 249                                         dma-names = "rx", "tx";
 250                                         fsl,fifo-depth = <15>;
 251                                         status = "disabled";
 252                                 };
 253
 254                                 ssi3: ssi@02030000 {
 255                                         compatible = "fsl,imx6sl-ssi",
 256                                                         "fsl,imx51-ssi";
 257                                         reg = <0x02030000 0x4000>;
 258                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 259                                         clocks = <&clks IMX6SL_CLK_SSI3>;
 260                                         dmas = <&sdma 45 1 0>,
 261                                                <&sdma 46 1 0>;
 262                                         dma-names = "rx", "tx";
 263                                         fsl,fifo-depth = <15>;
 264                                         status = "disabled";
 265                                 };
 266
 267                                 uart3: serial@02034000 {
 268                                         compatible = "fsl,imx6sl-uart",
 269                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 270                                         reg = <0x02034000 0x4000>;
 271                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 272                                         clocks = <&clks IMX6SL_CLK_UART>,
 273                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 274                                         clock-names = "ipg", "per";
 275                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 276                                         dma-names = "rx", "tx";
 277                                         status = "disabled";
 278                                 };
 279
 280                                 uart4: serial@02038000 {
 281                                         compatible = "fsl,imx6sl-uart",
 282                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 283                                         reg = <0x02038000 0x4000>;
 284                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6SL_CLK_UART>,
 286                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 287                                         clock-names = "ipg", "per";
 288                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 289                                         dma-names = "rx", "tx";
 290                                         status = "disabled";
 291                                 };
 292                         };
 293
 294                         pwm1: pwm@02080000 {
 295                                 #pwm-cells = <2>;
 296                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 297                                 reg = <0x02080000 0x4000>;
 298                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 299                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 300                                          <&clks IMX6SL_CLK_PWM1>;
 301                                 clock-names = "ipg", "per";
 302                         };
 303
 304                         pwm2: pwm@02084000 {
 305                                 #pwm-cells = <2>;
 306                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 307                                 reg = <0x02084000 0x4000>;
 308                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 309                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 310                                          <&clks IMX6SL_CLK_PWM2>;
 311                                 clock-names = "ipg", "per";
 312                         };
 313
 314                         pwm3: pwm@02088000 {
 315                                 #pwm-cells = <2>;
 316                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 317                                 reg = <0x02088000 0x4000>;
 318                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 319                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 320                                          <&clks IMX6SL_CLK_PWM3>;
 321                                 clock-names = "ipg", "per";
 322                         };
 323
 324                         pwm4: pwm@0208c000 {
 325                                 #pwm-cells = <2>;
 326                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 327                                 reg = <0x0208c000 0x4000>;
 328                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 329                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 330                                          <&clks IMX6SL_CLK_PWM4>;
 331                                 clock-names = "ipg", "per";
 332                         };
 333
 334                         gpt: gpt@02098000 {
 335                                 compatible = "fsl,imx6sl-gpt";
 336                                 reg = <0x02098000 0x4000>;
 337                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clks IMX6SL_CLK_GPT>,
 339                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 340                                 clock-names = "ipg", "per";
 341                         };
 342
 343                         gpio1: gpio@0209c000 {
 344                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 345                                 reg = <0x0209c000 0x4000>;
 346                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 347                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 348                                 gpio-controller;
 349                                 #gpio-cells = <2>;
 350                                 interrupt-controller;
 351                                 #interrupt-cells = <2>;
 352                         };
 353
 354                         gpio2: gpio@020a0000 {
 355                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 356                                 reg = <0x020a0000 0x4000>;
 357                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 358                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 359                                 gpio-controller;
 360                                 #gpio-cells = <2>;
 361                                 interrupt-controller;
 362                                 #interrupt-cells = <2>;
 363                         };
 364
 365                         gpio3: gpio@020a4000 {
 366                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 367                                 reg = <0x020a4000 0x4000>;
 368                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 369                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 370                                 gpio-controller;
 371                                 #gpio-cells = <2>;
 372                                 interrupt-controller;
 373                                 #interrupt-cells = <2>;
 374                         };
 375
 376                         gpio4: gpio@020a8000 {
 377                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 378                                 reg = <0x020a8000 0x4000>;
 379                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 380                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 381                                 gpio-controller;
 382                                 #gpio-cells = <2>;
 383                                 interrupt-controller;
 384                                 #interrupt-cells = <2>;
 385                         };
 386
 387                         gpio5: gpio@020ac000 {
 388                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 389                                 reg = <0x020ac000 0x4000>;
 390                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 391                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 392                                 gpio-controller;
 393                                 #gpio-cells = <2>;
 394                                 interrupt-controller;
 395                                 #interrupt-cells = <2>;
 396                         };
 397
 398                         kpp: kpp@020b8000 {
 399                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 400                                 reg = <0x020b8000 0x4000>;
 401                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 402                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 403                                 status = "disabled";
 404                         };
 405
 406                         wdog1: wdog@020bc000 {
 407                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 408                                 reg = <0x020bc000 0x4000>;
 409                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 410                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 411                         };
 412
 413                         wdog2: wdog@020c0000 {
 414                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 415                                 reg = <0x020c0000 0x4000>;
 416                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 418                                 status = "disabled";
 419                         };
 420
 421                         clks: ccm@020c4000 {
 422                                 compatible = "fsl,imx6sl-ccm";
 423                                 reg = <0x020c4000 0x4000>;
 424                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 425                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 426                                 #clock-cells = <1>;
 427                         };
 428
 429                         anatop: anatop@020c8000 {
 430                                 compatible = "fsl,imx6sl-anatop",
 431                                              "fsl,imx6q-anatop",
 432                                              "syscon", "simple-bus";
 433                                 reg = <0x020c8000 0x1000>;
 434                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 435                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 436                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 437
 438                                 regulator-1p1@110 {
 439                                         compatible = "fsl,anatop-regulator";
 440                                         regulator-name = "vdd1p1";
 441                                         regulator-min-microvolt = <800000>;
 442                                         regulator-max-microvolt = <1375000>;
 443                                         regulator-always-on;
 444                                         anatop-reg-offset = <0x110>;
 445                                         anatop-vol-bit-shift = <8>;
 446                                         anatop-vol-bit-width = <5>;
 447                                         anatop-min-bit-val = <4>;
 448                                         anatop-min-voltage = <800000>;
 449                                         anatop-max-voltage = <1375000>;
 450                                 };
 451
 452                                 regulator-3p0@120 {
 453                                         compatible = "fsl,anatop-regulator";
 454                                         regulator-name = "vdd3p0";
 455                                         regulator-min-microvolt = <2800000>;
 456                                         regulator-max-microvolt = <3150000>;
 457                                         regulator-always-on;
 458                                         anatop-reg-offset = <0x120>;
 459                                         anatop-vol-bit-shift = <8>;
 460                                         anatop-vol-bit-width = <5>;
 461                                         anatop-min-bit-val = <0>;
 462                                         anatop-min-voltage = <2625000>;
 463                                         anatop-max-voltage = <3400000>;
 464                                 };
 465
 466                                 regulator-2p5@130 {
 467                                         compatible = "fsl,anatop-regulator";
 468                                         regulator-name = "vdd2p5";
 469                                         regulator-min-microvolt = <2100000>;
 470                                         regulator-max-microvolt = <2850000>;
 471                                         regulator-always-on;
 472                                         anatop-reg-offset = <0x130>;
 473                                         anatop-vol-bit-shift = <8>;
 474                                         anatop-vol-bit-width = <5>;
 475                                         anatop-min-bit-val = <0>;
 476                                         anatop-min-voltage = <2100000>;
 477                                         anatop-max-voltage = <2850000>;
 478                                 };
 479
 480                                 reg_arm: regulator-vddcore@140 {
 481                                         compatible = "fsl,anatop-regulator";
 482                                         regulator-name = "vddarm";
 483                                         regulator-min-microvolt = <725000>;
 484                                         regulator-max-microvolt = <1450000>;
 485                                         regulator-always-on;
 486                                         anatop-reg-offset = <0x140>;
 487                                         anatop-vol-bit-shift = <0>;
 488                                         anatop-vol-bit-width = <5>;
 489                                         anatop-delay-reg-offset = <0x170>;
 490                                         anatop-delay-bit-shift = <24>;
 491                                         anatop-delay-bit-width = <2>;
 492                                         anatop-min-bit-val = <1>;
 493                                         anatop-min-voltage = <725000>;
 494                                         anatop-max-voltage = <1450000>;
 495                                 };
 496
 497                                 reg_pu: regulator-vddpu@140 {
 498                                         compatible = "fsl,anatop-regulator";
 499                                         regulator-name = "vddpu";
 500                                         regulator-min-microvolt = <725000>;
 501                                         regulator-max-microvolt = <1450000>;
 502                                         regulator-always-on;
 503                                         anatop-reg-offset = <0x140>;
 504                                         anatop-vol-bit-shift = <9>;
 505                                         anatop-vol-bit-width = <5>;
 506                                         anatop-delay-reg-offset = <0x170>;
 507                                         anatop-delay-bit-shift = <26>;
 508                                         anatop-delay-bit-width = <2>;
 509                                         anatop-min-bit-val = <1>;
 510                                         anatop-min-voltage = <725000>;
 511                                         anatop-max-voltage = <1450000>;
 512                                 };
 513
 514                                 reg_soc: regulator-vddsoc@140 {
 515                                         compatible = "fsl,anatop-regulator";
 516                                         regulator-name = "vddsoc";
 517                                         regulator-min-microvolt = <725000>;
 518                                         regulator-max-microvolt = <1450000>;
 519                                         regulator-always-on;
 520                                         anatop-reg-offset = <0x140>;
 521                                         anatop-vol-bit-shift = <18>;
 522                                         anatop-vol-bit-width = <5>;
 523                                         anatop-delay-reg-offset = <0x170>;
 524                                         anatop-delay-bit-shift = <28>;
 525                                         anatop-delay-bit-width = <2>;
 526                                         anatop-min-bit-val = <1>;
 527                                         anatop-min-voltage = <725000>;
 528                                         anatop-max-voltage = <1450000>;
 529                                 };
 530                         };
 531
 532                         usbphy1: usbphy@020c9000 {
 533                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 534                                 reg = <0x020c9000 0x1000>;
 535                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 536                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 537                                 fsl,anatop = <&anatop>;
 538                         };
 539
 540                         usbphy2: usbphy@020ca000 {
 541                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 542                                 reg = <0x020ca000 0x1000>;
 543                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 544                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 545                                 fsl,anatop = <&anatop>;
 546                         };
 547
 548                         snvs@020cc000 {
 549                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 550                                 #address-cells = <1>;
 551                                 #size-cells = <1>;
 552                                 ranges = <0 0x020cc000 0x4000>;
 553
 554                                 snvs-rtc-lp@34 {
 555                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 556                                         reg = <0x34 0x58>;
 557                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 558                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 559                                 };
 560                         };
 561
 562                         epit1: epit@020d0000 {
 563                                 reg = <0x020d0000 0x4000>;
 564                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 565                         };
 566
 567                         epit2: epit@020d4000 {
 568                                 reg = <0x020d4000 0x4000>;
 569                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 570                         };
 571
 572                         src: src@020d8000 {
 573                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 574                                 reg = <0x020d8000 0x4000>;
 575                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 576                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 577                                 #reset-cells = <1>;
 578                         };
 579
 580                         gpc: gpc@020dc000 {
 581                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 582                                 reg = <0x020dc000 0x4000>;
 583                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 584                         };
 585
 586                         gpr: iomuxc-gpr@020e0000 {
 587                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 588                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 589                                 reg = <0x020e0000 0x38>;
 590                         };
 591
 592                         iomuxc: iomuxc@020e0000 {
 593                                 compatible = "fsl,imx6sl-iomuxc";
 594                                 reg = <0x020e0000 0x4000>;
 595                         };
 596
 597                         csi: csi@020e4000 {
 598                                 reg = <0x020e4000 0x4000>;
 599                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 600                         };
 601
 602                         spdc: spdc@020e8000 {
 603                                 reg = <0x020e8000 0x4000>;
 604                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 605                         };
 606
 607                         sdma: sdma@020ec000 {
 608                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 609                                 reg = <0x020ec000 0x4000>;
 610                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 611                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 612                                          <&clks IMX6SL_CLK_SDMA>;
 613                                 clock-names = "ipg", "ahb";
 614                                 #dma-cells = <3>;
 615                                 /* imx6sl reuses imx6q sdma firmware */
 616                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 617                         };
 618
 619                         pxp: pxp@020f0000 {
 620                                 reg = <0x020f0000 0x4000>;
 621                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 622                         };
 623
 624                         epdc: epdc@020f4000 {
 625                                 reg = <0x020f4000 0x4000>;
 626                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 627                         };
 628
 629                         lcdif: lcdif@020f8000 {
 630                                 reg = <0x020f8000 0x4000>;
 631                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 632                         };
 633
 634                         dcp: dcp@020fc000 {
 635                                 reg = <0x020fc000 0x4000>;
 636                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
 637                         };
 638                 };
 639
 640                 aips2: aips-bus@02100000 {
 641                         compatible = "fsl,aips-bus", "simple-bus";
 642                         #address-cells = <1>;
 643                         #size-cells = <1>;
 644                         reg = <0x02100000 0x100000>;
 645                         ranges;
 646
 647                         usbotg1: usb@02184000 {
 648                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 649                                 reg = <0x02184000 0x200>;
 650                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 651                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 652                                 fsl,usbphy = <&usbphy1>;
 653                                 fsl,usbmisc = <&usbmisc 0>;
 654                                 status = "disabled";
 655                         };
 656
 657                         usbotg2: usb@02184200 {
 658                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 659                                 reg = <0x02184200 0x200>;
 660                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 661                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 662                                 fsl,usbphy = <&usbphy2>;
 663                                 fsl,usbmisc = <&usbmisc 1>;
 664                                 status = "disabled";
 665                         };
 666
 667                         usbh: usb@02184400 {
 668                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 669                                 reg = <0x02184400 0x200>;
 670                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 672                                 fsl,usbmisc = <&usbmisc 2>;
 673                                 status = "disabled";
 674                         };
 675
 676                         usbmisc: usbmisc@02184800 {
 677                                 #index-cells = <1>;
 678                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 679                                 reg = <0x02184800 0x200>;
 680                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 681                         };
 682
 683                         fec: ethernet@02188000 {
 684                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 685                                 reg = <0x02188000 0x4000>;
 686                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 687                                 clocks = <&clks IMX6SL_CLK_ENET>,
 688                                          <&clks IMX6SL_CLK_ENET_REF>;
 689                                 clock-names = "ipg", "ahb";
 690                                 status = "disabled";
 691                         };
 692
 693                         usdhc1: usdhc@02190000 {
 694                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 695                                 reg = <0x02190000 0x4000>;
 696                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 697                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 698                                          <&clks IMX6SL_CLK_USDHC1>,
 699                                          <&clks IMX6SL_CLK_USDHC1>;
 700                                 clock-names = "ipg", "ahb", "per";
 701                                 bus-width = <4>;
 702                                 status = "disabled";
 703                         };
 704
 705                         usdhc2: usdhc@02194000 {
 706                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 707                                 reg = <0x02194000 0x4000>;
 708                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 709                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 710                                          <&clks IMX6SL_CLK_USDHC2>,
 711                                          <&clks IMX6SL_CLK_USDHC2>;
 712                                 clock-names = "ipg", "ahb", "per";
 713                                 bus-width = <4>;
 714                                 status = "disabled";
 715                         };
 716
 717                         usdhc3: usdhc@02198000 {
 718                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 719                                 reg = <0x02198000 0x4000>;
 720                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 721                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 722                                          <&clks IMX6SL_CLK_USDHC3>,
 723                                          <&clks IMX6SL_CLK_USDHC3>;
 724                                 clock-names = "ipg", "ahb", "per";
 725                                 bus-width = <4>;
 726                                 status = "disabled";
 727                         };
 728
 729                         usdhc4: usdhc@0219c000 {
 730                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 731                                 reg = <0x0219c000 0x4000>;
 732                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 733                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 734                                          <&clks IMX6SL_CLK_USDHC4>,
 735                                          <&clks IMX6SL_CLK_USDHC4>;
 736                                 clock-names = "ipg", "ahb", "per";
 737                                 bus-width = <4>;
 738                                 status = "disabled";
 739                         };
 740
 741                         i2c1: i2c@021a0000 {
 742                                 #address-cells = <1>;
 743                                 #size-cells = <0>;
 744                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 745                                 reg = <0x021a0000 0x4000>;
 746                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 747                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 748                                 status = "disabled";
 749                         };
 750
 751                         i2c2: i2c@021a4000 {
 752                                 #address-cells = <1>;
 753                                 #size-cells = <0>;
 754                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 755                                 reg = <0x021a4000 0x4000>;
 756                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 758                                 status = "disabled";
 759                         };
 760
 761                         i2c3: i2c@021a8000 {
 762                                 #address-cells = <1>;
 763                                 #size-cells = <0>;
 764                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 765                                 reg = <0x021a8000 0x4000>;
 766                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 767                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 768                                 status = "disabled";
 769                         };
 770
 771                         mmdc: mmdc@021b0000 {
 772                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 773                                 reg = <0x021b0000 0x4000>;
 774                         };
 775
 776                         rngb: rngb@021b4000 {
 777                                 reg = <0x021b4000 0x4000>;
 778                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 779                         };
 780
 781                         weim: weim@021b8000 {
 782                                 reg = <0x021b8000 0x4000>;
 783                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 784                         };
 785
 786                         ocotp: ocotp@021bc000 {
 787                                 compatible = "fsl,imx6sl-ocotp";
 788                                 reg = <0x021bc000 0x4000>;
 789                         };
 790
 791                         audmux: audmux@021d8000 {
 792                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 793                                 reg = <0x021d8000 0x4000>;
 794                                 status = "disabled";
 795                         };
 796                 };
 797         };
 798 };