arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 gpio5 = &gpio6;
  23                 gpio6 = &gpio7;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 spi0 = &ecspi1;
  33                 spi1 = &ecspi2;
  34                 spi2 = &ecspi3;
  35                 spi3 = &ecspi4;
  36         };
  37
  38         intc: interrupt-controller@00a01000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 interrupt-controller;
  44                 reg = <0x00a01000 0x1000>,
  45                       <0x00a00100 0x100>;
  46         };
  47
  48         clocks {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 ckil {
  53                         compatible = "fsl,imx-ckil", "fixed-clock";
  54                         clock-frequency = <32768>;
  55                 };
  56
  57                 ckih1 {
  58                         compatible = "fsl,imx-ckih1", "fixed-clock";
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 osc {
  63                         compatible = "fsl,imx-osc", "fixed-clock";
  64                         clock-frequency = <24000000>;
  65                 };
  66         };
  67
  68         soc {
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&intc>;
  73                 ranges;
  74
  75                 dma_apbh: dma-apbh@00110000 {
  76                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  77                         reg = <0x00110000 0x2000>;
  78                         interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
  79                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  80                         #dma-cells = <1>;
  81                         dma-channels = <4>;
  82                         clocks = <&clks 106>;
  83                 };
  84
  85                 gpmi: gpmi-nand@00112000 {
  86                         compatible = "fsl,imx6q-gpmi-nand";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  90                         reg-names = "gpmi-nand", "bch";
  91                         interrupts = <0 13 0x04>, <0 15 0x04>;
  92                         interrupt-names = "gpmi-dma", "bch";
  93                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  94                                  <&clks 150>, <&clks 149>;
  95                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  96                                       "gpmi_bch_apb", "per1_bch";
  97                         dmas = <&dma_apbh 0>;
  98                         dma-names = "rx-tx";
  99                         fsl,gpmi-dma-channel = <0>;
 100                         status = "disabled";
 101                 };
 102
 103                 ocram: sram@00900000 {
 104                         compatible = "mmio-sram";
 105                         reg = <0x00900000 0x3f000>;
 106                         clocks = <&clks 142>;
 107                 };
 108
 109                 timer@00a00600 {
 110                         compatible = "arm,cortex-a9-twd-timer";
 111                         reg = <0x00a00600 0x20>;
 112                         interrupts = <1 13 0xf01>;
 113                         clocks = <&clks 15>;
 114                 };
 115
 116                 L2: l2-cache@00a02000 {
 117                         compatible = "arm,pl310-cache";
 118                         reg = <0x00a02000 0x1000>;
 119                         interrupts = <0 92 0x04>;
 120                         cache-unified;
 121                         cache-level = <2>;
 122                         arm,tag-latency = <4 2 3>;
 123                         arm,data-latency = <4 2 3>;
 124                 };
 125
 126                 pmu {
 127                         compatible = "arm,cortex-a9-pmu";
 128                         interrupts = <0 94 0x04>;
 129                 };
 130
 131                 aips-bus@02000000 { /* AIPS1 */
 132                         compatible = "fsl,aips-bus", "simple-bus";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         reg = <0x02000000 0x100000>;
 136                         ranges;
 137
 138                         spba-bus@02000000 {
 139                                 compatible = "fsl,spba-bus", "simple-bus";
 140                                 #address-cells = <1>;
 141                                 #size-cells = <1>;
 142                                 reg = <0x02000000 0x40000>;
 143                                 ranges;
 144
 145                                 spdif: spdif@02004000 {
 146                                         reg = <0x02004000 0x4000>;
 147                                         interrupts = <0 52 0x04>;
 148                                 };
 149
 150                                 ecspi1: ecspi@02008000 {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 154                                         reg = <0x02008000 0x4000>;
 155                                         interrupts = <0 31 0x04>;
 156                                         clocks = <&clks 112>, <&clks 112>;
 157                                         clock-names = "ipg", "per";
 158                                         status = "disabled";
 159                                 };
 160
 161                                 ecspi2: ecspi@0200c000 {
 162                                         #address-cells = <1>;
 163                                         #size-cells = <0>;
 164                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 165                                         reg = <0x0200c000 0x4000>;
 166                                         interrupts = <0 32 0x04>;
 167                                         clocks = <&clks 113>, <&clks 113>;
 168                                         clock-names = "ipg", "per";
 169                                         status = "disabled";
 170                                 };
 171
 172                                 ecspi3: ecspi@02010000 {
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 176                                         reg = <0x02010000 0x4000>;
 177                                         interrupts = <0 33 0x04>;
 178                                         clocks = <&clks 114>, <&clks 114>;
 179                                         clock-names = "ipg", "per";
 180                                         status = "disabled";
 181                                 };
 182
 183                                 ecspi4: ecspi@02014000 {
 184                                         #address-cells = <1>;
 185                                         #size-cells = <0>;
 186                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 187                                         reg = <0x02014000 0x4000>;
 188                                         interrupts = <0 34 0x04>;
 189                                         clocks = <&clks 115>, <&clks 115>;
 190                                         clock-names = "ipg", "per";
 191                                         status = "disabled";
 192                                 };
 193
 194                                 uart1: serial@02020000 {
 195                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 196                                         reg = <0x02020000 0x4000>;
 197                                         interrupts = <0 26 0x04>;
 198                                         clocks = <&clks 160>, <&clks 161>;
 199                                         clock-names = "ipg", "per";
 200                                         status = "disabled";
 201                                 };
 202
 203                                 esai: esai@02024000 {
 204                                         reg = <0x02024000 0x4000>;
 205                                         interrupts = <0 51 0x04>;
 206                                 };
 207
 208                                 ssi1: ssi@02028000 {
 209                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 210                                         reg = <0x02028000 0x4000>;
 211                                         interrupts = <0 46 0x04>;
 212                                         clocks = <&clks 178>;
 213                                         fsl,fifo-depth = <15>;
 214                                         fsl,ssi-dma-events = <38 37>;
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ssi2: ssi@0202c000 {
 219                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 220                                         reg = <0x0202c000 0x4000>;
 221                                         interrupts = <0 47 0x04>;
 222                                         clocks = <&clks 179>;
 223                                         fsl,fifo-depth = <15>;
 224                                         fsl,ssi-dma-events = <42 41>;
 225                                         status = "disabled";
 226                                 };
 227
 228                                 ssi3: ssi@02030000 {
 229                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 230                                         reg = <0x02030000 0x4000>;
 231                                         interrupts = <0 48 0x04>;
 232                                         clocks = <&clks 180>;
 233                                         fsl,fifo-depth = <15>;
 234                                         fsl,ssi-dma-events = <46 45>;
 235                                         status = "disabled";
 236                                 };
 237
 238                                 asrc: asrc@02034000 {
 239                                         reg = <0x02034000 0x4000>;
 240                                         interrupts = <0 50 0x04>;
 241                                 };
 242
 243                                 spba@0203c000 {
 244                                         reg = <0x0203c000 0x4000>;
 245                                 };
 246                         };
 247
 248                         vpu: vpu@02040000 {
 249                                 reg = <0x02040000 0x3c000>;
 250                                 interrupts = <0 3 0x04 0 12 0x04>;
 251                         };
 252
 253                         aipstz@0207c000 { /* AIPSTZ1 */
 254                                 reg = <0x0207c000 0x4000>;
 255                         };
 256
 257                         pwm1: pwm@02080000 {
 258                                 #pwm-cells = <2>;
 259                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 260                                 reg = <0x02080000 0x4000>;
 261                                 interrupts = <0 83 0x04>;
 262                                 clocks = <&clks 62>, <&clks 145>;
 263                                 clock-names = "ipg", "per";
 264                         };
 265
 266                         pwm2: pwm@02084000 {
 267                                 #pwm-cells = <2>;
 268                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 269                                 reg = <0x02084000 0x4000>;
 270                                 interrupts = <0 84 0x04>;
 271                                 clocks = <&clks 62>, <&clks 146>;
 272                                 clock-names = "ipg", "per";
 273                         };
 274
 275                         pwm3: pwm@02088000 {
 276                                 #pwm-cells = <2>;
 277                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 278                                 reg = <0x02088000 0x4000>;
 279                                 interrupts = <0 85 0x04>;
 280                                 clocks = <&clks 62>, <&clks 147>;
 281                                 clock-names = "ipg", "per";
 282                         };
 283
 284                         pwm4: pwm@0208c000 {
 285                                 #pwm-cells = <2>;
 286                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 287                                 reg = <0x0208c000 0x4000>;
 288                                 interrupts = <0 86 0x04>;
 289                                 clocks = <&clks 62>, <&clks 148>;
 290                                 clock-names = "ipg", "per";
 291                         };
 292
 293                         can1: flexcan@02090000 {
 294                                 compatible = "fsl,imx6q-flexcan";
 295                                 reg = <0x02090000 0x4000>;
 296                                 interrupts = <0 110 0x04>;
 297                                 clocks = <&clks 108>, <&clks 109>;
 298                                 clock-names = "ipg", "per";
 299                         };
 300
 301                         can2: flexcan@02094000 {
 302                                 compatible = "fsl,imx6q-flexcan";
 303                                 reg = <0x02094000 0x4000>;
 304                                 interrupts = <0 111 0x04>;
 305                                 clocks = <&clks 110>, <&clks 111>;
 306                                 clock-names = "ipg", "per";
 307                         };
 308
 309                         gpt: gpt@02098000 {
 310                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 311                                 reg = <0x02098000 0x4000>;
 312                                 interrupts = <0 55 0x04>;
 313                                 clocks = <&clks 119>, <&clks 120>;
 314                                 clock-names = "ipg", "per";
 315                         };
 316
 317                         gpio1: gpio@0209c000 {
 318                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 319                                 reg = <0x0209c000 0x4000>;
 320                                 interrupts = <0 66 0x04 0 67 0x04>;
 321                                 gpio-controller;
 322                                 #gpio-cells = <2>;
 323                                 interrupt-controller;
 324                                 #interrupt-cells = <2>;
 325                         };
 326
 327                         gpio2: gpio@020a0000 {
 328                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 329                                 reg = <0x020a0000 0x4000>;
 330                                 interrupts = <0 68 0x04 0 69 0x04>;
 331                                 gpio-controller;
 332                                 #gpio-cells = <2>;
 333                                 interrupt-controller;
 334                                 #interrupt-cells = <2>;
 335                         };
 336
 337                         gpio3: gpio@020a4000 {
 338                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 339                                 reg = <0x020a4000 0x4000>;
 340                                 interrupts = <0 70 0x04 0 71 0x04>;
 341                                 gpio-controller;
 342                                 #gpio-cells = <2>;
 343                                 interrupt-controller;
 344                                 #interrupt-cells = <2>;
 345                         };
 346
 347                         gpio4: gpio@020a8000 {
 348                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 349                                 reg = <0x020a8000 0x4000>;
 350                                 interrupts = <0 72 0x04 0 73 0x04>;
 351                                 gpio-controller;
 352                                 #gpio-cells = <2>;
 353                                 interrupt-controller;
 354                                 #interrupt-cells = <2>;
 355                         };
 356
 357                         gpio5: gpio@020ac000 {
 358                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 359                                 reg = <0x020ac000 0x4000>;
 360                                 interrupts = <0 74 0x04 0 75 0x04>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                         };
 366
 367                         gpio6: gpio@020b0000 {
 368                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 369                                 reg = <0x020b0000 0x4000>;
 370                                 interrupts = <0 76 0x04 0 77 0x04>;
 371                                 gpio-controller;
 372                                 #gpio-cells = <2>;
 373                                 interrupt-controller;
 374                                 #interrupt-cells = <2>;
 375                         };
 376
 377                         gpio7: gpio@020b4000 {
 378                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 379                                 reg = <0x020b4000 0x4000>;
 380                                 interrupts = <0 78 0x04 0 79 0x04>;
 381                                 gpio-controller;
 382                                 #gpio-cells = <2>;
 383                                 interrupt-controller;
 384                                 #interrupt-cells = <2>;
 385                         };
 386
 387                         kpp: kpp@020b8000 {
 388                                 reg = <0x020b8000 0x4000>;
 389                                 interrupts = <0 82 0x04>;
 390                         };
 391
 392                         wdog1: wdog@020bc000 {
 393                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 394                                 reg = <0x020bc000 0x4000>;
 395                                 interrupts = <0 80 0x04>;
 396                                 clocks = <&clks 0>;
 397                         };
 398
 399                         wdog2: wdog@020c0000 {
 400                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 401                                 reg = <0x020c0000 0x4000>;
 402                                 interrupts = <0 81 0x04>;
 403                                 clocks = <&clks 0>;
 404                                 status = "disabled";
 405                         };
 406
 407                         clks: ccm@020c4000 {
 408                                 compatible = "fsl,imx6q-ccm";
 409                                 reg = <0x020c4000 0x4000>;
 410                                 interrupts = <0 87 0x04 0 88 0x04>;
 411                                 #clock-cells = <1>;
 412                         };
 413
 414                         anatop: anatop@020c8000 {
 415                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 416                                 reg = <0x020c8000 0x1000>;
 417                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 418
 419                                 regulator-1p1@110 {
 420                                         compatible = "fsl,anatop-regulator";
 421                                         regulator-name = "vdd1p1";
 422                                         regulator-min-microvolt = <800000>;
 423                                         regulator-max-microvolt = <1375000>;
 424                                         regulator-always-on;
 425                                         anatop-reg-offset = <0x110>;
 426                                         anatop-vol-bit-shift = <8>;
 427                                         anatop-vol-bit-width = <5>;
 428                                         anatop-min-bit-val = <4>;
 429                                         anatop-min-voltage = <800000>;
 430                                         anatop-max-voltage = <1375000>;
 431                                 };
 432
 433                                 regulator-3p0@120 {
 434                                         compatible = "fsl,anatop-regulator";
 435                                         regulator-name = "vdd3p0";
 436                                         regulator-min-microvolt = <2800000>;
 437                                         regulator-max-microvolt = <3150000>;
 438                                         regulator-always-on;
 439                                         anatop-reg-offset = <0x120>;
 440                                         anatop-vol-bit-shift = <8>;
 441                                         anatop-vol-bit-width = <5>;
 442                                         anatop-min-bit-val = <0>;
 443                                         anatop-min-voltage = <2625000>;
 444                                         anatop-max-voltage = <3400000>;
 445                                 };
 446
 447                                 regulator-2p5@130 {
 448                                         compatible = "fsl,anatop-regulator";
 449                                         regulator-name = "vdd2p5";
 450                                         regulator-min-microvolt = <2000000>;
 451                                         regulator-max-microvolt = <2750000>;
 452                                         regulator-always-on;
 453                                         anatop-reg-offset = <0x130>;
 454                                         anatop-vol-bit-shift = <8>;
 455                                         anatop-vol-bit-width = <5>;
 456                                         anatop-min-bit-val = <0>;
 457                                         anatop-min-voltage = <2000000>;
 458                                         anatop-max-voltage = <2750000>;
 459                                 };
 460
 461                                 reg_arm: regulator-vddcore@140 {
 462                                         compatible = "fsl,anatop-regulator";
 463                                         regulator-name = "cpu";
 464                                         regulator-min-microvolt = <725000>;
 465                                         regulator-max-microvolt = <1450000>;
 466                                         regulator-always-on;
 467                                         anatop-reg-offset = <0x140>;
 468                                         anatop-vol-bit-shift = <0>;
 469                                         anatop-vol-bit-width = <5>;
 470                                         anatop-delay-reg-offset = <0x170>;
 471                                         anatop-delay-bit-shift = <24>;
 472                                         anatop-delay-bit-width = <2>;
 473                                         anatop-min-bit-val = <1>;
 474                                         anatop-min-voltage = <725000>;
 475                                         anatop-max-voltage = <1450000>;
 476                                 };
 477
 478                                 reg_pu: regulator-vddpu@140 {
 479                                         compatible = "fsl,anatop-regulator";
 480                                         regulator-name = "vddpu";
 481                                         regulator-min-microvolt = <725000>;
 482                                         regulator-max-microvolt = <1450000>;
 483                                         regulator-always-on;
 484                                         anatop-reg-offset = <0x140>;
 485                                         anatop-vol-bit-shift = <9>;
 486                                         anatop-vol-bit-width = <5>;
 487                                         anatop-delay-reg-offset = <0x170>;
 488                                         anatop-delay-bit-shift = <26>;
 489                                         anatop-delay-bit-width = <2>;
 490                                         anatop-min-bit-val = <1>;
 491                                         anatop-min-voltage = <725000>;
 492                                         anatop-max-voltage = <1450000>;
 493                                 };
 494
 495                                 reg_soc: regulator-vddsoc@140 {
 496                                         compatible = "fsl,anatop-regulator";
 497                                         regulator-name = "vddsoc";
 498                                         regulator-min-microvolt = <725000>;
 499                                         regulator-max-microvolt = <1450000>;
 500                                         regulator-always-on;
 501                                         anatop-reg-offset = <0x140>;
 502                                         anatop-vol-bit-shift = <18>;
 503                                         anatop-vol-bit-width = <5>;
 504                                         anatop-delay-reg-offset = <0x170>;
 505                                         anatop-delay-bit-shift = <28>;
 506                                         anatop-delay-bit-width = <2>;
 507                                         anatop-min-bit-val = <1>;
 508                                         anatop-min-voltage = <725000>;
 509                                         anatop-max-voltage = <1450000>;
 510                                 };
 511                         };
 512
 513                         usbphy1: usbphy@020c9000 {
 514                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 515                                 reg = <0x020c9000 0x1000>;
 516                                 interrupts = <0 44 0x04>;
 517                                 clocks = <&clks 182>;
 518                         };
 519
 520                         usbphy2: usbphy@020ca000 {
 521                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 522                                 reg = <0x020ca000 0x1000>;
 523                                 interrupts = <0 45 0x04>;
 524                                 clocks = <&clks 183>;
 525                         };
 526
 527                         snvs@020cc000 {
 528                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 529                                 #address-cells = <1>;
 530                                 #size-cells = <1>;
 531                                 ranges = <0 0x020cc000 0x4000>;
 532
 533                                 snvs-rtc-lp@34 {
 534                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 535                                         reg = <0x34 0x58>;
 536                                         interrupts = <0 19 0x04 0 20 0x04>;
 537                                 };
 538                         };
 539
 540                         epit1: epit@020d0000 { /* EPIT1 */
 541                                 reg = <0x020d0000 0x4000>;
 542                                 interrupts = <0 56 0x04>;
 543                         };
 544
 545                         epit2: epit@020d4000 { /* EPIT2 */
 546                                 reg = <0x020d4000 0x4000>;
 547                                 interrupts = <0 57 0x04>;
 548                         };
 549
 550                         src: src@020d8000 {
 551                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 552                                 reg = <0x020d8000 0x4000>;
 553                                 interrupts = <0 91 0x04 0 96 0x04>;
 554                                 #reset-cells = <1>;
 555                         };
 556
 557                         gpc: gpc@020dc000 {
 558                                 compatible = "fsl,imx6q-gpc";
 559                                 reg = <0x020dc000 0x4000>;
 560                                 interrupts = <0 89 0x04 0 90 0x04>;
 561                         };
 562
 563                         gpr: iomuxc-gpr@020e0000 {
 564                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 565                                 reg = <0x020e0000 0x38>;
 566                         };
 567
 568                         iomuxc: iomuxc@020e0000 {
 569                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 570                                 reg = <0x020e0000 0x4000>;
 571
 572                                 audmux {
 573                                         pinctrl_audmux_1: audmux-1 {
 574                                                 fsl,pins = <
 575                                                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
 576                                                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
 577                                                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
 578                                                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
 579                                                 >;
 580                                         };
 581
 582                                         pinctrl_audmux_2: audmux-2 {
 583                                                 fsl,pins = <
 584                                                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
 585                                                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
 586                                                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
 587                                                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
 588                                                 >;
 589                                         };
 590                                 };
 591
 592                                 ecspi1 {
 593                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 594                                                 fsl,pins = <
 595                                                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 596                                                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 597                                                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 598                                                 >;
 599                                         };
 600
 601                                         pinctrl_ecspi1_2: ecspi1grp-2 {
 602                                                 fsl,pins = <
 603                                                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
 604                                                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
 605                                                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
 606                                                 >;
 607                                         };
 608                                 };
 609
 610                                 ecspi3 {
 611                                         pinctrl_ecspi3_1: ecspi3grp-1 {
 612                                                 fsl,pins = <
 613                                                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
 614                                                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
 615                                                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
 616                                                 >;
 617                                         };
 618                                 };
 619
 620                                 enet {
 621                                         pinctrl_enet_1: enetgrp-1 {
 622                                                 fsl,pins = <
 623                                                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 624                                                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 625                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 626                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 627                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 628                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 629                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 630                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 631                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 632                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 633                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 634                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 635                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 636                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 637                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 638                                                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 639                                                 >;
 640                                         };
 641
 642                                         pinctrl_enet_2: enetgrp-2 {
 643                                                 fsl,pins = <
 644                                                         MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
 645                                                         MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
 646                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 647                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 648                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 649                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 650                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 651                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 652                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 653                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 654                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 655                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 656                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 657                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 658                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 659                                                 >;
 660                                         };
 661
 662                                         pinctrl_enet_3: enetgrp-3 {
 663                                                 fsl,pins = <
 664                                                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 665                                                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 666                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 667                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 668                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 669                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 670                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 671                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 672                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 673                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 674                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 675                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 676                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 677                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 678                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 679                                                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 680                                                 >;
 681                                         };
 682                                 };
 683
 684                                 gpmi-nand {
 685                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 686                                                 fsl,pins = <
 687                                                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 688                                                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 689                                                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 690                                                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 691                                                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 692                                                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 693                                                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 694                                                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 695                                                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 696                                                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 697                                                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 698                                                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 699                                                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 700                                                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 701                                                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 702                                                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 703                                                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 704                                                 >;
 705                                         };
 706                                 };
 707
 708                                 i2c1 {
 709                                         pinctrl_i2c1_1: i2c1grp-1 {
 710                                                 fsl,pins = <
 711                                                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 712                                                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 713                                                 >;
 714                                         };
 715
 716                                         pinctrl_i2c1_2: i2c1grp-2 {
 717                                                 fsl,pins = <
 718                                                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 719                                                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 720                                                 >;
 721                                         };
 722                                 };
 723
 724                                 i2c2 {
 725                                         pinctrl_i2c2_1: i2c2grp-1 {
 726                                                 fsl,pins = <
 727                                                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 728                                                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 729                                                 >;
 730                                         };
 731
 732                                         pinctrl_i2c2_2: i2c2grp-2 {
 733                                                 fsl,pins = <
 734                                                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 735                                                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 736                                                 >;
 737                                         };
 738                                 };
 739
 740                                 i2c3 {
 741                                         pinctrl_i2c3_1: i2c3grp-1 {
 742                                                 fsl,pins = <
 743                                                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 744                                                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 745                                                 >;
 746                                         };
 747                                 };
 748
 749                                 uart1 {
 750                                         pinctrl_uart1_1: uart1grp-1 {
 751                                                 fsl,pins = <
 752                                                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 753                                                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 754                                                 >;
 755                                         };
 756                                 };
 757
 758                                 uart2 {
 759                                         pinctrl_uart2_1: uart2grp-1 {
 760                                                 fsl,pins = <
 761                                                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
 762                                                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
 763                                                 >;
 764                                         };
 765
 766                                         pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
 767                                                 fsl,pins = <
 768                                                         MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
 769                                                         MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
 770                                                         MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
 771                                                         MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
 772                                                 >;
 773                                         };
 774                                 };
 775
 776                                 uart4 {
 777                                         pinctrl_uart4_1: uart4grp-1 {
 778                                                 fsl,pins = <
 779                                                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 780                                                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 781                                                 >;
 782                                         };
 783                                 };
 784
 785                                 usbotg {
 786                                         pinctrl_usbotg_1: usbotggrp-1 {
 787                                                 fsl,pins = <
 788                                                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
 789                                                 >;
 790                                         };
 791
 792                                         pinctrl_usbotg_2: usbotggrp-2 {
 793                                                 fsl,pins = <
 794                                                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 795                                                 >;
 796                                         };
 797                                 };
 798
 799                                 usdhc2 {
 800                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 801                                                 fsl,pins = <
 802                                                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
 803                                                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
 804                                                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 805                                                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 806                                                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 807                                                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 808                                                         MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
 809                                                         MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
 810                                                         MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
 811                                                         MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
 812                                                 >;
 813                                         };
 814
 815                                         pinctrl_usdhc2_2: usdhc2grp-2 {
 816                                                 fsl,pins = <
 817                                                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
 818                                                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
 819                                                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 820                                                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 821                                                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 822                                                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 823                                                 >;
 824                                         };
 825                                 };
 826
 827                                 usdhc3 {
 828                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 829                                                 fsl,pins = <
 830                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 831                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 832                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 833                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 834                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 835                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 836                                                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 837                                                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 838                                                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 839                                                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 840                                                 >;
 841                                         };
 842
 843                                         pinctrl_usdhc3_2: usdhc3grp-2 {
 844                                                 fsl,pins = <
 845                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 846                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 847                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 848                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 849                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 850                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 851                                                 >;
 852                                         };
 853                                 };
 854
 855                                 usdhc4 {
 856                                         pinctrl_usdhc4_1: usdhc4grp-1 {
 857                                                 fsl,pins = <
 858                                                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
 859                                                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
 860                                                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
 861                                                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
 862                                                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
 863                                                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
 864                                                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
 865                                                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
 866                                                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
 867                                                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
 868                                                 >;
 869                                         };
 870
 871                                         pinctrl_usdhc4_2: usdhc4grp-2 {
 872                                                 fsl,pins = <
 873                                                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
 874                                                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
 875                                                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
 876                                                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
 877                                                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
 878                                                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
 879                                                 >;
 880                                         };
 881                                 };
 882
 883                                 weim {
 884                                         pinctrl_weim_cs0_1: weim_cs0grp-1 {
 885                                                 fsl,pins = <
 886                                                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 887                                                 >;
 888                                         };
 889
 890                                         pinctrl_weim_nor_1: weim_norgrp-1 {
 891                                                 fsl,pins = <
 892                                                         MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
 893                                                         MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
 894                                                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
 895                                                         /* data */
 896                                                         MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
 897                                                         MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
 898                                                         MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
 899                                                         MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
 900                                                         MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
 901                                                         MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
 902                                                         MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
 903                                                         MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
 904                                                         MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
 905                                                         MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
 906                                                         MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
 907                                                         MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
 908                                                         MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
 909                                                         MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
 910                                                         MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
 911                                                         MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
 912                                                         /* address */
 913                                                         MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
 914                                                         MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
 915                                                         MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
 916                                                         MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
 917                                                         MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
 918                                                         MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
 919                                                         MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
 920                                                         MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
 921                                                         MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
 922                                                         MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
 923                                                         MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
 924                                                         MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
 925                                                         MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
 926                                                         MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
 927                                                         MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
 928                                                         MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
 929                                                         MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
 930                                                         MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
 931                                                         MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
 932                                                         MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
 933                                                         MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
 934                                                         MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
 935                                                         MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
 936                                                         MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
 937                                                 >;
 938                                         };
 939                                 };
 940                         };
 941
 942                         ldb: ldb@020e0008 {
 943                                 #address-cells = <1>;
 944                                 #size-cells = <0>;
 945                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 946                                 gpr = <&gpr>;
 947                                 status = "disabled";
 948
 949                                 lvds-channel@0 {
 950                                         reg = <0>;
 951                                         status = "disabled";
 952                                 };
 953
 954                                 lvds-channel@1 {
 955                                         reg = <1>;
 956                                         status = "disabled";
 957                                 };
 958                         };
 959
 960                         dcic1: dcic@020e4000 {
 961                                 reg = <0x020e4000 0x4000>;
 962                                 interrupts = <0 124 0x04>;
 963                         };
 964
 965                         dcic2: dcic@020e8000 {
 966                                 reg = <0x020e8000 0x4000>;
 967                                 interrupts = <0 125 0x04>;
 968                         };
 969
 970                         sdma: sdma@020ec000 {
 971                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 972                                 reg = <0x020ec000 0x4000>;
 973                                 interrupts = <0 2 0x04>;
 974                                 clocks = <&clks 155>, <&clks 155>;
 975                                 clock-names = "ipg", "ahb";
 976                                 #dma-cells = <3>;
 977                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 978                         };
 979                 };
 980
 981                 aips-bus@02100000 { /* AIPS2 */
 982                         compatible = "fsl,aips-bus", "simple-bus";
 983                         #address-cells = <1>;
 984                         #size-cells = <1>;
 985                         reg = <0x02100000 0x100000>;
 986                         ranges;
 987
 988                         caam@02100000 {
 989                                 reg = <0x02100000 0x40000>;
 990                                 interrupts = <0 105 0x04 0 106 0x04>;
 991                         };
 992
 993                         aipstz@0217c000 { /* AIPSTZ2 */
 994                                 reg = <0x0217c000 0x4000>;
 995                         };
 996
 997                         usbotg: usb@02184000 {
 998                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 999                                 reg = <0x02184000 0x200>;
1000                                 interrupts = <0 43 0x04>;
1001                                 clocks = <&clks 162>;
1002                                 fsl,usbphy = <&usbphy1>;
1003                                 fsl,usbmisc = <&usbmisc 0>;
1004                                 status = "disabled";
1005                         };
1006
1007                         usbh1: usb@02184200 {
1008                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1009                                 reg = <0x02184200 0x200>;
1010                                 interrupts = <0 40 0x04>;
1011                                 clocks = <&clks 162>;
1012                                 fsl,usbphy = <&usbphy2>;
1013                                 fsl,usbmisc = <&usbmisc 1>;
1014                                 status = "disabled";
1015                         };
1016
1017                         usbh2: usb@02184400 {
1018                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1019                                 reg = <0x02184400 0x200>;
1020                                 interrupts = <0 41 0x04>;
1021                                 clocks = <&clks 162>;
1022                                 fsl,usbmisc = <&usbmisc 2>;
1023                                 status = "disabled";
1024                         };
1025
1026                         usbh3: usb@02184600 {
1027                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1028                                 reg = <0x02184600 0x200>;
1029                                 interrupts = <0 42 0x04>;
1030                                 clocks = <&clks 162>;
1031                                 fsl,usbmisc = <&usbmisc 3>;
1032                                 status = "disabled";
1033                         };
1034
1035                         usbmisc: usbmisc@02184800 {
1036                                 #index-cells = <1>;
1037                                 compatible = "fsl,imx6q-usbmisc";
1038                                 reg = <0x02184800 0x200>;
1039                                 clocks = <&clks 162>;
1040                         };
1041
1042                         fec: ethernet@02188000 {
1043                                 compatible = "fsl,imx6q-fec";
1044                                 reg = <0x02188000 0x4000>;
1045                                 interrupts = <0 118 0x04 0 119 0x04>;
1046                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1047                                 clock-names = "ipg", "ahb", "ptp";
1048                                 status = "disabled";
1049                         };
1050
1051                         mlb@0218c000 {
1052                                 reg = <0x0218c000 0x4000>;
1053                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1054                         };
1055
1056                         usdhc1: usdhc@02190000 {
1057                                 compatible = "fsl,imx6q-usdhc";
1058                                 reg = <0x02190000 0x4000>;
1059                                 interrupts = <0 22 0x04>;
1060                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1061                                 clock-names = "ipg", "ahb", "per";
1062                                 bus-width = <4>;
1063                                 status = "disabled";
1064                         };
1065
1066                         usdhc2: usdhc@02194000 {
1067                                 compatible = "fsl,imx6q-usdhc";
1068                                 reg = <0x02194000 0x4000>;
1069                                 interrupts = <0 23 0x04>;
1070                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1071                                 clock-names = "ipg", "ahb", "per";
1072                                 bus-width = <4>;
1073                                 status = "disabled";
1074                         };
1075
1076                         usdhc3: usdhc@02198000 {
1077                                 compatible = "fsl,imx6q-usdhc";
1078                                 reg = <0x02198000 0x4000>;
1079                                 interrupts = <0 24 0x04>;
1080                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1081                                 clock-names = "ipg", "ahb", "per";
1082                                 bus-width = <4>;
1083                                 status = "disabled";
1084                         };
1085
1086                         usdhc4: usdhc@0219c000 {
1087                                 compatible = "fsl,imx6q-usdhc";
1088                                 reg = <0x0219c000 0x4000>;
1089                                 interrupts = <0 25 0x04>;
1090                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1091                                 clock-names = "ipg", "ahb", "per";
1092                                 bus-width = <4>;
1093                                 status = "disabled";
1094                         };
1095
1096                         i2c1: i2c@021a0000 {
1097                                 #address-cells = <1>;
1098                                 #size-cells = <0>;
1099                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1100                                 reg = <0x021a0000 0x4000>;
1101                                 interrupts = <0 36 0x04>;
1102                                 clocks = <&clks 125>;
1103                                 status = "disabled";
1104                         };
1105
1106                         i2c2: i2c@021a4000 {
1107                                 #address-cells = <1>;
1108                                 #size-cells = <0>;
1109                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1110                                 reg = <0x021a4000 0x4000>;
1111                                 interrupts = <0 37 0x04>;
1112                                 clocks = <&clks 126>;
1113                                 status = "disabled";
1114                         };
1115
1116                         i2c3: i2c@021a8000 {
1117                                 #address-cells = <1>;
1118                                 #size-cells = <0>;
1119                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1120                                 reg = <0x021a8000 0x4000>;
1121                                 interrupts = <0 38 0x04>;
1122                                 clocks = <&clks 127>;
1123                                 status = "disabled";
1124                         };
1125
1126                         romcp@021ac000 {
1127                                 reg = <0x021ac000 0x4000>;
1128                         };
1129
1130                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1131                                 compatible = "fsl,imx6q-mmdc";
1132                                 reg = <0x021b0000 0x4000>;
1133                         };
1134
1135                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1136                                 reg = <0x021b4000 0x4000>;
1137                         };
1138
1139                         weim: weim@021b8000 {
1140                                 compatible = "fsl,imx6q-weim";
1141                                 reg = <0x021b8000 0x4000>;
1142                                 interrupts = <0 14 0x04>;
1143                                 clocks = <&clks 196>;
1144                         };
1145
1146                         ocotp@021bc000 {
1147                                 compatible = "fsl,imx6q-ocotp";
1148                                 reg = <0x021bc000 0x4000>;
1149                         };
1150
1151                         tzasc@021d0000 { /* TZASC1 */
1152                                 reg = <0x021d0000 0x4000>;
1153                                 interrupts = <0 108 0x04>;
1154                         };
1155
1156                         tzasc@021d4000 { /* TZASC2 */
1157                                 reg = <0x021d4000 0x4000>;
1158                                 interrupts = <0 109 0x04>;
1159                         };
1160
1161                         audmux: audmux@021d8000 {
1162                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1163                                 reg = <0x021d8000 0x4000>;
1164                                 status = "disabled";
1165                         };
1166
1167                         mipi@021dc000 { /* MIPI-CSI */
1168                                 reg = <0x021dc000 0x4000>;
1169                         };
1170
1171                         mipi@021e0000 { /* MIPI-DSI */
1172                                 reg = <0x021e0000 0x4000>;
1173                         };
1174
1175                         vdoa@021e4000 {
1176                                 reg = <0x021e4000 0x4000>;
1177                                 interrupts = <0 18 0x04>;
1178                         };
1179
1180                         uart2: serial@021e8000 {
1181                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1182                                 reg = <0x021e8000 0x4000>;
1183                                 interrupts = <0 27 0x04>;
1184                                 clocks = <&clks 160>, <&clks 161>;
1185                                 clock-names = "ipg", "per";
1186                                 status = "disabled";
1187                         };
1188
1189                         uart3: serial@021ec000 {
1190                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1191                                 reg = <0x021ec000 0x4000>;
1192                                 interrupts = <0 28 0x04>;
1193                                 clocks = <&clks 160>, <&clks 161>;
1194                                 clock-names = "ipg", "per";
1195                                 status = "disabled";
1196                         };
1197
1198                         uart4: serial@021f0000 {
1199                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1200                                 reg = <0x021f0000 0x4000>;
1201                                 interrupts = <0 29 0x04>;
1202                                 clocks = <&clks 160>, <&clks 161>;
1203                                 clock-names = "ipg", "per";
1204                                 status = "disabled";
1205                         };
1206
1207                         uart5: serial@021f4000 {
1208                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1209                                 reg = <0x021f4000 0x4000>;
1210                                 interrupts = <0 30 0x04>;
1211                                 clocks = <&clks 160>, <&clks 161>;
1212                                 clock-names = "ipg", "per";
1213                                 status = "disabled";
1214                         };
1215                 };
1216
1217                 ipu1: ipu@02400000 {
1218                         #crtc-cells = <1>;
1219                         compatible = "fsl,imx6q-ipu";
1220                         reg = <0x02400000 0x400000>;
1221                         interrupts = <0 6 0x4 0 5 0x4>;
1222                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1223                         clock-names = "bus", "di0", "di1";
1224                         resets = <&src 2>;
1225                 };
1226         };
1227 };