2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
50 intc: interrupt-controller@00a01000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0x00a01000 0x1000>,
56 interrupt-parent = <&intc>;
64 compatible = "fsl,imx-ckil", "fixed-clock";
66 clock-frequency = <32768>;
70 compatible = "fsl,imx-ckih1", "fixed-clock";
72 clock-frequency = <0>;
76 compatible = "fsl,imx-osc", "fixed-clock";
78 clock-frequency = <24000000>;
85 compatible = "simple-bus";
86 interrupt-parent = <&gpc>;
89 dma_apbh: dma-apbh@00110000 {
90 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
91 reg = <0x00110000 0x2000>;
92 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>,
95 <0 13 IRQ_TYPE_LEVEL_HIGH>;
96 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
99 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
102 gpmi: gpmi-nand@00112000 {
103 compatible = "fsl,imx6q-gpmi-nand";
104 #address-cells = <1>;
106 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
107 reg-names = "gpmi-nand", "bch";
108 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-names = "bch";
110 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
111 <&clks IMX6QDL_CLK_GPMI_APB>,
112 <&clks IMX6QDL_CLK_GPMI_BCH>,
113 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
114 <&clks IMX6QDL_CLK_PER1_BCH>;
115 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
116 "gpmi_bch_apb", "per1_bch";
117 dmas = <&dma_apbh 0>;
123 compatible = "arm,cortex-a9-twd-timer";
124 reg = <0x00a00600 0x20>;
125 interrupts = <1 13 0xf01>;
126 interrupt-parent = <&intc>;
127 clocks = <&clks IMX6QDL_CLK_TWD>;
130 L2: l2-cache@00a02000 {
131 compatible = "arm,pl310-cache";
132 reg = <0x00a02000 0x1000>;
133 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
136 arm,tag-latency = <4 2 3>;
137 arm,data-latency = <4 2 3>;
140 pcie: pcie@0x01000000 {
141 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
142 reg = <0x01ffc000 0x04000>,
143 <0x01f00000 0x80000>;
144 reg-names = "dbi", "config";
145 #address-cells = <3>;
148 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
149 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
150 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
152 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-names = "msi";
154 #interrupt-cells = <1>;
155 interrupt-map-mask = <0 0 0 0x7>;
156 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
157 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
158 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
159 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
161 <&clks IMX6QDL_CLK_LVDS1_GATE>,
162 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
163 clock-names = "pcie", "pcie_bus", "pcie_phy";
168 compatible = "arm,cortex-a9-pmu";
169 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
172 aips-bus@02000000 { /* AIPS1 */
173 compatible = "fsl,aips-bus", "simple-bus";
174 #address-cells = <1>;
176 reg = <0x02000000 0x100000>;
180 compatible = "fsl,spba-bus", "simple-bus";
181 #address-cells = <1>;
183 reg = <0x02000000 0x40000>;
186 spdif: spdif@02004000 {
187 compatible = "fsl,imx35-spdif";
188 reg = <0x02004000 0x4000>;
189 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
190 dmas = <&sdma 14 18 0>,
192 dma-names = "rx", "tx";
193 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
194 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
195 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
196 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
197 <&clks IMX6QDL_CLK_DUMMY>;
198 clock-names = "core", "rxtx0",
206 ecspi1: ecspi@02008000 {
207 #address-cells = <1>;
209 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
210 reg = <0x02008000 0x4000>;
211 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
213 <&clks IMX6QDL_CLK_ECSPI1>;
214 clock-names = "ipg", "per";
215 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
216 dma-names = "rx", "tx";
220 ecspi2: ecspi@0200c000 {
221 #address-cells = <1>;
223 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
224 reg = <0x0200c000 0x4000>;
225 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
227 <&clks IMX6QDL_CLK_ECSPI2>;
228 clock-names = "ipg", "per";
229 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
230 dma-names = "rx", "tx";
234 ecspi3: ecspi@02010000 {
235 #address-cells = <1>;
237 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
238 reg = <0x02010000 0x4000>;
239 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
241 <&clks IMX6QDL_CLK_ECSPI3>;
242 clock-names = "ipg", "per";
243 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
244 dma-names = "rx", "tx";
248 ecspi4: ecspi@02014000 {
249 #address-cells = <1>;
251 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
252 reg = <0x02014000 0x4000>;
253 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
255 <&clks IMX6QDL_CLK_ECSPI4>;
256 clock-names = "ipg", "per";
257 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
258 dma-names = "rx", "tx";
262 uart1: serial@02020000 {
263 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
264 reg = <0x02020000 0x4000>;
265 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
267 <&clks IMX6QDL_CLK_UART_SERIAL>;
268 clock-names = "ipg", "per";
269 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
270 dma-names = "rx", "tx";
274 esai: esai@02024000 {
275 reg = <0x02024000 0x4000>;
276 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
280 #sound-dai-cells = <0>;
281 compatible = "fsl,imx6q-ssi",
283 reg = <0x02028000 0x4000>;
284 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
286 <&clks IMX6QDL_CLK_SSI1>;
287 clock-names = "ipg", "baud";
288 dmas = <&sdma 37 1 0>,
290 dma-names = "rx", "tx";
291 fsl,fifo-depth = <15>;
296 #sound-dai-cells = <0>;
297 compatible = "fsl,imx6q-ssi",
299 reg = <0x0202c000 0x4000>;
300 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
302 <&clks IMX6QDL_CLK_SSI2>;
303 clock-names = "ipg", "baud";
304 dmas = <&sdma 41 1 0>,
306 dma-names = "rx", "tx";
307 fsl,fifo-depth = <15>;
312 #sound-dai-cells = <0>;
313 compatible = "fsl,imx6q-ssi",
315 reg = <0x02030000 0x4000>;
316 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
318 <&clks IMX6QDL_CLK_SSI3>;
319 clock-names = "ipg", "baud";
320 dmas = <&sdma 45 1 0>,
322 dma-names = "rx", "tx";
323 fsl,fifo-depth = <15>;
327 asrc: asrc@02034000 {
328 reg = <0x02034000 0x4000>;
329 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
333 reg = <0x0203c000 0x4000>;
338 compatible = "cnm,coda960";
339 reg = <0x02040000 0x3c000>;
340 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
341 <0 3 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "bit", "jpeg";
343 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
344 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
345 clock-names = "per", "ahb";
350 aipstz@0207c000 { /* AIPSTZ1 */
351 reg = <0x0207c000 0x4000>;
356 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
357 reg = <0x02080000 0x4000>;
358 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clks IMX6QDL_CLK_IPG>,
360 <&clks IMX6QDL_CLK_PWM1>;
361 clock-names = "ipg", "per";
367 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
368 reg = <0x02084000 0x4000>;
369 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6QDL_CLK_IPG>,
371 <&clks IMX6QDL_CLK_PWM2>;
372 clock-names = "ipg", "per";
378 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
379 reg = <0x02088000 0x4000>;
380 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6QDL_CLK_IPG>,
382 <&clks IMX6QDL_CLK_PWM3>;
383 clock-names = "ipg", "per";
389 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
390 reg = <0x0208c000 0x4000>;
391 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clks IMX6QDL_CLK_IPG>,
393 <&clks IMX6QDL_CLK_PWM4>;
394 clock-names = "ipg", "per";
398 can1: flexcan@02090000 {
399 compatible = "fsl,imx6q-flexcan";
400 reg = <0x02090000 0x4000>;
401 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
403 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
404 clock-names = "ipg", "per";
408 can2: flexcan@02094000 {
409 compatible = "fsl,imx6q-flexcan";
410 reg = <0x02094000 0x4000>;
411 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
413 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
414 clock-names = "ipg", "per";
419 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
420 reg = <0x02098000 0x4000>;
421 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
423 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
424 <&clks IMX6QDL_CLK_GPT_3M>;
425 clock-names = "ipg", "per", "osc_per";
428 gpio1: gpio@0209c000 {
429 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
430 reg = <0x0209c000 0x4000>;
431 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
432 <0 67 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
439 gpio2: gpio@020a0000 {
440 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
441 reg = <0x020a0000 0x4000>;
442 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
443 <0 69 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
450 gpio3: gpio@020a4000 {
451 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
452 reg = <0x020a4000 0x4000>;
453 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
454 <0 71 IRQ_TYPE_LEVEL_HIGH>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
461 gpio4: gpio@020a8000 {
462 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
463 reg = <0x020a8000 0x4000>;
464 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
465 <0 73 IRQ_TYPE_LEVEL_HIGH>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 gpio5: gpio@020ac000 {
473 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
474 reg = <0x020ac000 0x4000>;
475 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
476 <0 75 IRQ_TYPE_LEVEL_HIGH>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
483 gpio6: gpio@020b0000 {
484 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
485 reg = <0x020b0000 0x4000>;
486 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
487 <0 77 IRQ_TYPE_LEVEL_HIGH>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
494 gpio7: gpio@020b4000 {
495 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
496 reg = <0x020b4000 0x4000>;
497 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
498 <0 79 IRQ_TYPE_LEVEL_HIGH>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
506 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
507 reg = <0x020b8000 0x4000>;
508 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clks IMX6QDL_CLK_IPG>;
513 wdog1: wdog@020bc000 {
514 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
515 reg = <0x020bc000 0x4000>;
516 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clks IMX6QDL_CLK_DUMMY>;
520 wdog2: wdog@020c0000 {
521 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
522 reg = <0x020c0000 0x4000>;
523 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&clks IMX6QDL_CLK_DUMMY>;
529 compatible = "fsl,imx6q-ccm";
530 reg = <0x020c4000 0x4000>;
531 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
532 <0 88 IRQ_TYPE_LEVEL_HIGH>;
536 anatop: anatop@020c8000 {
537 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
538 reg = <0x020c8000 0x1000>;
539 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
540 <0 54 IRQ_TYPE_LEVEL_HIGH>,
541 <0 127 IRQ_TYPE_LEVEL_HIGH>;
544 compatible = "fsl,anatop-regulator";
545 regulator-name = "vdd1p1";
546 regulator-min-microvolt = <800000>;
547 regulator-max-microvolt = <1375000>;
549 anatop-reg-offset = <0x110>;
550 anatop-vol-bit-shift = <8>;
551 anatop-vol-bit-width = <5>;
552 anatop-min-bit-val = <4>;
553 anatop-min-voltage = <800000>;
554 anatop-max-voltage = <1375000>;
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vdd3p0";
560 regulator-min-microvolt = <2800000>;
561 regulator-max-microvolt = <3150000>;
563 anatop-reg-offset = <0x120>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2625000>;
568 anatop-max-voltage = <3400000>;
572 compatible = "fsl,anatop-regulator";
573 regulator-name = "vdd2p5";
574 regulator-min-microvolt = <2000000>;
575 regulator-max-microvolt = <2750000>;
577 anatop-reg-offset = <0x130>;
578 anatop-vol-bit-shift = <8>;
579 anatop-vol-bit-width = <5>;
580 anatop-min-bit-val = <0>;
581 anatop-min-voltage = <2000000>;
582 anatop-max-voltage = <2750000>;
585 reg_arm: regulator-vddcore@140 {
586 compatible = "fsl,anatop-regulator";
587 regulator-name = "vddarm";
588 regulator-min-microvolt = <725000>;
589 regulator-max-microvolt = <1450000>;
591 anatop-reg-offset = <0x140>;
592 anatop-vol-bit-shift = <0>;
593 anatop-vol-bit-width = <5>;
594 anatop-delay-reg-offset = <0x170>;
595 anatop-delay-bit-shift = <24>;
596 anatop-delay-bit-width = <2>;
597 anatop-min-bit-val = <1>;
598 anatop-min-voltage = <725000>;
599 anatop-max-voltage = <1450000>;
602 reg_pu: regulator-vddpu@140 {
603 compatible = "fsl,anatop-regulator";
604 regulator-name = "vddpu";
605 regulator-min-microvolt = <725000>;
606 regulator-max-microvolt = <1450000>;
607 regulator-enable-ramp-delay = <150>;
608 anatop-reg-offset = <0x140>;
609 anatop-vol-bit-shift = <9>;
610 anatop-vol-bit-width = <5>;
611 anatop-delay-reg-offset = <0x170>;
612 anatop-delay-bit-shift = <26>;
613 anatop-delay-bit-width = <2>;
614 anatop-min-bit-val = <1>;
615 anatop-min-voltage = <725000>;
616 anatop-max-voltage = <1450000>;
619 reg_soc: regulator-vddsoc@140 {
620 compatible = "fsl,anatop-regulator";
621 regulator-name = "vddsoc";
622 regulator-min-microvolt = <725000>;
623 regulator-max-microvolt = <1450000>;
625 anatop-reg-offset = <0x140>;
626 anatop-vol-bit-shift = <18>;
627 anatop-vol-bit-width = <5>;
628 anatop-delay-reg-offset = <0x170>;
629 anatop-delay-bit-shift = <28>;
630 anatop-delay-bit-width = <2>;
631 anatop-min-bit-val = <1>;
632 anatop-min-voltage = <725000>;
633 anatop-max-voltage = <1450000>;
638 compatible = "fsl,imx6q-tempmon";
639 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
640 fsl,tempmon = <&anatop>;
641 fsl,tempmon-data = <&ocotp>;
642 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
645 usbphy1: usbphy@020c9000 {
646 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
647 reg = <0x020c9000 0x1000>;
648 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
650 fsl,anatop = <&anatop>;
653 usbphy2: usbphy@020ca000 {
654 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
655 reg = <0x020ca000 0x1000>;
656 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
658 fsl,anatop = <&anatop>;
662 compatible = "fsl,sec-v4.0-mon", "simple-bus";
663 #address-cells = <1>;
665 ranges = <0 0x020cc000 0x4000>;
667 snvs_rtc: snvs-rtc-lp@34 {
668 compatible = "fsl,sec-v4.0-mon-rtc-lp";
670 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
671 <0 20 IRQ_TYPE_LEVEL_HIGH>;
674 snvs_poweroff: snvs-poweroff@38 {
675 compatible = "fsl,sec-v4.0-poweroff";
681 epit1: epit@020d0000 { /* EPIT1 */
682 reg = <0x020d0000 0x4000>;
683 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
686 epit2: epit@020d4000 { /* EPIT2 */
687 reg = <0x020d4000 0x4000>;
688 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
692 compatible = "fsl,imx6q-src", "fsl,imx51-src";
693 reg = <0x020d8000 0x4000>;
694 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
695 <0 96 IRQ_TYPE_LEVEL_HIGH>;
700 compatible = "fsl,imx6q-gpc";
701 reg = <0x020dc000 0x4000>;
702 interrupt-controller;
703 #interrupt-cells = <3>;
704 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
705 <0 90 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-parent = <&intc>;
707 pu-supply = <®_pu>;
708 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
709 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
710 <&clks IMX6QDL_CLK_GPU2D_CORE>,
711 <&clks IMX6QDL_CLK_GPU2D_AXI>,
712 <&clks IMX6QDL_CLK_OPENVG_AXI>,
713 <&clks IMX6QDL_CLK_VPU_AXI>;
714 #power-domain-cells = <1>;
717 gpr: iomuxc-gpr@020e0000 {
718 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
719 reg = <0x020e0000 0x38>;
722 iomuxc: iomuxc@020e0000 {
723 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
724 reg = <0x020e0000 0x4000>;
728 #address-cells = <1>;
730 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
735 #address-cells = <1>;
743 lvds0_mux_0: endpoint {
744 remote-endpoint = <&ipu1_di0_lvds0>;
751 lvds0_mux_1: endpoint {
752 remote-endpoint = <&ipu1_di1_lvds0>;
758 #address-cells = <1>;
766 lvds1_mux_0: endpoint {
767 remote-endpoint = <&ipu1_di0_lvds1>;
774 lvds1_mux_1: endpoint {
775 remote-endpoint = <&ipu1_di1_lvds1>;
782 #address-cells = <1>;
784 reg = <0x00120000 0x9000>;
785 interrupts = <0 115 0x04>;
787 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
788 <&clks IMX6QDL_CLK_HDMI_ISFR>;
789 clock-names = "iahb", "isfr";
795 hdmi_mux_0: endpoint {
796 remote-endpoint = <&ipu1_di0_hdmi>;
803 hdmi_mux_1: endpoint {
804 remote-endpoint = <&ipu1_di1_hdmi>;
809 dcic1: dcic@020e4000 {
810 reg = <0x020e4000 0x4000>;
811 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
814 dcic2: dcic@020e8000 {
815 reg = <0x020e8000 0x4000>;
816 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
819 sdma: sdma@020ec000 {
820 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
821 reg = <0x020ec000 0x4000>;
822 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&clks IMX6QDL_CLK_SDMA>,
824 <&clks IMX6QDL_CLK_SDMA>;
825 clock-names = "ipg", "ahb";
827 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
831 aips-bus@02100000 { /* AIPS2 */
832 compatible = "fsl,aips-bus", "simple-bus";
833 #address-cells = <1>;
835 reg = <0x02100000 0x100000>;
839 reg = <0x02100000 0x40000>;
840 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
841 <0 106 IRQ_TYPE_LEVEL_HIGH>;
844 aipstz@0217c000 { /* AIPSTZ2 */
845 reg = <0x0217c000 0x4000>;
848 usbotg: usb@02184000 {
849 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
850 reg = <0x02184000 0x200>;
851 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX6QDL_CLK_USBOH3>;
853 fsl,usbphy = <&usbphy1>;
854 fsl,usbmisc = <&usbmisc 0>;
858 usbh1: usb@02184200 {
859 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
860 reg = <0x02184200 0x200>;
861 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&clks IMX6QDL_CLK_USBOH3>;
863 fsl,usbphy = <&usbphy2>;
864 fsl,usbmisc = <&usbmisc 1>;
869 usbh2: usb@02184400 {
870 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
871 reg = <0x02184400 0x200>;
872 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6QDL_CLK_USBOH3>;
874 fsl,usbmisc = <&usbmisc 2>;
879 usbh3: usb@02184600 {
880 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
881 reg = <0x02184600 0x200>;
882 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX6QDL_CLK_USBOH3>;
884 fsl,usbmisc = <&usbmisc 3>;
889 usbmisc: usbmisc@02184800 {
891 compatible = "fsl,imx6q-usbmisc";
892 reg = <0x02184800 0x200>;
893 clocks = <&clks IMX6QDL_CLK_USBOH3>;
896 fec: ethernet@02188000 {
897 compatible = "fsl,imx6q-fec";
898 reg = <0x02188000 0x4000>;
899 interrupts-extended =
900 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
901 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clks IMX6QDL_CLK_ENET>,
903 <&clks IMX6QDL_CLK_ENET>,
904 <&clks IMX6QDL_CLK_ENET_REF>;
905 clock-names = "ipg", "ahb", "ptp";
910 reg = <0x0218c000 0x4000>;
911 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
912 <0 117 IRQ_TYPE_LEVEL_HIGH>,
913 <0 126 IRQ_TYPE_LEVEL_HIGH>;
916 usdhc1: usdhc@02190000 {
917 compatible = "fsl,imx6q-usdhc";
918 reg = <0x02190000 0x4000>;
919 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clks IMX6QDL_CLK_USDHC1>,
921 <&clks IMX6QDL_CLK_USDHC1>,
922 <&clks IMX6QDL_CLK_USDHC1>;
923 clock-names = "ipg", "ahb", "per";
928 usdhc2: usdhc@02194000 {
929 compatible = "fsl,imx6q-usdhc";
930 reg = <0x02194000 0x4000>;
931 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&clks IMX6QDL_CLK_USDHC2>,
933 <&clks IMX6QDL_CLK_USDHC2>,
934 <&clks IMX6QDL_CLK_USDHC2>;
935 clock-names = "ipg", "ahb", "per";
940 usdhc3: usdhc@02198000 {
941 compatible = "fsl,imx6q-usdhc";
942 reg = <0x02198000 0x4000>;
943 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX6QDL_CLK_USDHC3>,
945 <&clks IMX6QDL_CLK_USDHC3>,
946 <&clks IMX6QDL_CLK_USDHC3>;
947 clock-names = "ipg", "ahb", "per";
952 usdhc4: usdhc@0219c000 {
953 compatible = "fsl,imx6q-usdhc";
954 reg = <0x0219c000 0x4000>;
955 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6QDL_CLK_USDHC4>,
957 <&clks IMX6QDL_CLK_USDHC4>,
958 <&clks IMX6QDL_CLK_USDHC4>;
959 clock-names = "ipg", "ahb", "per";
965 #address-cells = <1>;
967 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
968 reg = <0x021a0000 0x4000>;
969 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&clks IMX6QDL_CLK_I2C1>;
975 #address-cells = <1>;
977 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
978 reg = <0x021a4000 0x4000>;
979 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clks IMX6QDL_CLK_I2C2>;
985 #address-cells = <1>;
987 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
988 reg = <0x021a8000 0x4000>;
989 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&clks IMX6QDL_CLK_I2C3>;
995 reg = <0x021ac000 0x4000>;
998 mmdc0: mmdc@021b0000 { /* MMDC0 */
999 compatible = "fsl,imx6q-mmdc";
1000 reg = <0x021b0000 0x4000>;
1003 mmdc1: mmdc@021b4000 { /* MMDC1 */
1004 reg = <0x021b4000 0x4000>;
1007 weim: weim@021b8000 {
1008 compatible = "fsl,imx6q-weim";
1009 reg = <0x021b8000 0x4000>;
1010 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1014 ocotp: ocotp@021bc000 {
1015 compatible = "fsl,imx6q-ocotp", "syscon";
1016 reg = <0x021bc000 0x4000>;
1019 tzasc@021d0000 { /* TZASC1 */
1020 reg = <0x021d0000 0x4000>;
1021 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1024 tzasc@021d4000 { /* TZASC2 */
1025 reg = <0x021d4000 0x4000>;
1026 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1029 audmux: audmux@021d8000 {
1030 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1031 reg = <0x021d8000 0x4000>;
1032 status = "disabled";
1035 mipi_csi: mipi@021dc000 {
1036 reg = <0x021dc000 0x4000>;
1039 mipi_dsi: mipi@021e0000 {
1040 #address-cells = <1>;
1042 reg = <0x021e0000 0x4000>;
1043 status = "disabled";
1046 #address-cells = <1>;
1052 mipi_mux_0: endpoint {
1053 remote-endpoint = <&ipu1_di0_mipi>;
1060 mipi_mux_1: endpoint {
1061 remote-endpoint = <&ipu1_di1_mipi>;
1068 reg = <0x021e4000 0x4000>;
1069 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1072 uart2: serial@021e8000 {
1073 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1074 reg = <0x021e8000 0x4000>;
1075 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1077 <&clks IMX6QDL_CLK_UART_SERIAL>;
1078 clock-names = "ipg", "per";
1079 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1080 dma-names = "rx", "tx";
1081 status = "disabled";
1084 uart3: serial@021ec000 {
1085 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1086 reg = <0x021ec000 0x4000>;
1087 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1089 <&clks IMX6QDL_CLK_UART_SERIAL>;
1090 clock-names = "ipg", "per";
1091 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1092 dma-names = "rx", "tx";
1093 status = "disabled";
1096 uart4: serial@021f0000 {
1097 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1098 reg = <0x021f0000 0x4000>;
1099 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1101 <&clks IMX6QDL_CLK_UART_SERIAL>;
1102 clock-names = "ipg", "per";
1103 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1104 dma-names = "rx", "tx";
1105 status = "disabled";
1108 uart5: serial@021f4000 {
1109 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1110 reg = <0x021f4000 0x4000>;
1111 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1112 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1113 <&clks IMX6QDL_CLK_UART_SERIAL>;
1114 clock-names = "ipg", "per";
1115 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1116 dma-names = "rx", "tx";
1117 status = "disabled";
1121 ipu1: ipu@02400000 {
1122 #address-cells = <1>;
1124 compatible = "fsl,imx6q-ipu";
1125 reg = <0x02400000 0x400000>;
1126 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1127 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&clks IMX6QDL_CLK_IPU1>,
1129 <&clks IMX6QDL_CLK_IPU1_DI0>,
1130 <&clks IMX6QDL_CLK_IPU1_DI1>;
1131 clock-names = "bus", "di0", "di1";
1143 #address-cells = <1>;
1147 ipu1_di0_disp0: endpoint@0 {
1150 ipu1_di0_hdmi: endpoint@1 {
1151 remote-endpoint = <&hdmi_mux_0>;
1154 ipu1_di0_mipi: endpoint@2 {
1155 remote-endpoint = <&mipi_mux_0>;
1158 ipu1_di0_lvds0: endpoint@3 {
1159 remote-endpoint = <&lvds0_mux_0>;
1162 ipu1_di0_lvds1: endpoint@4 {
1163 remote-endpoint = <&lvds1_mux_0>;
1168 #address-cells = <1>;
1172 ipu1_di0_disp1: endpoint@0 {
1175 ipu1_di1_hdmi: endpoint@1 {
1176 remote-endpoint = <&hdmi_mux_1>;
1179 ipu1_di1_mipi: endpoint@2 {
1180 remote-endpoint = <&mipi_mux_1>;
1183 ipu1_di1_lvds0: endpoint@3 {
1184 remote-endpoint = <&lvds0_mux_1>;
1187 ipu1_di1_lvds1: endpoint@4 {
1188 remote-endpoint = <&lvds1_mux_1>;