arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 ethernet0 = &fec;
  21                 can0 = &can1;
  22                 can1 = &can2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 mmc3 = &usdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         intc: interrupt-controller@00a01000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56                 interrupt-parent = <&intc>;
  57         };
  58
  59         clocks {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 ckil {
  64                         compatible = "fsl,imx-ckil", "fixed-clock";
  65                         #clock-cells = <0>;
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 ckih1 {
  70                         compatible = "fsl,imx-ckih1", "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc {
  76                         compatible = "fsl,imx-osc", "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <24000000>;
  79                 };
  80         };
  81
  82         soc {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 compatible = "simple-bus";
  86                 interrupt-parent = <&gpc>;
  87                 ranges;
  88
  89                 dma_apbh: dma-apbh@00110000 {
  90                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  91                         reg = <0x00110000 0x2000>;
  92                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  96                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  97                         #dma-cells = <1>;
  98                         dma-channels = <4>;
  99                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 100                 };
 101
 102                 gpmi: gpmi-nand@00112000 {
 103                         compatible = "fsl,imx6q-gpmi-nand";
 104                         #address-cells = <1>;
 105                         #size-cells = <1>;
 106                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 107                         reg-names = "gpmi-nand", "bch";
 108                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 109                         interrupt-names = "bch";
 110                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 111                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 112                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 113                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 114                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 115                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 116                                       "gpmi_bch_apb", "per1_bch";
 117                         dmas = <&dma_apbh 0>;
 118                         dma-names = "rx-tx";
 119                         status = "disabled";
 120                 };
 121
 122                 timer@00a00600 {
 123                         compatible = "arm,cortex-a9-twd-timer";
 124                         reg = <0x00a00600 0x20>;
 125                         interrupts = <1 13 0xf01>;
 126                         interrupt-parent = <&intc>;
 127                         clocks = <&clks IMX6QDL_CLK_TWD>;
 128                 };
 129
 130                 L2: l2-cache@00a02000 {
 131                         compatible = "arm,pl310-cache";
 132                         reg = <0x00a02000 0x1000>;
 133                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 134                         cache-unified;
 135                         cache-level = <2>;
 136                         arm,tag-latency = <4 2 3>;
 137                         arm,data-latency = <4 2 3>;
 138                 };
 139
 140                 pcie: pcie@0x01000000 {
 141                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 142                         reg = <0x01ffc000 0x04000>,
 143                               <0x01f00000 0x80000>;
 144                         reg-names = "dbi", "config";
 145                         #address-cells = <3>;
 146                         #size-cells = <2>;
 147                         device_type = "pci";
 148                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 149                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 150                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 151                         num-lanes = <1>;
 152                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 153                         interrupt-names = "msi";
 154                         #interrupt-cells = <1>;
 155                         interrupt-map-mask = <0 0 0 0x7>;
 156                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 157                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 158                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 159                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 160                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 161                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 162                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 163                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 164                         status = "disabled";
 165                 };
 166
 167                 pmu {
 168                         compatible = "arm,cortex-a9-pmu";
 169                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 170                 };
 171
 172                 aips-bus@02000000 { /* AIPS1 */
 173                         compatible = "fsl,aips-bus", "simple-bus";
 174                         #address-cells = <1>;
 175                         #size-cells = <1>;
 176                         reg = <0x02000000 0x100000>;
 177                         ranges;
 178
 179                         spba-bus@02000000 {
 180                                 compatible = "fsl,spba-bus", "simple-bus";
 181                                 #address-cells = <1>;
 182                                 #size-cells = <1>;
 183                                 reg = <0x02000000 0x40000>;
 184                                 ranges;
 185
 186                                 spdif: spdif@02004000 {
 187                                         compatible = "fsl,imx35-spdif";
 188                                         reg = <0x02004000 0x4000>;
 189                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 190                                         dmas = <&sdma 14 18 0>,
 191                                                <&sdma 15 18 0>;
 192                                         dma-names = "rx", "tx";
 193                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 194                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
 195                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 196                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 197                                                  <&clks IMX6QDL_CLK_DUMMY>;
 198                                         clock-names = "core",  "rxtx0",
 199                                                       "rxtx1", "rxtx2",
 200                                                       "rxtx3", "rxtx4",
 201                                                       "rxtx5", "rxtx6",
 202                                                       "rxtx7";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 ecspi1: ecspi@02008000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x02008000 0x4000>;
 211                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 212                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 213                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 214                                         clock-names = "ipg", "per";
 215                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 216                                         dma-names = "rx", "tx";
 217                                         status = "disabled";
 218                                 };
 219
 220                                 ecspi2: ecspi@0200c000 {
 221                                         #address-cells = <1>;
 222                                         #size-cells = <0>;
 223                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 224                                         reg = <0x0200c000 0x4000>;
 225                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 226                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 227                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 228                                         clock-names = "ipg", "per";
 229                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 230                                         dma-names = "rx", "tx";
 231                                         status = "disabled";
 232                                 };
 233
 234                                 ecspi3: ecspi@02010000 {
 235                                         #address-cells = <1>;
 236                                         #size-cells = <0>;
 237                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 238                                         reg = <0x02010000 0x4000>;
 239                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 240                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 241                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 ecspi4: ecspi@02014000 {
 249                                         #address-cells = <1>;
 250                                         #size-cells = <0>;
 251                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 252                                         reg = <0x02014000 0x4000>;
 253                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 255                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 256                                         clock-names = "ipg", "per";
 257                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 258                                         dma-names = "rx", "tx";
 259                                         status = "disabled";
 260                                 };
 261
 262                                 uart1: serial@02020000 {
 263                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 264                                         reg = <0x02020000 0x4000>;
 265                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 267                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 270                                         dma-names = "rx", "tx";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 esai: esai@02024000 {
 275                                         reg = <0x02024000 0x4000>;
 276                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 277                                 };
 278
 279                                 ssi1: ssi@02028000 {
 280                                         #sound-dai-cells = <0>;
 281                                         compatible = "fsl,imx6q-ssi",
 282                                                         "fsl,imx51-ssi";
 283                                         reg = <0x02028000 0x4000>;
 284                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 286                                                  <&clks IMX6QDL_CLK_SSI1>;
 287                                         clock-names = "ipg", "baud";
 288                                         dmas = <&sdma 37 1 0>,
 289                                                <&sdma 38 1 0>;
 290                                         dma-names = "rx", "tx";
 291                                         fsl,fifo-depth = <15>;
 292                                         status = "disabled";
 293                                 };
 294
 295                                 ssi2: ssi@0202c000 {
 296                                         #sound-dai-cells = <0>;
 297                                         compatible = "fsl,imx6q-ssi",
 298                                                         "fsl,imx51-ssi";
 299                                         reg = <0x0202c000 0x4000>;
 300                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 301                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 302                                                  <&clks IMX6QDL_CLK_SSI2>;
 303                                         clock-names = "ipg", "baud";
 304                                         dmas = <&sdma 41 1 0>,
 305                                                <&sdma 42 1 0>;
 306                                         dma-names = "rx", "tx";
 307                                         fsl,fifo-depth = <15>;
 308                                         status = "disabled";
 309                                 };
 310
 311                                 ssi3: ssi@02030000 {
 312                                         #sound-dai-cells = <0>;
 313                                         compatible = "fsl,imx6q-ssi",
 314                                                         "fsl,imx51-ssi";
 315                                         reg = <0x02030000 0x4000>;
 316                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 317                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 318                                                  <&clks IMX6QDL_CLK_SSI3>;
 319                                         clock-names = "ipg", "baud";
 320                                         dmas = <&sdma 45 1 0>,
 321                                                <&sdma 46 1 0>;
 322                                         dma-names = "rx", "tx";
 323                                         fsl,fifo-depth = <15>;
 324                                         status = "disabled";
 325                                 };
 326
 327                                 asrc: asrc@02034000 {
 328                                         reg = <0x02034000 0x4000>;
 329                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 330                                 };
 331
 332                                 spba@0203c000 {
 333                                         reg = <0x0203c000 0x4000>;
 334                                 };
 335                         };
 336
 337                         vpu: vpu@02040000 {
 338                                 compatible = "cnm,coda960";
 339                                 reg = <0x02040000 0x3c000>;
 340                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 341                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 342                                 interrupt-names = "bit", "jpeg";
 343                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 344                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 345                                 clock-names = "per", "ahb";
 346                                 resets = <&src 1>;
 347                                 iram = <&ocram>;
 348                         };
 349
 350                         aipstz@0207c000 { /* AIPSTZ1 */
 351                                 reg = <0x0207c000 0x4000>;
 352                         };
 353
 354                         pwm1: pwm@02080000 {
 355                                 #pwm-cells = <2>;
 356                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x02080000 0x4000>;
 358                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 360                                          <&clks IMX6QDL_CLK_PWM1>;
 361                                 clock-names = "ipg", "per";
 362                         };
 363
 364                         pwm2: pwm@02084000 {
 365                                 #pwm-cells = <2>;
 366                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 367                                 reg = <0x02084000 0x4000>;
 368                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 369                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 370                                          <&clks IMX6QDL_CLK_PWM2>;
 371                                 clock-names = "ipg", "per";
 372                         };
 373
 374                         pwm3: pwm@02088000 {
 375                                 #pwm-cells = <2>;
 376                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 377                                 reg = <0x02088000 0x4000>;
 378                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 380                                          <&clks IMX6QDL_CLK_PWM3>;
 381                                 clock-names = "ipg", "per";
 382                         };
 383
 384                         pwm4: pwm@0208c000 {
 385                                 #pwm-cells = <2>;
 386                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 387                                 reg = <0x0208c000 0x4000>;
 388                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 389                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 390                                          <&clks IMX6QDL_CLK_PWM4>;
 391                                 clock-names = "ipg", "per";
 392                         };
 393
 394                         can1: flexcan@02090000 {
 395                                 compatible = "fsl,imx6q-flexcan";
 396                                 reg = <0x02090000 0x4000>;
 397                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 398                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 399                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 400                                 clock-names = "ipg", "per";
 401                                 status = "disabled";
 402                         };
 403
 404                         can2: flexcan@02094000 {
 405                                 compatible = "fsl,imx6q-flexcan";
 406                                 reg = <0x02094000 0x4000>;
 407                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 408                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 409                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 410                                 clock-names = "ipg", "per";
 411                                 status = "disabled";
 412                         };
 413
 414                         gpt: gpt@02098000 {
 415                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 416                                 reg = <0x02098000 0x4000>;
 417                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 419                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 420                                          <&clks IMX6QDL_CLK_GPT_3M>;
 421                                 clock-names = "ipg", "per", "osc_per";
 422                         };
 423
 424                         gpio1: gpio@0209c000 {
 425                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 426                                 reg = <0x0209c000 0x4000>;
 427                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 428                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 429                                 gpio-controller;
 430                                 #gpio-cells = <2>;
 431                                 interrupt-controller;
 432                                 #interrupt-cells = <2>;
 433                         };
 434
 435                         gpio2: gpio@020a0000 {
 436                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 437                                 reg = <0x020a0000 0x4000>;
 438                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 439                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 440                                 gpio-controller;
 441                                 #gpio-cells = <2>;
 442                                 interrupt-controller;
 443                                 #interrupt-cells = <2>;
 444                         };
 445
 446                         gpio3: gpio@020a4000 {
 447                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 448                                 reg = <0x020a4000 0x4000>;
 449                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 450                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 451                                 gpio-controller;
 452                                 #gpio-cells = <2>;
 453                                 interrupt-controller;
 454                                 #interrupt-cells = <2>;
 455                         };
 456
 457                         gpio4: gpio@020a8000 {
 458                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 459                                 reg = <0x020a8000 0x4000>;
 460                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 461                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 462                                 gpio-controller;
 463                                 #gpio-cells = <2>;
 464                                 interrupt-controller;
 465                                 #interrupt-cells = <2>;
 466                         };
 467
 468                         gpio5: gpio@020ac000 {
 469                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 470                                 reg = <0x020ac000 0x4000>;
 471                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 472                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 473                                 gpio-controller;
 474                                 #gpio-cells = <2>;
 475                                 interrupt-controller;
 476                                 #interrupt-cells = <2>;
 477                         };
 478
 479                         gpio6: gpio@020b0000 {
 480                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 481                                 reg = <0x020b0000 0x4000>;
 482                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 483                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 484                                 gpio-controller;
 485                                 #gpio-cells = <2>;
 486                                 interrupt-controller;
 487                                 #interrupt-cells = <2>;
 488                         };
 489
 490                         gpio7: gpio@020b4000 {
 491                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 492                                 reg = <0x020b4000 0x4000>;
 493                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 494                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 495                                 gpio-controller;
 496                                 #gpio-cells = <2>;
 497                                 interrupt-controller;
 498                                 #interrupt-cells = <2>;
 499                         };
 500
 501                         kpp: kpp@020b8000 {
 502                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 503                                 reg = <0x020b8000 0x4000>;
 504                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 505                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 506                                 status = "disabled";
 507                         };
 508
 509                         wdog1: wdog@020bc000 {
 510                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 511                                 reg = <0x020bc000 0x4000>;
 512                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 513                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 514                         };
 515
 516                         wdog2: wdog@020c0000 {
 517                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 518                                 reg = <0x020c0000 0x4000>;
 519                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 520                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 521                                 status = "disabled";
 522                         };
 523
 524                         clks: ccm@020c4000 {
 525                                 compatible = "fsl,imx6q-ccm";
 526                                 reg = <0x020c4000 0x4000>;
 527                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 528                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 529                                 #clock-cells = <1>;
 530                         };
 531
 532                         anatop: anatop@020c8000 {
 533                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 534                                 reg = <0x020c8000 0x1000>;
 535                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 536                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 537                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 538
 539                                 regulator-1p1@110 {
 540                                         compatible = "fsl,anatop-regulator";
 541                                         regulator-name = "vdd1p1";
 542                                         regulator-min-microvolt = <800000>;
 543                                         regulator-max-microvolt = <1375000>;
 544                                         regulator-always-on;
 545                                         anatop-reg-offset = <0x110>;
 546                                         anatop-vol-bit-shift = <8>;
 547                                         anatop-vol-bit-width = <5>;
 548                                         anatop-min-bit-val = <4>;
 549                                         anatop-min-voltage = <800000>;
 550                                         anatop-max-voltage = <1375000>;
 551                                 };
 552
 553                                 regulator-3p0@120 {
 554                                         compatible = "fsl,anatop-regulator";
 555                                         regulator-name = "vdd3p0";
 556                                         regulator-min-microvolt = <2800000>;
 557                                         regulator-max-microvolt = <3150000>;
 558                                         regulator-always-on;
 559                                         anatop-reg-offset = <0x120>;
 560                                         anatop-vol-bit-shift = <8>;
 561                                         anatop-vol-bit-width = <5>;
 562                                         anatop-min-bit-val = <0>;
 563                                         anatop-min-voltage = <2625000>;
 564                                         anatop-max-voltage = <3400000>;
 565                                 };
 566
 567                                 regulator-2p5@130 {
 568                                         compatible = "fsl,anatop-regulator";
 569                                         regulator-name = "vdd2p5";
 570                                         regulator-min-microvolt = <2000000>;
 571                                         regulator-max-microvolt = <2750000>;
 572                                         regulator-always-on;
 573                                         anatop-reg-offset = <0x130>;
 574                                         anatop-vol-bit-shift = <8>;
 575                                         anatop-vol-bit-width = <5>;
 576                                         anatop-min-bit-val = <0>;
 577                                         anatop-min-voltage = <2000000>;
 578                                         anatop-max-voltage = <2750000>;
 579                                 };
 580
 581                                 reg_arm: regulator-vddcore@140 {
 582                                         compatible = "fsl,anatop-regulator";
 583                                         regulator-name = "vddarm";
 584                                         regulator-min-microvolt = <725000>;
 585                                         regulator-max-microvolt = <1450000>;
 586                                         regulator-always-on;
 587                                         anatop-reg-offset = <0x140>;
 588                                         anatop-vol-bit-shift = <0>;
 589                                         anatop-vol-bit-width = <5>;
 590                                         anatop-delay-reg-offset = <0x170>;
 591                                         anatop-delay-bit-shift = <24>;
 592                                         anatop-delay-bit-width = <2>;
 593                                         anatop-min-bit-val = <1>;
 594                                         anatop-min-voltage = <725000>;
 595                                         anatop-max-voltage = <1450000>;
 596                                 };
 597
 598                                 reg_pu: regulator-vddpu@140 {
 599                                         compatible = "fsl,anatop-regulator";
 600                                         regulator-name = "vddpu";
 601                                         regulator-min-microvolt = <725000>;
 602                                         regulator-max-microvolt = <1450000>;
 603                                         regulator-always-on;
 604                                         anatop-reg-offset = <0x140>;
 605                                         anatop-vol-bit-shift = <9>;
 606                                         anatop-vol-bit-width = <5>;
 607                                         anatop-delay-reg-offset = <0x170>;
 608                                         anatop-delay-bit-shift = <26>;
 609                                         anatop-delay-bit-width = <2>;
 610                                         anatop-min-bit-val = <1>;
 611                                         anatop-min-voltage = <725000>;
 612                                         anatop-max-voltage = <1450000>;
 613                                 };
 614
 615                                 reg_soc: regulator-vddsoc@140 {
 616                                         compatible = "fsl,anatop-regulator";
 617                                         regulator-name = "vddsoc";
 618                                         regulator-min-microvolt = <725000>;
 619                                         regulator-max-microvolt = <1450000>;
 620                                         regulator-always-on;
 621                                         anatop-reg-offset = <0x140>;
 622                                         anatop-vol-bit-shift = <18>;
 623                                         anatop-vol-bit-width = <5>;
 624                                         anatop-delay-reg-offset = <0x170>;
 625                                         anatop-delay-bit-shift = <28>;
 626                                         anatop-delay-bit-width = <2>;
 627                                         anatop-min-bit-val = <1>;
 628                                         anatop-min-voltage = <725000>;
 629                                         anatop-max-voltage = <1450000>;
 630                                 };
 631                         };
 632
 633                         tempmon: tempmon {
 634                                 compatible = "fsl,imx6q-tempmon";
 635                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 636                                 fsl,tempmon = <&anatop>;
 637                                 fsl,tempmon-data = <&ocotp>;
 638                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 639                         };
 640
 641                         usbphy1: usbphy@020c9000 {
 642                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 643                                 reg = <0x020c9000 0x1000>;
 644                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 645                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 646                                 fsl,anatop = <&anatop>;
 647                         };
 648
 649                         usbphy2: usbphy@020ca000 {
 650                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 651                                 reg = <0x020ca000 0x1000>;
 652                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 653                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 654                                 fsl,anatop = <&anatop>;
 655                         };
 656
 657                         snvs@020cc000 {
 658                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 659                                 #address-cells = <1>;
 660                                 #size-cells = <1>;
 661                                 ranges = <0 0x020cc000 0x4000>;
 662
 663                                 snvs_rtc: snvs-rtc-lp@34 {
 664                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 665                                         reg = <0x34 0x58>;
 666                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 667                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 668                                 };
 669
 670                                 snvs_poweroff: snvs-poweroff@38 {
 671                                         compatible = "fsl,sec-v4.0-poweroff";
 672                                         reg = <0x38 0x4>;
 673                                         status = "disabled";
 674                                 };
 675                         };
 676
 677                         epit1: epit@020d0000 { /* EPIT1 */
 678                                 reg = <0x020d0000 0x4000>;
 679                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 680                         };
 681
 682                         epit2: epit@020d4000 { /* EPIT2 */
 683                                 reg = <0x020d4000 0x4000>;
 684                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 685                         };
 686
 687                         src: src@020d8000 {
 688                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 689                                 reg = <0x020d8000 0x4000>;
 690                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 691                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 692                                 #reset-cells = <1>;
 693                         };
 694
 695                         gpc: gpc@020dc000 {
 696                                 compatible = "fsl,imx6q-gpc";
 697                                 reg = <0x020dc000 0x4000>;
 698                                 interrupt-controller;
 699                                 #interrupt-cells = <3>;
 700                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 701                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 702                                 interrupt-parent = <&intc>;
 703                         };
 704
 705                         gpr: iomuxc-gpr@020e0000 {
 706                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 707                                 reg = <0x020e0000 0x38>;
 708                         };
 709
 710                         iomuxc: iomuxc@020e0000 {
 711                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 712                                 reg = <0x020e0000 0x4000>;
 713                         };
 714
 715                         ldb: ldb@020e0008 {
 716                                 #address-cells = <1>;
 717                                 #size-cells = <0>;
 718                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 719                                 gpr = <&gpr>;
 720                                 status = "disabled";
 721
 722                                 lvds-channel@0 {
 723                                         #address-cells = <1>;
 724                                         #size-cells = <0>;
 725                                         reg = <0>;
 726                                         status = "disabled";
 727
 728                                         port@0 {
 729                                                 reg = <0>;
 730
 731                                                 lvds0_mux_0: endpoint {
 732                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 733                                                 };
 734                                         };
 735
 736                                         port@1 {
 737                                                 reg = <1>;
 738
 739                                                 lvds0_mux_1: endpoint {
 740                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 741                                                 };
 742                                         };
 743                                 };
 744
 745                                 lvds-channel@1 {
 746                                         #address-cells = <1>;
 747                                         #size-cells = <0>;
 748                                         reg = <1>;
 749                                         status = "disabled";
 750
 751                                         port@0 {
 752                                                 reg = <0>;
 753
 754                                                 lvds1_mux_0: endpoint {
 755                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 756                                                 };
 757                                         };
 758
 759                                         port@1 {
 760                                                 reg = <1>;
 761
 762                                                 lvds1_mux_1: endpoint {
 763                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 764                                                 };
 765                                         };
 766                                 };
 767                         };
 768
 769                         hdmi: hdmi@0120000 {
 770                                 #address-cells = <1>;
 771                                 #size-cells = <0>;
 772                                 reg = <0x00120000 0x9000>;
 773                                 interrupts = <0 115 0x04>;
 774                                 gpr = <&gpr>;
 775                                 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 776                                          <&clks IMX6QDL_CLK_HDMI_ISFR>;
 777                                 clock-names = "iahb", "isfr";
 778                                 status = "disabled";
 779
 780                                 port@0 {
 781                                         reg = <0>;
 782
 783                                         hdmi_mux_0: endpoint {
 784                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 785                                         };
 786                                 };
 787
 788                                 port@1 {
 789                                         reg = <1>;
 790
 791                                         hdmi_mux_1: endpoint {
 792                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 793                                         };
 794                                 };
 795                         };
 796
 797                         dcic1: dcic@020e4000 {
 798                                 reg = <0x020e4000 0x4000>;
 799                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 800                         };
 801
 802                         dcic2: dcic@020e8000 {
 803                                 reg = <0x020e8000 0x4000>;
 804                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 805                         };
 806
 807                         sdma: sdma@020ec000 {
 808                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 809                                 reg = <0x020ec000 0x4000>;
 810                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 812                                          <&clks IMX6QDL_CLK_SDMA>;
 813                                 clock-names = "ipg", "ahb";
 814                                 #dma-cells = <3>;
 815                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 816                         };
 817                 };
 818
 819                 aips-bus@02100000 { /* AIPS2 */
 820                         compatible = "fsl,aips-bus", "simple-bus";
 821                         #address-cells = <1>;
 822                         #size-cells = <1>;
 823                         reg = <0x02100000 0x100000>;
 824                         ranges;
 825
 826                         caam@02100000 {
 827                                 reg = <0x02100000 0x40000>;
 828                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 829                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 830                         };
 831
 832                         aipstz@0217c000 { /* AIPSTZ2 */
 833                                 reg = <0x0217c000 0x4000>;
 834                         };
 835
 836                         usbotg: usb@02184000 {
 837                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 838                                 reg = <0x02184000 0x200>;
 839                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 841                                 fsl,usbphy = <&usbphy1>;
 842                                 fsl,usbmisc = <&usbmisc 0>;
 843                                 status = "disabled";
 844                         };
 845
 846                         usbh1: usb@02184200 {
 847                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 848                                 reg = <0x02184200 0x200>;
 849                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 851                                 fsl,usbphy = <&usbphy2>;
 852                                 fsl,usbmisc = <&usbmisc 1>;
 853                                 status = "disabled";
 854                         };
 855
 856                         usbh2: usb@02184400 {
 857                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 858                                 reg = <0x02184400 0x200>;
 859                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 860                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 861                                 fsl,usbmisc = <&usbmisc 2>;
 862                                 status = "disabled";
 863                         };
 864
 865                         usbh3: usb@02184600 {
 866                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 867                                 reg = <0x02184600 0x200>;
 868                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 869                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 870                                 fsl,usbmisc = <&usbmisc 3>;
 871                                 status = "disabled";
 872                         };
 873
 874                         usbmisc: usbmisc@02184800 {
 875                                 #index-cells = <1>;
 876                                 compatible = "fsl,imx6q-usbmisc";
 877                                 reg = <0x02184800 0x200>;
 878                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 879                         };
 880
 881                         fec: ethernet@02188000 {
 882                                 compatible = "fsl,imx6q-fec";
 883                                 reg = <0x02188000 0x4000>;
 884                                 interrupts-extended =
 885                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 886                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 887                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 888                                          <&clks IMX6QDL_CLK_ENET>,
 889                                          <&clks IMX6QDL_CLK_ENET_REF>;
 890                                 clock-names = "ipg", "ahb", "ptp";
 891                                 status = "disabled";
 892                         };
 893
 894                         mlb@0218c000 {
 895                                 reg = <0x0218c000 0x4000>;
 896                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 897                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 898                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 899                         };
 900
 901                         usdhc1: usdhc@02190000 {
 902                                 compatible = "fsl,imx6q-usdhc";
 903                                 reg = <0x02190000 0x4000>;
 904                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 905                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 906                                          <&clks IMX6QDL_CLK_USDHC1>,
 907                                          <&clks IMX6QDL_CLK_USDHC1>;
 908                                 clock-names = "ipg", "ahb", "per";
 909                                 bus-width = <4>;
 910                                 status = "disabled";
 911                         };
 912
 913                         usdhc2: usdhc@02194000 {
 914                                 compatible = "fsl,imx6q-usdhc";
 915                                 reg = <0x02194000 0x4000>;
 916                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 917                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 918                                          <&clks IMX6QDL_CLK_USDHC2>,
 919                                          <&clks IMX6QDL_CLK_USDHC2>;
 920                                 clock-names = "ipg", "ahb", "per";
 921                                 bus-width = <4>;
 922                                 status = "disabled";
 923                         };
 924
 925                         usdhc3: usdhc@02198000 {
 926                                 compatible = "fsl,imx6q-usdhc";
 927                                 reg = <0x02198000 0x4000>;
 928                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 929                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 930                                          <&clks IMX6QDL_CLK_USDHC3>,
 931                                          <&clks IMX6QDL_CLK_USDHC3>;
 932                                 clock-names = "ipg", "ahb", "per";
 933                                 bus-width = <4>;
 934                                 status = "disabled";
 935                         };
 936
 937                         usdhc4: usdhc@0219c000 {
 938                                 compatible = "fsl,imx6q-usdhc";
 939                                 reg = <0x0219c000 0x4000>;
 940                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 941                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 942                                          <&clks IMX6QDL_CLK_USDHC4>,
 943                                          <&clks IMX6QDL_CLK_USDHC4>;
 944                                 clock-names = "ipg", "ahb", "per";
 945                                 bus-width = <4>;
 946                                 status = "disabled";
 947                         };
 948
 949                         i2c1: i2c@021a0000 {
 950                                 #address-cells = <1>;
 951                                 #size-cells = <0>;
 952                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 953                                 reg = <0x021a0000 0x4000>;
 954                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 955                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 956                                 status = "disabled";
 957                         };
 958
 959                         i2c2: i2c@021a4000 {
 960                                 #address-cells = <1>;
 961                                 #size-cells = <0>;
 962                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 963                                 reg = <0x021a4000 0x4000>;
 964                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 965                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 966                                 status = "disabled";
 967                         };
 968
 969                         i2c3: i2c@021a8000 {
 970                                 #address-cells = <1>;
 971                                 #size-cells = <0>;
 972                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 973                                 reg = <0x021a8000 0x4000>;
 974                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 975                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 976                                 status = "disabled";
 977                         };
 978
 979                         romcp@021ac000 {
 980                                 reg = <0x021ac000 0x4000>;
 981                         };
 982
 983                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 984                                 compatible = "fsl,imx6q-mmdc";
 985                                 reg = <0x021b0000 0x4000>;
 986                         };
 987
 988                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 989                                 reg = <0x021b4000 0x4000>;
 990                         };
 991
 992                         weim: weim@021b8000 {
 993                                 compatible = "fsl,imx6q-weim";
 994                                 reg = <0x021b8000 0x4000>;
 995                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 996                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
 997                         };
 998
 999                         ocotp: ocotp@021bc000 {
1000                                 compatible = "fsl,imx6q-ocotp", "syscon";
1001                                 reg = <0x021bc000 0x4000>;
1002                         };
1003
1004                         tzasc@021d0000 { /* TZASC1 */
1005                                 reg = <0x021d0000 0x4000>;
1006                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1007                         };
1008
1009                         tzasc@021d4000 { /* TZASC2 */
1010                                 reg = <0x021d4000 0x4000>;
1011                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1012                         };
1013
1014                         audmux: audmux@021d8000 {
1015                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1016                                 reg = <0x021d8000 0x4000>;
1017                                 status = "disabled";
1018                         };
1019
1020                         mipi_csi: mipi@021dc000 {
1021                                 reg = <0x021dc000 0x4000>;
1022                         };
1023
1024                         mipi_dsi: mipi@021e0000 {
1025                                 #address-cells = <1>;
1026                                 #size-cells = <0>;
1027                                 reg = <0x021e0000 0x4000>;
1028                                 status = "disabled";
1029
1030                                 ports {
1031                                         #address-cells = <1>;
1032                                         #size-cells = <0>;
1033
1034                                         port@0 {
1035                                                 reg = <0>;
1036
1037                                                 mipi_mux_0: endpoint {
1038                                                         remote-endpoint = <&ipu1_di0_mipi>;
1039                                                 };
1040                                         };
1041
1042                                         port@1 {
1043                                                 reg = <1>;
1044
1045                                                 mipi_mux_1: endpoint {
1046                                                         remote-endpoint = <&ipu1_di1_mipi>;
1047                                                 };
1048                                         };
1049                                 };
1050                         };
1051
1052                         vdoa@021e4000 {
1053                                 reg = <0x021e4000 0x4000>;
1054                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1055                         };
1056
1057                         uart2: serial@021e8000 {
1058                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1059                                 reg = <0x021e8000 0x4000>;
1060                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1061                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1062                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1063                                 clock-names = "ipg", "per";
1064                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1065                                 dma-names = "rx", "tx";
1066                                 status = "disabled";
1067                         };
1068
1069                         uart3: serial@021ec000 {
1070                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1071                                 reg = <0x021ec000 0x4000>;
1072                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1073                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1074                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1075                                 clock-names = "ipg", "per";
1076                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1077                                 dma-names = "rx", "tx";
1078                                 status = "disabled";
1079                         };
1080
1081                         uart4: serial@021f0000 {
1082                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1083                                 reg = <0x021f0000 0x4000>;
1084                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1085                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1086                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1087                                 clock-names = "ipg", "per";
1088                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1089                                 dma-names = "rx", "tx";
1090                                 status = "disabled";
1091                         };
1092
1093                         uart5: serial@021f4000 {
1094                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1095                                 reg = <0x021f4000 0x4000>;
1096                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1097                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1098                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1099                                 clock-names = "ipg", "per";
1100                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1101                                 dma-names = "rx", "tx";
1102                                 status = "disabled";
1103                         };
1104                 };
1105
1106                 ipu1: ipu@02400000 {
1107                         #address-cells = <1>;
1108                         #size-cells = <0>;
1109                         compatible = "fsl,imx6q-ipu";
1110                         reg = <0x02400000 0x400000>;
1111                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1112                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1113                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1114                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1115                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1116                         clock-names = "bus", "di0", "di1";
1117                         resets = <&src 2>;
1118
1119                         ipu1_csi0: port@0 {
1120                                 reg = <0>;
1121                         };
1122
1123                         ipu1_csi1: port@1 {
1124                                 reg = <1>;
1125                         };
1126
1127                         ipu1_di0: port@2 {
1128                                 #address-cells = <1>;
1129                                 #size-cells = <0>;
1130                                 reg = <2>;
1131
1132                                 ipu1_di0_disp0: endpoint@0 {
1133                                 };
1134
1135                                 ipu1_di0_hdmi: endpoint@1 {
1136                                         remote-endpoint = <&hdmi_mux_0>;
1137                                 };
1138
1139                                 ipu1_di0_mipi: endpoint@2 {
1140                                         remote-endpoint = <&mipi_mux_0>;
1141                                 };
1142
1143                                 ipu1_di0_lvds0: endpoint@3 {
1144                                         remote-endpoint = <&lvds0_mux_0>;
1145                                 };
1146
1147                                 ipu1_di0_lvds1: endpoint@4 {
1148                                         remote-endpoint = <&lvds1_mux_0>;
1149                                 };
1150                         };
1151
1152                         ipu1_di1: port@3 {
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155                                 reg = <3>;
1156
1157                                 ipu1_di0_disp1: endpoint@0 {
1158                                 };
1159
1160                                 ipu1_di1_hdmi: endpoint@1 {
1161                                         remote-endpoint = <&hdmi_mux_1>;
1162                                 };
1163
1164                                 ipu1_di1_mipi: endpoint@2 {
1165                                         remote-endpoint = <&mipi_mux_1>;
1166                                 };
1167
1168                                 ipu1_di1_lvds0: endpoint@3 {
1169                                         remote-endpoint = <&lvds0_mux_1>;
1170                                 };
1171
1172                                 ipu1_di1_lvds1: endpoint@4 {
1173                                         remote-endpoint = <&lvds1_mux_1>;
1174                                 };
1175                         };
1176                 };
1177         };
1178 };