arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi

   1 /*
   2  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 / {
  13         chosen {
  14                 linux,stdout-path = &uart4;
  15         };
  16 };
  17
  18 &fec {
  19         status = "okay";
  20 };
  21
  22 &gpmi {
  23         status = "okay";
  24 };
  25
  26 &hdmi {
  27         status = "okay";
  28 };
  29
  30 &i2c2 {
  31         pinctrl-names = "default";
  32         pinctrl-0 = <&pinctrl_i2c2>;
  33         clock-frequency = <100000>;
  34         status = "okay";
  35
  36         tlv320@18 {
  37                 compatible = "ti,tlv320aic3x";
  38                 reg = <0x18>;
  39         };
  40
  41         stmpe@41 {
  42                 compatible = "st,stmpe811";
  43                 reg = <0x41>;
  44         };
  45
  46         rtc@51 {
  47                 compatible = "nxp,rtc8564";
  48                 reg = <0x51>;
  49         };
  50
  51         adc@64 {
  52                 compatible = "maxim,max1037";
  53                 reg = <0x64>;
  54         };
  55 };
  56
  57 &i2c3 {
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_i2c3>;
  60         clock-frequency = <100000>;
  61         status = "okay";
  62 };
  63
  64 &uart3 {
  65         status = "okay";
  66 };
  67
  68 &uart4 {
  69         status = "okay";
  70 };
  71
  72 &usbh1 {
  73         status = "okay";
  74 };
  75
  76 &usbotg {
  77         status = "okay";
  78 };
  79
  80 &usdhc2 {
  81         status = "okay";
  82 };
  83
  84 &usdhc3 {
  85         status = "okay";
  86 };
  87
  88 &iomuxc {
  89         pinctrl_i2c2: i2c2grp {
  90                 fsl,pins = <
  91                         MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
  92                         MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
  93                 >;
  94         };
  95
  96         pinctrl_i2c3: i2c3grp {
  97                 fsl,pins = <
  98                         MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
  99                         MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 100                 >;
 101         };
 102 };