2 * Copyright (C) 2013,2014 Russell King
4 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
17 * This file is distributed in the hope that it will be useful
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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43 * OTHER DEALINGS IN THE SOFTWARE.
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
49 phy-reset-duration = <2>;
50 phy-reset-gpios = <&gpio4 15 0>;
56 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
58 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
59 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
61 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
62 /* AR8035 interrupt */
63 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
64 /* GPIO16 -> AR8035 25MHz */
65 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
66 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
67 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
68 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
69 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
70 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
71 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
72 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
73 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
74 /* AR8035 pin strapping: IO voltage: pull up */
75 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
76 /* AR8035 pin strapping: PHYADDR#0: pull down */
77 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
78 /* AR8035 pin strapping: PHYADDR#1: pull down */
79 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
80 /* AR8035 pin strapping: MODE#1: pull up */
81 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
82 /* AR8035 pin strapping: MODE#3: pull up */
83 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
84 /* AR8035 pin strapping: MODE#0: pull down */
85 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
88 * As the RMII pins are also connected to RGMII
89 * so that an AR8030 can be placed, set these
90 * to high-z with the same pulls as above.
91 * Use the GPIO settings to avoid changing the
92 * input select registers.
94 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000
95 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000
96 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000