2 * Copyright 2013 Pavel Machek <pavel@denx.de>
4 * The code contained herein is licensed under the GNU General Public
12 model = "MicroSys sbc6x board";
13 compatible = "microsys,sbc6x", "fsl,imx6q";
16 reg = <0x10000000 0x80000000>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_enet>;
30 pinctrl_enet: enetgrp {
32 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
33 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
34 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
35 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
36 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
37 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
38 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
39 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
40 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
41 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
42 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
43 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
44 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
46 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
47 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
51 pinctrl_uart1: uart1grp {
53 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
54 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
58 pinctrl_usbotg: usbotggrp {
60 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
64 pinctrl_usdhc3: usdhc3grp {
66 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
67 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
68 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
69 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
70 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
71 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_uart1>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usbotg>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_usdhc3>;