arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi

   1 /*
   2  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "imx6q.dtsi"
  13
  14 / {
  15         model = "Phytec phyFLEX-i.MX6 Ouad";
  16         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
  17
  18         memory {
  19                 reg = <0x10000000 0x80000000>;
  20         };
  21 };
  22
  23 &ecspi3 {
  24         pinctrl-names = "default";
  25         pinctrl-0 = <&pinctrl_ecspi3>;
  26         status = "okay";
  27         fsl,spi-num-chipselects = <1>;
  28         cs-gpios = <&gpio4 24 0>;
  29
  30         flash@0 {
  31                 compatible = "m25p80";
  32                 spi-max-frequency = <20000000>;
  33                 reg = <0>;
  34         };
  35 };
  36
  37 &i2c1 {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_i2c1>;
  40         status = "okay";
  41
  42         eeprom@50 {
  43                 compatible = "atmel,24c32";
  44                 reg = <0x50>;
  45         };
  46
  47         pmic@58 {
  48                 compatible = "dialog,da9063";
  49                 reg = <0x58>;
  50                 interrupt-parent = <&gpio4>;
  51                 interrupts = <17 0x8>; /* active-low GPIO4_17 */
  52
  53                 regulators {
  54                         vddcore_reg: bcore1 {
  55                                 regulator-min-microvolt = <730000>;
  56                                 regulator-max-microvolt = <1380000>;
  57                                 regulator-always-on;
  58                         };
  59
  60                         vddsoc_reg: bcore2 {
  61                                 regulator-min-microvolt = <730000>;
  62                                 regulator-max-microvolt = <1380000>;
  63                                 regulator-always-on;
  64                         };
  65
  66                         vdd_ddr3_reg: bpro {
  67                                 regulator-min-microvolt = <1500000>;
  68                                 regulator-max-microvolt = <1500000>;
  69                                 regulator-always-on;
  70                         };
  71
  72                         vdd_3v3_reg: bperi {
  73                                 regulator-min-microvolt = <3300000>;
  74                                 regulator-max-microvolt = <3300000>;
  75                                 regulator-always-on;
  76                         };
  77
  78                         vdd_buckmem_reg: bmem {
  79                                 regulator-min-microvolt = <3300000>;
  80                                 regulator-max-microvolt = <3300000>;
  81                                 regulator-always-on;
  82                         };
  83
  84                         vdd_eth_reg: bio {
  85                                 regulator-min-microvolt = <1200000>;
  86                                 regulator-max-microvolt = <1200000>;
  87                                 regulator-always-on;
  88                         };
  89
  90                         vdd_eth_io_reg: ldo4 {
  91                                 regulator-min-microvolt = <2500000>;
  92                                 regulator-max-microvolt = <2500000>;
  93                                 regulator-always-on;
  94                         };
  95
  96                         vdd_mx6_snvs_reg: ldo5 {
  97                                 regulator-min-microvolt = <3000000>;
  98                                 regulator-max-microvolt = <3000000>;
  99                                 regulator-always-on;
 100                         };
 101
 102                         vdd_3v3_pmic_io_reg: ldo6 {
 103                                 regulator-min-microvolt = <3300000>;
 104                                 regulator-max-microvolt = <3300000>;
 105                                 regulator-always-on;
 106                         };
 107
 108                         vdd_sd0_reg: ldo9 {
 109                                 regulator-min-microvolt = <3300000>;
 110                                 regulator-max-microvolt = <3300000>;
 111                         };
 112
 113                         vdd_sd1_reg: ldo10 {
 114                                 regulator-min-microvolt = <3300000>;
 115                                 regulator-max-microvolt = <3300000>;
 116                         };
 117
 118                         vdd_mx6_high_reg: ldo11 {
 119                                 regulator-min-microvolt = <3000000>;
 120                                 regulator-max-microvolt = <3000000>;
 121                                 regulator-always-on;
 122                         };
 123                 };
 124         };
 125 };
 126
 127 &iomuxc {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_hog>;
 130
 131         imx6q-phytec-pfla02 {
 132                 pinctrl_hog: hoggrp {
 133                         fsl,pins = <
 134                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 135                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
 136                                 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
 137                         >;
 138                 };
 139
 140                 pinctrl_ecspi3: ecspi3grp {
 141                         fsl,pins = <
 142                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 143                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 144                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 145                         >;
 146                 };
 147
 148                 pinctrl_enet: enetgrp {
 149                         fsl,pins = <
 150                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 151                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 152                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 153                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 154                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 155                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 156                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 157                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 158                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 159                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 160                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 161                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 162                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 163                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 164                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 165                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 166                         >;
 167                 };
 168
 169                 pinctrl_i2c1: i2c1grp {
 170                         fsl,pins = <
 171                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 172                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 173                         >;
 174                 };
 175
 176                 pinctrl_uart4: uart4grp {
 177                         fsl,pins = <
 178                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 179                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 180                         >;
 181                 };
 182
 183                 pinctrl_usdhc2: usdhc2grp {
 184                         fsl,pins = <
 185                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 186                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 187                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 188                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 189                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 190                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 191                         >;
 192                 };
 193
 194                 pinctrl_usdhc3: usdhc3grp {
 195                         fsl,pins = <
 196                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 197                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 198                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 199                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 200                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 201                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 202                         >;
 203                 };
 204
 205                 pinctrl_usdhc3_cdwp: usdhc3cdwp {
 206                         fsl,pins = <
 207                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 208                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 209                         >;
 210                 };
 211         };
 212 };
 213
 214 &fec {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_enet>;
 217         phy-mode = "rgmii";
 218         phy-reset-gpios = <&gpio3 23 0>;
 219         status = "disabled";
 220 };
 221
 222 &uart4 {
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_uart4>;
 225         status = "disabled";
 226 };
 227
 228 &usdhc2 {
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&pinctrl_usdhc2>;
 231         cd-gpios = <&gpio1 4 0>;
 232         wp-gpios = <&gpio1 2 0>;
 233         status = "disabled";
 234 };
 235
 236 &usdhc3 {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&pinctrl_usdhc3
 239                      &pinctrl_usdhc3_cdwp>;
 240         cd-gpios = <&gpio1 27 0>;
 241         wp-gpios = <&gpio1 29 0>;
 242         status = "disabled";
 243 };