arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         tzic: tz-interrupt-controller@0fffc000 {
  32                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  33                 interrupt-controller;
  34                 #interrupt-cells = <1>;
  35                 reg = <0x0fffc000 0x4000>;
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 ckil {
  43                         compatible = "fsl,imx-ckil", "fixed-clock";
  44                         clock-frequency = <32768>;
  45                 };
  46
  47                 ckih1 {
  48                         compatible = "fsl,imx-ckih1", "fixed-clock";
  49                         clock-frequency = <22579200>;
  50                 };
  51
  52                 ckih2 {
  53                         compatible = "fsl,imx-ckih2", "fixed-clock";
  54                         clock-frequency = <0>;
  55                 };
  56
  57                 osc {
  58                         compatible = "fsl,imx-osc", "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61         };
  62
  63         soc {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 compatible = "simple-bus";
  67                 interrupt-parent = <&tzic>;
  68                 ranges;
  69
  70                 ipu: ipu@18000000 {
  71                         #crtc-cells = <1>;
  72                         compatible = "fsl,imx53-ipu";
  73                         reg = <0x18000000 0x080000000>;
  74                         interrupts = <11 10>;
  75                 };
  76
  77                 aips@50000000 { /* AIPS1 */
  78                         compatible = "fsl,aips-bus", "simple-bus";
  79                         #address-cells = <1>;
  80                         #size-cells = <1>;
  81                         reg = <0x50000000 0x10000000>;
  82                         ranges;
  83
  84                         spba@50000000 {
  85                                 compatible = "fsl,spba-bus", "simple-bus";
  86                                 #address-cells = <1>;
  87                                 #size-cells = <1>;
  88                                 reg = <0x50000000 0x40000>;
  89                                 ranges;
  90
  91                                 esdhc@50004000 { /* ESDHC1 */
  92                                         compatible = "fsl,imx53-esdhc";
  93                                         reg = <0x50004000 0x4000>;
  94                                         interrupts = <1>;
  95                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
  96                                         clock-names = "ipg", "ahb", "per";
  97                                         status = "disabled";
  98                                 };
  99
 100                                 esdhc@50008000 { /* ESDHC2 */
 101                                         compatible = "fsl,imx53-esdhc";
 102                                         reg = <0x50008000 0x4000>;
 103                                         interrupts = <2>;
 104                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 105                                         clock-names = "ipg", "ahb", "per";
 106                                         status = "disabled";
 107                                 };
 108
 109                                 uart3: serial@5000c000 {
 110                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 111                                         reg = <0x5000c000 0x4000>;
 112                                         interrupts = <33>;
 113                                         clocks = <&clks 32>, <&clks 33>;
 114                                         clock-names = "ipg", "per";
 115                                         status = "disabled";
 116                                 };
 117
 118                                 ecspi@50010000 { /* ECSPI1 */
 119                                         #address-cells = <1>;
 120                                         #size-cells = <0>;
 121                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 122                                         reg = <0x50010000 0x4000>;
 123                                         interrupts = <36>;
 124                                         clocks = <&clks 51>, <&clks 52>;
 125                                         clock-names = "ipg", "per";
 126                                         status = "disabled";
 127                                 };
 128
 129                                 ssi2: ssi@50014000 {
 130                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 131                                         reg = <0x50014000 0x4000>;
 132                                         interrupts = <30>;
 133                                         clocks = <&clks 49>;
 134                                         fsl,fifo-depth = <15>;
 135                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 136                                         status = "disabled";
 137                                 };
 138
 139                                 esdhc@50020000 { /* ESDHC3 */
 140                                         compatible = "fsl,imx53-esdhc";
 141                                         reg = <0x50020000 0x4000>;
 142                                         interrupts = <3>;
 143                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 144                                         clock-names = "ipg", "ahb", "per";
 145                                         status = "disabled";
 146                                 };
 147
 148                                 esdhc@50024000 { /* ESDHC4 */
 149                                         compatible = "fsl,imx53-esdhc";
 150                                         reg = <0x50024000 0x4000>;
 151                                         interrupts = <4>;
 152                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 153                                         clock-names = "ipg", "ahb", "per";
 154                                         status = "disabled";
 155                                 };
 156                         };
 157
 158                         usb@53f80000 {
 159                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 160                                 reg = <0x53f80000 0x0200>;
 161                                 interrupts = <18>;
 162                                 status = "disabled";
 163                         };
 164
 165                         usb@53f80200 {
 166                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 167                                 reg = <0x53f80200 0x0200>;
 168                                 interrupts = <14>;
 169                                 status = "disabled";
 170                         };
 171
 172                         usb@53f80400 {
 173                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 174                                 reg = <0x53f80400 0x0200>;
 175                                 interrupts = <16>;
 176                                 status = "disabled";
 177                         };
 178
 179                         usb@53f80600 {
 180                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 181                                 reg = <0x53f80600 0x0200>;
 182                                 interrupts = <17>;
 183                                 status = "disabled";
 184                         };
 185
 186                         gpio1: gpio@53f84000 {
 187                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 188                                 reg = <0x53f84000 0x4000>;
 189                                 interrupts = <50 51>;
 190                                 gpio-controller;
 191                                 #gpio-cells = <2>;
 192                                 interrupt-controller;
 193                                 #interrupt-cells = <2>;
 194                         };
 195
 196                         gpio2: gpio@53f88000 {
 197                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 198                                 reg = <0x53f88000 0x4000>;
 199                                 interrupts = <52 53>;
 200                                 gpio-controller;
 201                                 #gpio-cells = <2>;
 202                                 interrupt-controller;
 203                                 #interrupt-cells = <2>;
 204                         };
 205
 206                         gpio3: gpio@53f8c000 {
 207                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 208                                 reg = <0x53f8c000 0x4000>;
 209                                 interrupts = <54 55>;
 210                                 gpio-controller;
 211                                 #gpio-cells = <2>;
 212                                 interrupt-controller;
 213                                 #interrupt-cells = <2>;
 214                         };
 215
 216                         gpio4: gpio@53f90000 {
 217                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 218                                 reg = <0x53f90000 0x4000>;
 219                                 interrupts = <56 57>;
 220                                 gpio-controller;
 221                                 #gpio-cells = <2>;
 222                                 interrupt-controller;
 223                                 #interrupt-cells = <2>;
 224                         };
 225
 226                         wdog@53f98000 { /* WDOG1 */
 227                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 228                                 reg = <0x53f98000 0x4000>;
 229                                 interrupts = <58>;
 230                                 clocks = <&clks 0>;
 231                         };
 232
 233                         wdog@53f9c000 { /* WDOG2 */
 234                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 235                                 reg = <0x53f9c000 0x4000>;
 236                                 interrupts = <59>;
 237                                 clocks = <&clks 0>;
 238                                 status = "disabled";
 239                         };
 240
 241                         iomuxc@53fa8000 {
 242                                 compatible = "fsl,imx53-iomuxc";
 243                                 reg = <0x53fa8000 0x4000>;
 244
 245                                 audmux {
 246                                         pinctrl_audmux_1: audmuxgrp-1 {
 247                                                 fsl,pins = <
 248                                                         10 0x80000000   /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
 249                                                         17 0x80000000   /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
 250                                                         23 0x80000000   /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
 251                                                         30 0x80000000   /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
 252                                                 >;
 253                                         };
 254                                 };
 255
 256                                 fec {
 257                                         pinctrl_fec_1: fecgrp-1 {
 258                                                 fsl,pins = <
 259                                                         820 0x80000000  /* MX53_PAD_FEC_MDC__FEC_MDC */
 260                                                         779 0x80000000  /* MX53_PAD_FEC_MDIO__FEC_MDIO */
 261                                                         786 0x80000000  /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
 262                                                         791 0x80000000  /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
 263                                                         796 0x80000000  /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
 264                                                         799 0x80000000  /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
 265                                                         804 0x80000000  /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
 266                                                         808 0x80000000  /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
 267                                                         811 0x80000000  /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
 268                                                         816 0x80000000  /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
 269                                                 >;
 270                                         };
 271                                 };
 272
 273                                 ecspi1 {
 274                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 275                                                 fsl,pins = <
 276                                                         433 0x80000000  /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
 277                                                         439 0x80000000  /* MX53_PAD_EIM_D17__ECSPI1_MISO */
 278                                                         445 0x80000000  /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
 279                                                 >;
 280                                         };
 281                                 };
 282
 283                                 esdhc1 {
 284                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 285                                                 fsl,pins = <
 286                                                         995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
 287                                                         1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
 288                                                         1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
 289                                                         1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
 290                                                         1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
 291                                                         1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 292                                                 >;
 293                                         };
 294
 295                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 296                                                 fsl,pins = <
 297                                                         995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
 298                                                         1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
 299                                                         1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
 300                                                         1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
 301                                                         941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
 302                                                         948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
 303                                                         955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
 304                                                         962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
 305                                                         1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
 306                                                         1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 307                                                 >;
 308                                         };
 309                                 };
 310
 311                                 esdhc2 {
 312                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 313                                                 fsl,pins = <
 314                                                         1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
 315                                                         1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
 316                                                         1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
 317                                                         1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
 318                                                         1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
 319                                                         1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
 320                                                 >;
 321                                         };
 322                                 };
 323
 324                                 esdhc3 {
 325                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 326                                                 fsl,pins = <
 327                                                         943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
 328                                                         950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
 329                                                         957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
 330                                                         964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
 331                                                         893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
 332                                                         900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
 333                                                         906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
 334                                                         912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
 335                                                         857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
 336                                                         863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
 337                                                 >;
 338                                         };
 339                                 };
 340
 341                                 i2c1 {
 342                                         pinctrl_i2c1_1: i2c1grp-1 {
 343                                                 fsl,pins = <
 344                                                         333 0xc0000000  /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
 345                                                         341 0xc0000000  /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
 346                                                 >;
 347                                         };
 348                                 };
 349
 350                                 i2c2 {
 351                                         pinctrl_i2c2_1: i2c2grp-1 {
 352                                                 fsl,pins = <
 353                                                         61 0xc0000000   /* MX53_PAD_KEY_ROW3__I2C2_SDA */
 354                                                         53 0xc0000000   /* MX53_PAD_KEY_COL3__I2C2_SCL */
 355                                                 >;
 356                                         };
 357                                 };
 358
 359                                 uart1 {
 360                                         pinctrl_uart1_1: uart1grp-1 {
 361                                                 fsl,pins = <
 362                                                         346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
 363                                                         354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
 364                                                 >;
 365                                         };
 366
 367                                         pinctrl_uart1_2: uart1grp-2 {
 368                                                 fsl,pins = <
 369                                                         828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
 370                                                         832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
 371                                                 >;
 372                                         };
 373                                 };
 374
 375                                 uart2 {
 376                                         pinctrl_uart2_1: uart2grp-1 {
 377                                                 fsl,pins = <
 378                                                         841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
 379                                                         836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
 380                                                 >;
 381                                         };
 382                                 };
 383
 384                                 uart3 {
 385                                         pinctrl_uart3_1: uart3grp-1 {
 386                                                 fsl,pins = <
 387                                                         884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
 388                                                         888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
 389                                                         875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
 390                                                         880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
 391                                                 >;
 392                                         };
 393                                 };
 394                         };
 395
 396                         uart1: serial@53fbc000 {
 397                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 398                                 reg = <0x53fbc000 0x4000>;
 399                                 interrupts = <31>;
 400                                 clocks = <&clks 28>, <&clks 29>;
 401                                 clock-names = "ipg", "per";
 402                                 status = "disabled";
 403                         };
 404
 405                         uart2: serial@53fc0000 {
 406                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 407                                 reg = <0x53fc0000 0x4000>;
 408                                 interrupts = <32>;
 409                                 clocks = <&clks 30>, <&clks 31>;
 410                                 clock-names = "ipg", "per";
 411                                 status = "disabled";
 412                         };
 413
 414                         can1: can@53fc8000 {
 415                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 416                                 reg = <0x53fc8000 0x4000>;
 417                                 interrupts = <82>;
 418                                 clocks = <&clks 158>, <&clks 157>;
 419                                 clock-names = "ipg", "per";
 420                                 status = "disabled";
 421                         };
 422
 423                         can2: can@53fcc000 {
 424                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 425                                 reg = <0x53fcc000 0x4000>;
 426                                 interrupts = <83>;
 427                                 clocks = <&clks 158>, <&clks 157>;
 428                                 clock-names = "ipg", "per";
 429                                 status = "disabled";
 430                         };
 431
 432                         clks: ccm@53fd4000{
 433                                 compatible = "fsl,imx53-ccm";
 434                                 reg = <0x53fd4000 0x4000>;
 435                                 interrupts = <0 71 0x04 0 72 0x04>;
 436                                 #clock-cells = <1>;
 437                         };
 438
 439                         gpio5: gpio@53fdc000 {
 440                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 441                                 reg = <0x53fdc000 0x4000>;
 442                                 interrupts = <103 104>;
 443                                 gpio-controller;
 444                                 #gpio-cells = <2>;
 445                                 interrupt-controller;
 446                                 #interrupt-cells = <2>;
 447                         };
 448
 449                         gpio6: gpio@53fe0000 {
 450                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 451                                 reg = <0x53fe0000 0x4000>;
 452                                 interrupts = <105 106>;
 453                                 gpio-controller;
 454                                 #gpio-cells = <2>;
 455                                 interrupt-controller;
 456                                 #interrupt-cells = <2>;
 457                         };
 458
 459                         gpio7: gpio@53fe4000 {
 460                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x53fe4000 0x4000>;
 462                                 interrupts = <107 108>;
 463                                 gpio-controller;
 464                                 #gpio-cells = <2>;
 465                                 interrupt-controller;
 466                                 #interrupt-cells = <2>;
 467                         };
 468
 469                         i2c@53fec000 { /* I2C3 */
 470                                 #address-cells = <1>;
 471                                 #size-cells = <0>;
 472                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 473                                 reg = <0x53fec000 0x4000>;
 474                                 interrupts = <64>;
 475                                 clocks = <&clks 88>;
 476                                 status = "disabled";
 477                         };
 478
 479                         uart4: serial@53ff0000 {
 480                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 481                                 reg = <0x53ff0000 0x4000>;
 482                                 interrupts = <13>;
 483                                 clocks = <&clks 65>, <&clks 66>;
 484                                 clock-names = "ipg", "per";
 485                                 status = "disabled";
 486                         };
 487                 };
 488
 489                 aips@60000000 { /* AIPS2 */
 490                         compatible = "fsl,aips-bus", "simple-bus";
 491                         #address-cells = <1>;
 492                         #size-cells = <1>;
 493                         reg = <0x60000000 0x10000000>;
 494                         ranges;
 495
 496                         uart5: serial@63f90000 {
 497                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 498                                 reg = <0x63f90000 0x4000>;
 499                                 interrupts = <86>;
 500                                 clocks = <&clks 67>, <&clks 68>;
 501                                 clock-names = "ipg", "per";
 502                                 status = "disabled";
 503                         };
 504
 505                         ecspi@63fac000 { /* ECSPI2 */
 506                                 #address-cells = <1>;
 507                                 #size-cells = <0>;
 508                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 509                                 reg = <0x63fac000 0x4000>;
 510                                 interrupts = <37>;
 511                                 clocks = <&clks 53>, <&clks 54>;
 512                                 clock-names = "ipg", "per";
 513                                 status = "disabled";
 514                         };
 515
 516                         sdma@63fb0000 {
 517                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 518                                 reg = <0x63fb0000 0x4000>;
 519                                 interrupts = <6>;
 520                                 clocks = <&clks 56>, <&clks 56>;
 521                                 clock-names = "ipg", "ahb";
 522                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 523                         };
 524
 525                         cspi@63fc0000 {
 526                                 #address-cells = <1>;
 527                                 #size-cells = <0>;
 528                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 529                                 reg = <0x63fc0000 0x4000>;
 530                                 interrupts = <38>;
 531                                 clocks = <&clks 55>, <&clks 0>;
 532                                 clock-names = "ipg", "per";
 533                                 status = "disabled";
 534                         };
 535
 536                         i2c@63fc4000 { /* I2C2 */
 537                                 #address-cells = <1>;
 538                                 #size-cells = <0>;
 539                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 540                                 reg = <0x63fc4000 0x4000>;
 541                                 interrupts = <63>;
 542                                 clocks = <&clks 35>;
 543                                 status = "disabled";
 544                         };
 545
 546                         i2c@63fc8000 { /* I2C1 */
 547                                 #address-cells = <1>;
 548                                 #size-cells = <0>;
 549                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 550                                 reg = <0x63fc8000 0x4000>;
 551                                 interrupts = <62>;
 552                                 clocks = <&clks 34>;
 553                                 status = "disabled";
 554                         };
 555
 556                         ssi1: ssi@63fcc000 {
 557                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 558                                 reg = <0x63fcc000 0x4000>;
 559                                 interrupts = <29>;
 560                                 clocks = <&clks 48>;
 561                                 fsl,fifo-depth = <15>;
 562                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 563                                 status = "disabled";
 564                         };
 565
 566                         audmux@63fd0000 {
 567                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 568                                 reg = <0x63fd0000 0x4000>;
 569                                 status = "disabled";
 570                         };
 571
 572                         nand@63fdb000 {
 573                                 compatible = "fsl,imx53-nand";
 574                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 575                                 interrupts = <8>;
 576                                 clocks = <&clks 60>;
 577                                 status = "disabled";
 578                         };
 579
 580                         ssi3: ssi@63fe8000 {
 581                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 582                                 reg = <0x63fe8000 0x4000>;
 583                                 interrupts = <96>;
 584                                 clocks = <&clks 50>;
 585                                 fsl,fifo-depth = <15>;
 586                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 587                                 status = "disabled";
 588                         };
 589
 590                         ethernet@63fec000 {
 591                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 592                                 reg = <0x63fec000 0x4000>;
 593                                 interrupts = <87>;
 594                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 595                                 clock-names = "ipg", "ahb", "ptp";
 596                                 status = "disabled";
 597                         };
 598                 };
 599         };
 600 };