2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
70 aips@50000000 { /* AIPS1 */
71 compatible = "fsl,aips-bus", "simple-bus";
74 reg = <0x50000000 0x10000000>;
78 compatible = "fsl,spba-bus", "simple-bus";
81 reg = <0x50000000 0x40000>;
84 esdhc@50004000 { /* ESDHC1 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50004000 0x4000>;
91 esdhc@50008000 { /* ESDHC2 */
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50008000 0x4000>;
98 uart3: serial@5000c000 {
99 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
100 reg = <0x5000c000 0x4000>;
105 ecspi@50010000 { /* ECSPI1 */
106 #address-cells = <1>;
108 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
109 reg = <0x50010000 0x4000>;
115 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
116 reg = <0x50014000 0x4000>;
118 fsl,fifo-depth = <15>;
119 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
123 esdhc@50020000 { /* ESDHC3 */
124 compatible = "fsl,imx53-esdhc";
125 reg = <0x50020000 0x4000>;
130 esdhc@50024000 { /* ESDHC4 */
131 compatible = "fsl,imx53-esdhc";
132 reg = <0x50024000 0x4000>;
139 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
140 reg = <0x53f80000 0x0200>;
146 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
147 reg = <0x53f80200 0x0200>;
153 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
154 reg = <0x53f80400 0x0200>;
160 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
161 reg = <0x53f80600 0x0200>;
166 gpio1: gpio@53f84000 {
167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
168 reg = <0x53f84000 0x4000>;
169 interrupts = <50 51>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
176 gpio2: gpio@53f88000 {
177 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
178 reg = <0x53f88000 0x4000>;
179 interrupts = <52 53>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
186 gpio3: gpio@53f8c000 {
187 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
188 reg = <0x53f8c000 0x4000>;
189 interrupts = <54 55>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
196 gpio4: gpio@53f90000 {
197 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
198 reg = <0x53f90000 0x4000>;
199 interrupts = <56 57>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
206 wdog@53f98000 { /* WDOG1 */
207 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
208 reg = <0x53f98000 0x4000>;
212 wdog@53f9c000 { /* WDOG2 */
213 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
214 reg = <0x53f9c000 0x4000>;
220 compatible = "fsl,imx53-iomuxc";
221 reg = <0x53fa8000 0x4000>;
224 pinctrl_audmux_1: audmuxgrp-1 {
226 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
227 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
228 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
229 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
235 pinctrl_fec_1: fecgrp-1 {
237 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
238 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
239 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
240 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
241 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
242 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
243 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
244 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
245 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
246 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
252 pinctrl_ecspi1_1: ecspi1grp-1 {
254 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
255 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
256 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
262 pinctrl_esdhc1_1: esdhc1grp-1 {
264 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
265 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
266 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
267 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
268 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
269 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
273 pinctrl_esdhc1_2: esdhc1grp-2 {
275 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
276 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
277 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
278 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
279 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
280 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
281 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
282 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
283 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
284 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
290 pinctrl_esdhc2_1: esdhc2grp-1 {
292 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
293 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
294 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
295 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
296 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
297 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
303 pinctrl_esdhc3_1: esdhc3grp-1 {
305 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
306 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
307 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
308 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
309 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
310 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
311 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
312 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
313 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
314 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
320 pinctrl_i2c1_1: i2c1grp-1 {
322 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
323 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
329 pinctrl_i2c2_1: i2c2grp-1 {
331 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
332 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
338 pinctrl_uart1_1: uart1grp-1 {
340 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
341 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
345 pinctrl_uart1_2: uart1grp-2 {
347 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
348 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
354 pinctrl_uart2_1: uart2grp-1 {
356 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
357 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
363 pinctrl_uart3_1: uart3grp-1 {
365 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
366 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
367 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
368 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
374 uart1: serial@53fbc000 {
375 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
376 reg = <0x53fbc000 0x4000>;
381 uart2: serial@53fc0000 {
382 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
383 reg = <0x53fc0000 0x4000>;
389 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
390 reg = <0x53fc8000 0x4000>;
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fcc000 0x4000>;
402 gpio5: gpio@53fdc000 {
403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
404 reg = <0x53fdc000 0x4000>;
405 interrupts = <103 104>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
412 gpio6: gpio@53fe0000 {
413 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
414 reg = <0x53fe0000 0x4000>;
415 interrupts = <105 106>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
422 gpio7: gpio@53fe4000 {
423 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
424 reg = <0x53fe4000 0x4000>;
425 interrupts = <107 108>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
432 i2c@53fec000 { /* I2C3 */
433 #address-cells = <1>;
435 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
436 reg = <0x53fec000 0x4000>;
441 uart4: serial@53ff0000 {
442 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
443 reg = <0x53ff0000 0x4000>;
449 aips@60000000 { /* AIPS2 */
450 compatible = "fsl,aips-bus", "simple-bus";
451 #address-cells = <1>;
453 reg = <0x60000000 0x10000000>;
456 uart5: serial@63f90000 {
457 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
458 reg = <0x63f90000 0x4000>;
463 ecspi@63fac000 { /* ECSPI2 */
464 #address-cells = <1>;
466 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
467 reg = <0x63fac000 0x4000>;
473 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
474 reg = <0x63fb0000 0x4000>;
476 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
480 #address-cells = <1>;
482 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
483 reg = <0x63fc0000 0x4000>;
488 i2c@63fc4000 { /* I2C2 */
489 #address-cells = <1>;
491 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
492 reg = <0x63fc4000 0x4000>;
497 i2c@63fc8000 { /* I2C1 */
498 #address-cells = <1>;
500 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
501 reg = <0x63fc8000 0x4000>;
507 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
508 reg = <0x63fcc000 0x4000>;
510 fsl,fifo-depth = <15>;
511 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
516 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
517 reg = <0x63fd0000 0x4000>;
522 compatible = "fsl,imx53-nand";
523 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
529 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
530 reg = <0x63fe8000 0x4000>;
532 fsl,fifo-depth = <15>;
533 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
538 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
539 reg = <0x63fec000 0x4000>;