2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
51 compatible = "arm,cortex-a8";
57 compatible = "fsl,imx-display-subsystem";
58 ports = <&ipu_di0>, <&ipu_di1>;
61 tzic: tz-interrupt-controller@0fffc000 {
62 compatible = "fsl,imx53-tzic", "fsl,tzic";
64 #interrupt-cells = <1>;
65 reg = <0x0fffc000 0x4000>;
73 compatible = "fsl,imx-ckil", "fixed-clock";
75 clock-frequency = <32768>;
79 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <22579200>;
85 compatible = "fsl,imx-ckih2", "fixed-clock";
87 clock-frequency = <0>;
91 compatible = "fsl,imx-osc", "fixed-clock";
93 clock-frequency = <24000000>;
100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>;
104 sata: sata@10000000 {
105 compatible = "fsl,imx53-ahci";
106 reg = <0x10000000 0x1000>;
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
111 clock-names = "sata", "sata_ref", "ahb";
116 #address-cells = <1>;
118 compatible = "fsl,imx53-ipu";
119 reg = <0x18000000 0x08000000>;
120 interrupts = <11 10>;
121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
124 clock-names = "bus", "di0", "di1";
128 #address-cells = <1>;
132 ipu_di0_disp0: endpoint@0 {
136 ipu_di0_lvds0: endpoint@1 {
138 remote-endpoint = <&lvds0_in>;
143 #address-cells = <1>;
147 ipu_di1_disp1: endpoint@0 {
151 ipu_di1_lvds1: endpoint@1 {
153 remote-endpoint = <&lvds1_in>;
156 ipu_di1_tve: endpoint@2 {
158 remote-endpoint = <&tve_in>;
163 aips@50000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
167 reg = <0x50000000 0x10000000>;
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
174 reg = <0x50000000 0x40000>;
177 esdhc1: esdhc@50004000 {
178 compatible = "fsl,imx53-esdhc";
179 reg = <0x50004000 0x4000>;
181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
184 clock-names = "ipg", "ahb", "per";
189 esdhc2: esdhc@50008000 {
190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50008000 0x4000>;
193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
201 uart3: serial@5000c000 {
202 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
203 reg = <0x5000c000 0x4000>;
205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
207 clock-names = "ipg", "per";
211 ecspi1: ecspi@50010000 {
212 #address-cells = <1>;
214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
215 reg = <0x50010000 0x4000>;
217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
219 clock-names = "ipg", "per";
224 compatible = "fsl,imx53-ssi",
227 reg = <0x50014000 0x4000>;
229 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
230 dmas = <&sdma 24 1 0>,
232 dma-names = "rx", "tx";
233 fsl,fifo-depth = <15>;
237 esdhc3: esdhc@50020000 {
238 compatible = "fsl,imx53-esdhc";
239 reg = <0x50020000 0x4000>;
241 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
242 <&clks IMX5_CLK_DUMMY>,
243 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
244 clock-names = "ipg", "ahb", "per";
249 esdhc4: esdhc@50024000 {
250 compatible = "fsl,imx53-esdhc";
251 reg = <0x50024000 0x4000>;
253 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
254 <&clks IMX5_CLK_DUMMY>,
255 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
256 clock-names = "ipg", "ahb", "per";
262 aipstz1: bridge@53f00000 {
263 compatible = "fsl,imx53-aipstz";
264 reg = <0x53f00000 0x60>;
268 compatible = "usb-nop-xceiv";
269 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
270 clock-names = "main_clk";
275 compatible = "usb-nop-xceiv";
276 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
277 clock-names = "main_clk";
281 usbotg: usb@53f80000 {
282 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
283 reg = <0x53f80000 0x0200>;
285 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
286 fsl,usbmisc = <&usbmisc 0>;
287 fsl,usbphy = <&usbphy0>;
291 usbh1: usb@53f80200 {
292 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
293 reg = <0x53f80200 0x0200>;
295 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
296 fsl,usbmisc = <&usbmisc 1>;
297 fsl,usbphy = <&usbphy1>;
301 usbh2: usb@53f80400 {
302 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
303 reg = <0x53f80400 0x0200>;
305 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
306 fsl,usbmisc = <&usbmisc 2>;
310 usbh3: usb@53f80600 {
311 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
312 reg = <0x53f80600 0x0200>;
314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
315 fsl,usbmisc = <&usbmisc 3>;
319 usbmisc: usbmisc@53f80800 {
321 compatible = "fsl,imx53-usbmisc";
322 reg = <0x53f80800 0x200>;
323 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
326 gpio1: gpio@53f84000 {
327 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
328 reg = <0x53f84000 0x4000>;
329 interrupts = <50 51>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
336 gpio2: gpio@53f88000 {
337 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
338 reg = <0x53f88000 0x4000>;
339 interrupts = <52 53>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
346 gpio3: gpio@53f8c000 {
347 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
348 reg = <0x53f8c000 0x4000>;
349 interrupts = <54 55>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
356 gpio4: gpio@53f90000 {
357 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
358 reg = <0x53f90000 0x4000>;
359 interrupts = <56 57>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
367 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
368 reg = <0x53f94000 0x4000>;
370 clocks = <&clks IMX5_CLK_DUMMY>;
374 wdog1: wdog@53f98000 {
375 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
376 reg = <0x53f98000 0x4000>;
378 clocks = <&clks IMX5_CLK_DUMMY>;
381 wdog2: wdog@53f9c000 {
382 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
383 reg = <0x53f9c000 0x4000>;
385 clocks = <&clks IMX5_CLK_DUMMY>;
389 gpt: timer@53fa0000 {
390 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
391 reg = <0x53fa0000 0x4000>;
393 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
394 <&clks IMX5_CLK_GPT_HF_GATE>;
395 clock-names = "ipg", "per";
398 iomuxc: iomuxc@53fa8000 {
399 compatible = "fsl,imx53-iomuxc";
400 reg = <0x53fa8000 0x4000>;
403 gpr: iomuxc-gpr@53fa8000 {
404 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
405 reg = <0x53fa8000 0xc>;
409 #address-cells = <1>;
411 compatible = "fsl,imx53-ldb";
412 reg = <0x53fa8008 0x4>;
414 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
415 <&clks IMX5_CLK_LDB_DI1_SEL>,
416 <&clks IMX5_CLK_IPU_DI0_SEL>,
417 <&clks IMX5_CLK_IPU_DI1_SEL>,
418 <&clks IMX5_CLK_LDB_DI0_GATE>,
419 <&clks IMX5_CLK_LDB_DI1_GATE>;
420 clock-names = "di0_pll", "di1_pll",
421 "di0_sel", "di1_sel",
431 remote-endpoint = <&ipu_di0_lvds0>;
442 remote-endpoint = <&ipu_di1_lvds1>;
450 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
451 reg = <0x53fb4000 0x4000>;
452 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
453 <&clks IMX5_CLK_PWM1_HF_GATE>;
454 clock-names = "ipg", "per";
460 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
461 reg = <0x53fb8000 0x4000>;
462 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
463 <&clks IMX5_CLK_PWM2_HF_GATE>;
464 clock-names = "ipg", "per";
468 uart1: serial@53fbc000 {
469 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
470 reg = <0x53fbc000 0x4000>;
472 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
473 <&clks IMX5_CLK_UART1_PER_GATE>;
474 clock-names = "ipg", "per";
478 uart2: serial@53fc0000 {
479 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
480 reg = <0x53fc0000 0x4000>;
482 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
483 <&clks IMX5_CLK_UART2_PER_GATE>;
484 clock-names = "ipg", "per";
489 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
490 reg = <0x53fc8000 0x4000>;
492 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
493 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
494 clock-names = "ipg", "per";
499 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
500 reg = <0x53fcc000 0x4000>;
502 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
503 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
504 clock-names = "ipg", "per";
509 compatible = "fsl,imx53-src", "fsl,imx51-src";
510 reg = <0x53fd0000 0x4000>;
515 compatible = "fsl,imx53-ccm";
516 reg = <0x53fd4000 0x4000>;
517 interrupts = <0 71 0x04 0 72 0x04>;
521 gpio5: gpio@53fdc000 {
522 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
523 reg = <0x53fdc000 0x4000>;
524 interrupts = <103 104>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gpio6: gpio@53fe0000 {
532 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
533 reg = <0x53fe0000 0x4000>;
534 interrupts = <105 106>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
541 gpio7: gpio@53fe4000 {
542 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
543 reg = <0x53fe4000 0x4000>;
544 interrupts = <107 108>;
547 interrupt-controller;
548 #interrupt-cells = <2>;
552 #address-cells = <1>;
554 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
555 reg = <0x53fec000 0x4000>;
557 clocks = <&clks IMX5_CLK_I2C3_GATE>;
561 uart4: serial@53ff0000 {
562 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
563 reg = <0x53ff0000 0x4000>;
565 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
566 <&clks IMX5_CLK_UART4_PER_GATE>;
567 clock-names = "ipg", "per";
572 aips@60000000 { /* AIPS2 */
573 compatible = "fsl,aips-bus", "simple-bus";
574 #address-cells = <1>;
576 reg = <0x60000000 0x10000000>;
579 aipstz2: bridge@63f00000 {
580 compatible = "fsl,imx53-aipstz";
581 reg = <0x63f00000 0x60>;
585 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
586 reg = <0x63f98000 0x4000>;
588 clocks = <&clks IMX5_CLK_IIM_GATE>;
591 uart5: serial@63f90000 {
592 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
593 reg = <0x63f90000 0x4000>;
595 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
596 <&clks IMX5_CLK_UART5_PER_GATE>;
597 clock-names = "ipg", "per";
601 owire: owire@63fa4000 {
602 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
603 reg = <0x63fa4000 0x4000>;
604 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
608 ecspi2: ecspi@63fac000 {
609 #address-cells = <1>;
611 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
612 reg = <0x63fac000 0x4000>;
614 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
615 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
616 clock-names = "ipg", "per";
620 sdma: sdma@63fb0000 {
621 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
622 reg = <0x63fb0000 0x4000>;
624 clocks = <&clks IMX5_CLK_SDMA_GATE>,
625 <&clks IMX5_CLK_SDMA_GATE>;
626 clock-names = "ipg", "ahb";
628 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
631 cspi: cspi@63fc0000 {
632 #address-cells = <1>;
634 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
635 reg = <0x63fc0000 0x4000>;
637 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
638 <&clks IMX5_CLK_CSPI_IPG_GATE>;
639 clock-names = "ipg", "per";
644 #address-cells = <1>;
646 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
647 reg = <0x63fc4000 0x4000>;
649 clocks = <&clks IMX5_CLK_I2C2_GATE>;
654 #address-cells = <1>;
656 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
657 reg = <0x63fc8000 0x4000>;
659 clocks = <&clks IMX5_CLK_I2C1_GATE>;
664 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
666 reg = <0x63fcc000 0x4000>;
668 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
669 dmas = <&sdma 28 0 0>,
671 dma-names = "rx", "tx";
672 fsl,fifo-depth = <15>;
676 audmux: audmux@63fd0000 {
677 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
678 reg = <0x63fd0000 0x4000>;
683 compatible = "fsl,imx53-nand";
684 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
686 clocks = <&clks IMX5_CLK_NFC_GATE>;
691 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
693 reg = <0x63fe8000 0x4000>;
695 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
696 dmas = <&sdma 46 0 0>,
698 dma-names = "rx", "tx";
699 fsl,fifo-depth = <15>;
703 fec: ethernet@63fec000 {
704 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
705 reg = <0x63fec000 0x4000>;
707 clocks = <&clks IMX5_CLK_FEC_GATE>,
708 <&clks IMX5_CLK_FEC_GATE>,
709 <&clks IMX5_CLK_FEC_GATE>;
710 clock-names = "ipg", "ahb", "ptp";
715 compatible = "fsl,imx53-tve";
716 reg = <0x63ff0000 0x1000>;
718 clocks = <&clks IMX5_CLK_TVE_GATE>,
719 <&clks IMX5_CLK_IPU_DI1_SEL>;
720 clock-names = "tve", "di_sel";
725 remote-endpoint = <&ipu_di1_tve>;
731 compatible = "fsl,imx53-vpu";
732 reg = <0x63ff4000 0x1000>;
734 clocks = <&clks IMX5_CLK_VPU_GATE>,
735 <&clks IMX5_CLK_VPU_GATE>;
736 clock-names = "per", "ahb";
742 ocram: sram@f8000000 {
743 compatible = "mmio-sram";
744 reg = <0xf8000000 0x20000>;
745 clocks = <&clks IMX5_CLK_OCRAM>;